ch-3 vlsi
ch-3 vlsi
Design Constraints:
Speed, power and
area.
1
The VLSI Design Process
Levels of abstraction:
(1) Functional (architecture)
(2) Register Transfer Level (microarchitecture, block)
(3) Logic Design
(4) Circuit Design
(5) Physical Design
2
The VLSI Design Process
Hardware Description
Languages
Verilog, VHDL etc.
VHDL Example: 32 bit
adder
Specificati A B
on
Op
SUM
Behavior
Functional al entity ALU32 is port (
Design Simulati A, B: in bit_vector(31
on if (a=b) then
downto
sum < =0);‘0’ ;
.....)
else end ALU32;
sum < = (a or b);
end if;
3
The VLSI Design Process
mux
zero
?
mux
P
Re
C
Register RTL g Dat
mux
Fil a
Transfer Simulati Inst
I
e Me
mux
R
Level on r
Me
m
Design m Sig store
n
Ex
load
A
B
C E
Logic Design Logic
Simulation Z
D F
Z <= E
OR F
4
The VLSI Design Process
Circuit Timing
Simulati
Design on
Physical Design
Rule
Design Checking
5
What is CMOS?
GND! Input
V DD !
n-substrate p-substrate
A CMOS contact contact
Inverter
polysilicon
Inpu
t n-diffusion p-diffusion
Vdd
GND N P ! (source)
! 1 1
(drain)
Output
Inverter Schematic
n-transistor p-transistor
n-diffusion p-diffusion
contact contact
Inverter Layout
Metal 1
Output
6
Hierarchy and Abstraction
7
Hierarchy and Abstraction
Entire CAD design frameworks are based on this design philosophy.
These have made it possible to achieve current design complexity.
Place-and-Route tools can use these libraries and generate layouts using logic level
8
description of the design.