CLASS 14: JFET AND MOSFET

PRESENTED
BY:
HIRANMAY
MISTRI
ASSISTANT
PROFESSOR,RKMGEC,
PURULIA
 OVERVIEW
 Introduction of Field Effect Transistor (FET)
• JFET
• MOSFET

Junction Field Effect Transistor (JFET)

 Operation of JFET
 Characteristic of JFET
 Parameter of JFET
 Analyzed How JFETs are Biased
N channel P channel
Metal Oxide Semi conductor Field Effect Transistor (MOSFET)
 Operation of MOSFET
 Characteristic of MOSFET E
 Parameter of MOSFET
 Analyzed How MOSFETs are Biased
 Troubleshoot FET circuit
D
2
OVERVIEW Transistor

Bi-Polar
Field Effect
Junction
Transistor
Transistor
(FET)
( BJT)

Junction Field Effect Metal Oxide

Transistor Semiconductor Field
Effect Transistor
(JFET) (MOSFET)
D- E-
MOSFET MOSFET
n p • n • n
channel channel channel channel
• p • p
channel channel
WHY TRANSISTOR IS VERY IMPORTANT IN

OUR TECHNOLOGY ?
ntroduction

FET
BJT • Unipolar devices
• Operate only with
• Bipolar Device one type of charger
used both carrier.
electron and • It is a voltage

VS
hole current. controlled
• Current device(Vgs,Vds).
controlled • Advantages:
• FET is very high
device (Ic,Ib,Ie)
input resistance.
• In switching
applications, FET is
faster than BJTs
when turned on and
off.
5
ntroduction- FET
• FET is a "Unipolar"
device
that depends only on the
conduction
of electrons (N-channel) or
holes
(P-channel).

• FET – a three-terminal
voltage-
controlled device used in
amplification and
switching
Application.

• FET is a voltage-
controlled device.

• FET high input

JFET

JFET

Basic Characteristi
Parameters Biasing
Structure cs

n p
channel channel
FET- Basic Structure
• The terminals of a JFET are the Source (S), Gate
(G), and Drain (D).
• A JFET can be either p channel or n channel.
• The arrow on the gate points “in” for n channel &
“out” for p channel.

JFET Schematic Symbol 8

JFET – Basic Operation
• VDD provide a drain-to-source voltage and
supplies current from Drain to Source (VDS

• VGG sets the reverse-bias voltage between

and source, (VGS).

• JFET is always operated with gate-source

pn-junction reverse-biased.

• GS junction never allowed to become

forward-biased because the gate materi
not designed to handle any significant am
of current.
 it may destroy the component.

9
 JFET

Characteristic Parameters
Basic Structure Biasing
s

DCC TCC
(Drain Characteristic (Transfer Characteristic
Curve) Curve)

X -Axis: VDS (V) X -Axis: - Vgs Equation:

Vgs= 0
Y-Axis: IDS (V)
Vgs= -ve
(mA) Y-Axis: IDS (mA

Data Sheet
1) Typ
2) Max
JFET Characteristic: Drain Characteristic Curve (DCC)
 JFET Characteristics: VGS=0

Case 1: When the gate-to-source voltage, VGS=0V.

is produced by shorting the gate to source junction.

minal Gate and Source, both are grounded.
characteristic of JFET need to be explain deeply by using Dr
aracteristic curve (DCC). 12
 VGS=0 ( JFET Drain Characteristic Curve) ,DCC

Y axis ID Range: 0  IDSS

unit: mA
X axis VDS Range: 0 ∞
unit: V

Point Region Description

A to B Ohmic Region • ID increases proportionally with increases of V DD (VDS increases as VDD increases).
• called the ohmic region VDS and ID are related by Ohm’s Law.

B Pinch-off • The Curve level off.

Voltage, VP • ID becomes essentially constant. (VDS=Vp)
B to C Constant current • ID still constant.
(Active Region) • Because, as VDS ↑, the reverse-bias voltage from gate to drain (VGD) produces a
depletion region large enough to offset the increase in VDS.
• This current is called maximum drain current (IDSS) .

C Breakdown . • Breakdown occur when ID begins to increase rapidly with any increase in VDS.
• Can caused irreversible damage the to the device.
• so JFETs operation is always well below this value. 13
VGS = - ve ( JFET Drain Characteristic Curve) ,DCC
2 : As VGS is set to more – ve value by adjusting VGG

• VGS is set to increasingly

more
negative by adjusting VGG
become
-1V.
• Therefore the value of VGS
become = -1V.
• A Drain Characteristic Curves
is produced.

14
VGS = - ve ( JFET Drain Characteristic Curve) ,DCC

• As VGS is set to more

negative values by
adjusting VGG, the ID
becomes decrease
because of the
narrowing of the
channel.
• VGS =0 and Vp is
benchmark point.
• For each increasing in
negative value of VGS
the JFET reaches of
their own pinch-off
point (where the point15
 JFET Characteristics : Cutoff Voltage, VGS (off)
• The value of VGS will be given in Data
Sheet.
• The value of VGS that makes ID
approximately zero is called Cutoff
voltage, VGS(off) .

• When VGS(off) (a very large –ve value), ID ≈

0.
• When VGS=0, ID= maximum IDSS.

• The JFET must be operated between

VThe operating limits of JFET are:
GS=0 and VGS(off).
ID≈0 VGS=VGS(off)
ID=IDSS VGS = 0

• Pinch-off voltage (Vp) and cutoff

voltage (VGS(off)) are both the same
value, but opposite in sign. 16
 POP QUIZ 1 - SUBMIT

Draw and explain each point

of Drain
Characteristic Curve (DCC).
Hint:
• Axis/unit
• Point A,B,C.(Name the
region).
• Point & Value Pinch off
voltage ,Vp.
 JFET Characteristics ( n vs p channel)
N -channel P -channel

he basic operation of P-channel JFET is the same as for an

n- channel device except:
channel JFET requires a negative VDD and positive VGS
r p-channel, VGS(off) is positive and for n-channel JFET,
GS(off) is negative 18
 POP- QUIZ 2- SUBMIT
For the JFET in Figure below, given VGS(off) = -4V and
IDSS =12mA. Determine minimum value of VDD
required to put the device in the constant-current
Solution:
region of operation when V GS type ofDraw
1) Identify= 0V. channelthe
( n or p type)?
complete DCC for this JFET.
2)List out all the info given:

19
 SUMMARY of DCC
he range of VGS values from zero to VGS(off)  controls the amount o

or n channel JFET VGS(off) is negative.

or p channel JFET VGS(off) is positive.

o that, the relationship between ID and VGS is very importance.

or DCC show value of VGS.

• Y AXIS unit:

• X AXIS unit:

• Equation involved 
 JFET Characteristics :Transfer Characteristics Curve,TCC

• TCC will show the value of ID at certain value of VGS .

• A JFET transfer characteristic curve is expressed
2
approximately as:  VGS 

(Square Law)I D I DSS  1  V 
 GS ( off ) 

nsfer Characteristic Curve,TCC • ID can be determined

for any VGS if VGS(off)
and IDSS are known.

• VGS(off) and IDSS are

usually available
from the JFET
datasheet.
Y axis ID Range: 0  IDSS unit: mA
X axis -VGS Range: 0 VGS(off) unit:
21
• Transfer characteristic curve (blue) can be
developed from Drain characteristic curves
(green) by plotting values of ID for the values of
VGS taken from drain curves at pinch-off, Vp.

• When VGS = - 2V, ID = 4.32mA.

• When VGS = 0V, ID = IDSS = 12mA. 22
SUMMARY OF TTC

• Y AXIS ID Range: 0  IDSS unit: mA

• X AXIS -VGS Range: 0 VGS(off) unit: V

2
• Equation involved   
 VGS 
Square Law I D I DSS 1 
 V 
 GS ( off ) 
 JFET

Basic Characteristic
Parameters Biasing
Structure s

Forward
Input
Transconductance,
Resistance,Rin
gm
JFET Parameters: Forward Transconductance

• Forward Transfer Conductance, gm is the changes

in drain current (ΔID) based on changes in gate-to-
source voltage (ΔVGS) with VDS is constant.
• The value is larger at the top of the curve (near
VGS=0) but become smaller as you increase VGS (near
VGS(off)).

25
• A data sheet normally gives the value gmo @ gfs, and then we
can calculate an approximate value for gm using at any point on
the transfer characteristic curve by using:

• Unit: Siemens (S)

• When the value of gm0 is not available in data sheet , it can be

calculate using this formula:

26
 POP-QUIZ 5
Q5) By refering data sheet for a 2N5457 JFET. Determine
transconductance for VGS = -4V and find ID at this point.

27
 JFET Parameters : Input Resistance, Rin

• Since JFET operates with GS-junction reverse-biased

for operation , which makes the input resistance (Rin)
becomes so large at the gate.

• This high input resistance is one advantage of using

JFET over BJT.

• This input resistance Rin can be calculated at different

VGS using :

Where:
IGSS = Gate Reverse Current (if not given refer data
sheet)

28
 6.3. JFET Biasing
JFET

Basic
Characteris Paramet Biasing
Structur
tics ers
e

Voltage Current
Mid point Divider Source
Self- Bias Gate Bias
Bias Bias Bias

1) Circuit
2) Q point
3) Advantage & Disadvantage 29
SELF- BIAS
JFET
Bias
Circuit

Self- Voltage
Mid point Current
Gate Bias Divider
Bias Bias
Bias
Source Bias

Q Advantages
Circuit point &
Is = ID (VGS,ID Disadvantag
) es
ET Biasing- 1) Self bias
• Self-bias is the most common type of biasing method for JFETs.
• JFET must be operated such that the gate-source junction is
always reverse biased.
• To keep the GS-junction reverse biased:
• It can be achieved using self-bias arrangement as shown in
figure below.
(a). VGS will be -ve for n-channel JFET (b). VGS will be
+ve for p-channel JFET.
• The gate resistor, RG : not affect the bias because it has
essentially no volt drop across it.
• Therefore, the gate remains 0V.
• RG only to force the gate to be 0V and isolate an
ac signal from ground in amplifier applications.
31
• Self-biased JFETs:
For n-channel JFET
• IS through RS produces a voltage drop,
making the Source +ve with respect to
ground.
• Since, IS = ID and VG = 0, VS = IDRS.

• So: VGS = VG – VS = 0 – IDRS

 (n channel) VGS = -IDRS

For p-channel JFET

• IS through RS produces a –ve voltage at
Source, making the Gate +ve with
respect to ground.
• Since, IS = ID, and VG = 0, -VS = –IDRS32
• For the drain voltage (VD) with respect to ground is
determined as follows:

KVL Drain to Source:

+
∴ 𝑉 𝑆=𝐼 𝐷 𝑅 𝑆

33
KVL Drain to Source:

KVL Gate to Source:

34
SELF- BIAS
JFET
Bias
Circuit

Self- Voltage
Mid point Current
Gate Bias Divider
Bias Bias
Bias
Source Bias

Q
Circuit point
Is = ID (VGS,ID
)
elf bias - Q-Point
• The basic approach to establishing a JFET bias
point is to determine the ID for a desired value
of Va
• For GS or vice versa.
desired value of V , I can be determined
GS D
from:
(a) Transfer characteristic curve
(b) Formula:

• Then, calculate the required value of RS using

the following relationship.

36
 POP- QUIZ 8 ( Using Formula)
Determine the value of RS required to self
bias
a n channel JFET with IDSS = 10mA and

VGS(off) = -15V. VGS is to be -5V.

37
P- QUIZ 9(Using Transfer Characteristic
Determine the value of RS required to self
bias
a n channel JFET that has the transfer
characteristic curve shown below at V GS= -
5V.
Q point:
ID (mA)
VGS= -5 V
ID= ??

-VGS(V) 38
f bias – Biasing-graphical Ana
• The Transfer characteristic curve of a JFET
can be use to determine the Q point ( ID and
VGS) of self bias circuit.
• To determine the Q point:
– Make a self-bias DC load line on the graph of
• Transfer
First, Characteristic
establish dc load line by:
given.
i) calculating VGS when ID=0.
ii) calculate VGS when ID=IDSS
ID= 0 VGS=-IDRS

ID=IDSS. VGS=-IDRS

• With 2 points, draw dc load line on the transfer characteristic

39
• First, establish dc load line by:
i) calculating VGS when ID=0.
ii) calculate VGS when ID=IDSS

ID= 0 VGS=-IDRS  ID= 0

= (0)(470Ω) VGS = 0 V
=0V
ID=IDSS. VGS=-IDRS  ID=IDSS.
= (10mA) VGS=-
(470Ω) 4.7V
= - 4.7V

• With 2 points, draw dc load line on the transfer

characteristic curve.

40
• The point where the line intersect the transfer
characteristic curve is the Q-point of the circuit.
41
 JFET
Bias Circuit

Mid Voltage Current

Gate Divider Source
Self-Bias point
Bias Bias Bias
Bias

Circuit
Q point
ID = (VGS,ID)
0.5IDSS
elf bias – Midpoint Bias
• Midpoint biasing – It is usually desirable to
bias a JFET near the midpoint of its transfer
characteristic curve (TCC) where ID = 0.5IDSS
when VGS= VGS(off)/ 3.4.
• Under signal condition, midpoint bias allows
the max amount of drain current swing
between 0 and IDSS.
ID = 0.5IDSS and
• Midpoint biasing

• By selecting VGS = VGS(off) /3.4  should get a

midpoint bias in terms of ID . 43
• To set the Drain Voltage (VD) at midpoint :

(to select a value of RD to produce the desired

voltage drop.)

• The value of RD needed can be determined by

taking half of VDD and dividing it by ID:

• RG, it’s value is arbitrarily large to prevent

loading on the driving stage in a cascaded
44
Midpoint biasing:
ID = 0.5IDSS
 JFET
Bias Circuit

Mid Voltage Current

Self-Bias
Gate Divider Source
point
Bias Bias Bias
Bias

Circuit
ET Biasing- 2) Gate- bias
• Gate supply voltage (-VGG)
is used to ensure GS-
junction is reverse-biased.

• Since there is no gate

current (IG), there is no
voltage dropped across RG.
So, VGS = -VGG.

• RG  to prevent input
signal from being shorted
to gate supply through low
reactance of input coupling
capacitor. 47
• To find ID:

Disadvantage
Gate bias does not provide a stable
Q-point value of ID from one JFET to
another.
48
 JFET
Bias Circuit

Voltag
Mid Current
Gate e
Self-Bias point Source
Bias Divider
Bias Bias
Bias

Q point
Circuit
(VGS,ID)
T Biasing- 3) Voltage-Divider bias
• The voltage at source, VS of the
JFET must be more +ve than
the voltage at gate,VG in order to
keep the GS-junction reverse
bias. Since ID=IS.

• Source voltage:

• Gate voltage:

• Gate-to-source voltage:

N channel JFET VDB • Source voltage: 50

tage Divider Bias – Biasing-graphical(Q point)

• By using the transfer characteristic

curve to determine the approximate Q-
point, we must establish the two
points for the DC load line.
ID= 0 VGS=VG-VS  ID= 0
1st point: VS = ID RS = (0)(RS) VGS = VG
VGS=VG-VS = VG – 0= VG
VGS=0 VGS=ID = VG - VGs = VG  VGS=0
2nd point: RS RS ID=VG
RS .

51
• The point at which the DC load line intersect
with transfer characteristic curve is Q-
point.
52
 Solution:
ID= 0 VGS=VG-VS  ID= 0
1st point: VS = ID RS = (0)(RS) VGS = VG
VGS=VG-VS = VG – 0= VG
VGS=0 ID = VG - VGs = VG  VGS=0
2nd point: RS RS ID=VG
RS .

For 1st point:

2nd point:

53
 ID= 0 VGS=VG  ID= 0
1st point:
VGS =

VGS=0 ID = VG - VGs = VG  VGS=0

2nd point: RS RS ID=VG =
RS .

Ans:

54
 JFET
Bias Circuit

Mid Voltage Current

Gate
Self-Bias point Divider Source
Bias
Bias Bias Bias

Circuit
T Biasing- 3) Current Source - Bias
• Current source bias: for
increasing Q-point stability of self
biased JFET by making value of ID
independently of VGS
• It can be accomplished by using
constant current source in series
with JFET source.
• From figure, BJT acts as constant –
current because IE is constant if
VEE>>VBE.
• FET also can be used as constant
current source. ID=
IE = VEE - VBE = VEE IE
RE RE
• ID= IE ( ID remains constant for
any transfer characteristic curve
as indicated by the horizontal line 56
Advantage
• provide the most
stable Q-point
value of ID.

Disadvantage
• circuit complexity
makes it
undesirable for
most applications.
57
 Structure: n-channel MOSFET
(NMOS)
gate: metal or heavily doped poly-Si
G
(bulk or body source IG=0 drain
substrate) B S D
y ID=IS
IS

metal
oxide

n+ n+
p
x

W
L
Circuit Symbol (NMOS)
enhancement-type: no channel at zero gate voltage

D
ID= IS

G B (IB=0, should be reverse biased)

IG= 0

IS G-Gate
D-Drain
S-Source
S B-Substrate or Body
 Structure: n-channel MOSFET
(NMOS)
gate: metal or heavily doped poly-Si
G
(bulk or body source IG=0 drain
substrate) B S D
y ID=IS
IS

metal
oxide

n+ n+
p
x

W
L
 Energy bands
(“flat band” condition; not equilibrium) (equilibrium)
Flatbands! For this choice of materials, VGS<0
n+pn+ structure  ID ~ 0
gate
G
body source drain
B S - + D
VD=Vs

n++
oxide

n+ n+
p

W
L
Flatbands < VGS < VT (Includes
VGS=0 here). n+-depletion-n+
structure  ID ~ 0
gate
G
body source drain
B S - + D
VD=Vs

+++
n++
oxide

n+ n+
p

W
L
 VGS > VT
n+-n-n+ structure  inversion
gate
G
body source drain
B S - + D
VD=Vs
+++
+++
+++
n++
oxide
-----
n+ n+
p

W
L
 Channel Charge (Qch)

VGS>VT
Depletion region
charge (QB) is due
to uncovered acceptor ions

Qch
 n++
n+ n+
p

W
L

(x)

Ec(y) with VDS=0

Triode Region
A voltage-controlled resistor @small VDS

B S D
-+ ID
+++ VGS1>Vt increasing
+++
metal VGS
- oxide
- - -
n+ n+
p

B S -+ D

+++ VGS2>VGS1
+++
+++
metal G
- -oxide
- - --
n+ n+
p
VDS
cut-off
B S -+ D 0.1 v
+++ VGS3>VGS2
++++++ Increasing VGS puts more charge
+++
metal
- - -oxide
------ in the channel, allowing more
n+ n+
p drain current to flow
Saturation Region
occurs at large VDS
As the drain voltage increases, the difference in
voltage between the drain and the gate becomes
smaller. At some point, the difference is too small to
maintain the channel near the drain  pinch-off

gate
G
body source drain
+
B S - D
VDS large
+++
+++
+++
metal
oxide

n+ n+
p
 Saturation Region
occurs at large VDS
The saturation region is when the MOSFET
experiences pinch-off.
Pinch-off occurs when VG - VD is less than VT.

gate
G
body source drain
+
B S - D
VDS large
+++
+++
+++
metal
oxide

n+ n+
p
 Saturation Region
occurs at large VDS
VGS - VDS < VT or VGD < VT
VDS > VGS - VT

gate
G
body source drain
+
B S - D
VD>>Vs
+++
+++
+++
metal
oxide

n+ n+
p
Saturation Region
once pinch-off occurs, there is no further increase in drain current
saturation
ID
triode

increasing VDS>VGS-VT
VGS VDS<VGS-VT

VDS

0.1 v
Band diagram of triode and saturation
Simplified MOSFET I-V Equations
Cut-off: VGS< VT
ID = IS = 0
Triode: VGS>VT and VDS < VGS-VT
ID = kn’(W/L)[(VGS-VT)VDS - 1/2VDS2]
Saturation: VGS>VT and VDS > VGS-VT
ID = 1/2kn’(W/L)(VGS-VT)2

where kn’= (electron mobility)x(gate capacitance)

= mn(eox/tox) …electron velocity = mnE
and VT depends on the doping concentration and gate
material used (…more details later)
 Energy bands
(“flat band” condition; not equilibrium) (equilibrium)
 Channel Charge (Qch)

VGS>VT
Depletion region
charge (QB) is due
to uncovered acceptor ions

Qch
Threshold Voltage Definition
VGS = VT when the carrier
concentration in the channel
is equal to the carrier
concentration in the bulk
silicon.

Mathematically, this occurs

when fs=2ff ,
where fs is called the
surface potential