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w7 ARM Flow Control

Chapter 6 covers flow control in assembly language, focusing on control structures such as selection (if-then-else) and loops (while and for). It explains condition flags and how to update them using various instructions like CMP, TST, and branch instructions. The chapter also discusses unconditional branch instructions and condition codes for signed and unsigned comparisons.

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tarihi seyir
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0% found this document useful (0 votes)
5 views44 pages

w7 ARM Flow Control

Chapter 6 covers flow control in assembly language, focusing on control structures such as selection (if-then-else) and loops (while and for). It explains condition flags and how to update them using various instructions like CMP, TST, and branch instructions. The chapter also discusses unconditional branch instructions and condition codes for signed and unsigned comparisons.

Uploaded by

tarihi seyir
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Chapter 6

Flow Control in Assembly

BLM19206-BLM22270 Mikroişlemci Sistemleri-


EEM19216-EEM22216 Mikroişlemciler

Dr. Musa Aydın - 2025

1
Overview
 If-then-else
 While loop
 For loop

2
Three Control Structures
 Selection Structure
 If-then-else
 Loop Structure
 while loop
 for loop

Sequence Selection Structure Loop Structure


Structure
3
Review: Condition Flags
Program Status Register (PSR)
N Z C V Q ICI/IT T Reserved GE Reserved ICI/IT ISR number

 Negative bit
 N = 1 if most significant bit of result is 1
 Zero bit
 Z = 1 if all bits of result are 0
 Carry bit
 For unsigned addition, C = 1 if carry takes place
 For unsigned subtraction, C = 0 (carry = not borrow) if borrow takes
place
 For shift/rotation, C = last bit shifted out
 oVerflow bit
 V = 1 if adding 2 same-signed numbers produces a result with the
opposite sign
 Positive + Positive = Negative, or
Negative + negative = Positive

4 
Non-arithmetic operations does not touch V bit, such as
Updating Condition Flags
 Method 1: append with “S”
 ADD r0,r1,r2 → ADDS r0,r1,r2
 SUB r0,r1,r2 → SUBS r0, r1, r2

 Method 2: using compare instructions


Instructi Brief
Flags
on description
CMP Compare N,Z,C,V
Compare
CMN Negative
N,Z,C,V

TEQ Test Equivalence N,Z,C


TST Test N,Z,C

5
Comparison Instructions
Instructi Brief
Operands Flags
on description
CMP Rn, Op2 Compare N,Z,C,V
Compare
CMN Rn, Op2 N,Z,C,V
Negative
TEQ Rn, Op2 Test Equivalence N,Z,C
 The only effect of the comparisons is to update the
TST Rn, Op2 Test N,Z,C
condition flags.
• No need to set S bit.
• No need to specify Rd.
 Operations are:
• CMP operand1 - operand2, but result not written
• CMN operand1 + operand2, but result not written
• TST operand1 & operand2, but result not written
• TEQ operand1 ^ operand2, but result not written
 Examples:
• CMP r0, r1
• TST r2, #5

6
CMP and CMN
CMP{cond} Rn, Operand2
CMN{cond} Rn, Operand2

 The CMP instruction subtracts the value of Operand2 from


the value in Rn.
 This is the same as a SUBS instruction, except that the result is
discarded.
 The CMN instruction adds the value of Operand2 to the
value in Rn.
 This is the same as an ADDS instruction, except that the result is
discarded.
 These instructions update the N, Z, C and V flags according
to the result.

7
Updating Condition Flags:
CMP and CMN

CMP Rn, Operand2


CMN Rn, Operand2

 Update N, Z, C and V according to the result


 CMP subtracts Operand2 from Rn.
 Same as SUBS, except result is discarded.
 CMN adds Operand2 to Rn.
 Same as ADDS, except result is discarded.

8
Example of CMP

𝑓 ( 𝑥 ) =¿ 𝑥∨¿
Area absolute, CODE, READONLY
EXPORT __main
ENTRY

__main PROC
CMP r1, #0
RSBLT r0, r1, #0

done B done ; deadloop

ENDP
END

Note: RSB = Reverse SuBtract


9
TST and TEQ
TST{cond} Rn, Operand2 ; Bitwise AND
TEQ{cond} Rn, Operand2 ; Bitwise Exclusive OR

 The TST instruction performs a bitwise AND operation on the


value in Rn and the value of Operand2.
 This is the same as a ANDS instruction, except that the result is
discarded.
 The TEQ instruction performs a bitwise Exclusive OR operation
on the value in Rn and the value of Operand2.
 This is the same as a EORS instruction, except that the result is
discarded.
 Update the N and Z flags according to the result
 Can update the C flag during the calculation of Operand2
 Do not affect the V flag.

10
Unconditional Branch Instructions
Instructi Operand
Brief description
on s
B label Branch
BL label Branch with Link
BLX Rm Branch indirect with Link
BX Rm Branch indirect
 B label
 cause a branch to label.
 BL label
 copy the address of the next instruction into r14 (lr, the link register), and
 cause a branch to label.
 BX Rm
 branch to the address held in Rm
 BLX Rm:
 copy the address of the next instruction into r14 (lr, the link register) and
 branch to the address held in Rm

11
Unconditional Branch Instructions:
A Simple Example

MOVS r1, #1
B target ; Branch to target
MOVS r2, #2 ; Not executed
MOVS r3, #3 ; Not executed
MOVS r4, #4 ; Not executed
target MOVS r5, #5

 A label marks the location of an instruction


 Labels helps human to read the code
 In machine program, labels are converted to numeric offsets by
assembler

12
Branch With Link
 The "Branch with link (BL)" instruction
implements a subroutine call by writing PC-
4 into the LR of the current bank.
 i.e. the address of the next instruction following
the branch with link (allowing for the pipeline).
 To return from subroutine, simply need to
restore the PC from the LR:
 MOV pc, lr
 Again, pipeline has to refill before execution
continues.
 The "Branch" instruction does not affect
LR.
13
Condition Codes
Suffix Description Flags tested
EQ EQual
NE Not Equal
CS/HS Unsigned Higher or Same
CC/LO Unsigned LOwer
MI MInus (Negative)
PL PLus (Positive or Zero)
VS oVerflow Set
VC oVerflow Clear
HI Unsigned HIgher
LS Unsigned Lower or Same
GE Signed Greater or Equal
LT Signed Less Than
GT Signed Greater Than
LE Signed Less than or Equal
AL ALways
Note AL is the default and does not need to be specified

14
Condition Codes
 The possible condition codes are listed below:
Suffix Description Flags tested
EQ EQual Z=1
NE Not Equal Z=0
CS/HS Unsigned Higher or Same C=1
CC/LO Unsigned LOwer C=0
MI MInus (Negative) N=1
PL PLus (Positive or Zero) N=0
VS oVerflow Set V=1
VC oVerflow Clear V=0
HI Unsigned HIgher C=1 & Z=0
LS Unsigned Lower or Same C=0 or Z=1
GE Signed Greater or Equal N=V
LT Signed Less Than N!=V
GT Signed Greater Than Z=0 & N=V
LE Signed Less than or Equal Z=1 or N!=V
AL ALways
Note AL is the default and does not need to be specified
15
Signed Greater or Equal ( N == V)
CMP r0, r1
We in fact perform subtraction r0 – r1, without saving the result.
N = 0 N = 1
V = 0 • No overflow, implying the • No overflow, implying the
result is correct. result is correct.
• The result is non-negative, • The result is negative.
• Thus r0 – r1 ≥ 0, i.e., r0 ≥ r1 • Thus r0 – r1 < 0, i.e., r0 < r1

V = 1 • Overflow occurs, implying • Overflow occurs, implying the


the result is incorrect. result is incorrect.
• The result is mistakenly • The result is mistakenly
reported as non-negative reported as negative and in
and in fact it should be fact it should be non-negative.
negative. • Thus r0 – r1 ≥ 0 in reality., i.e.
• Thus r0 – r1 < 0 in reality, r0 ≥ r1
i.e., r0 < r1
Conclusions:
• If N == V, then it is signed greater or equal (GE).
• Otherwise, it is signed less than (LT)
16
Signed Greater or Equal (N == V)
CMP r0, r1
perform subtraction r0 – r1, without saving the result
N = 0 N = 1

V = 0 r0 ≥ r1 r0 < r1

V = 1 r0 < r1 r0 ≥ r1

Conclusions:
• If N == V, then it is signed greater or equal (GE).
• Otherwise, it is signed less than (LT)
17
Signed Greater or Equal (N == V)
CMP r0, r1
perform subtraction r0 – r1, without saving the result
N = 0 N = 1

V = 0 1 0

V = 1 0 1

Conclusions:
• If N == V, then it is signed greater or equal (GE).
• Otherwise, it is signed less than (LT)
18
Signed vs. Unsigned Comparison
Conditional codes applied
to branch instructions
Compare Signed Unsigned Compare Signed Unsigned
> GT HI > BGT BHI
≥ GE HS >= BGE BHS
< LT LO < BLT BLO
≤ LE LS <= BLE BLS
== EQ == BEQ
≠ NE != BNE

19
Signed vs. Unsigned
Conditional codes applied to branch instructions

Compare Signed Unsigned Compare Signed Unsigned


== EQ EQ == BEQ BEQ
≠ NE NE != BNE BNE
> GT HI > BGT BHI
≥ GE HS >= BGE BHS
< LT LO < BLT BLO
≤ LE LS <= BLE BLS

20
Branch Instructions
Instruction Description Flags tested
Unconditio B label Branch to label
nal Branch
BEQ label Branch if EQual Z = 1
BNE label Branch if Not Equal Z = 0
BCS/BHS label Branch if unsigned Higher or C = 1
Same
BCC/BLO label Branch if unsigned LOwer C = 0
BMI label Branch if MInus (Negative) N = 1
BPL label Branch if PLus (Positive or N = 0
Zero)
BVS label Branch if oVerflow Set V = 1
Conditional
Branch BVC label Branch if oVerflow Clear V = 0
BHI label Branch if unsigned HIgher C = 1 & Z = 0
BLS label Branch if unsigned Lower or C = 0 or Z = 1
Same
BGE label Branch if signed Greater or N = V
Equal
BLT label Branch if signed Less Than N != V
21 BGT label Branch if signed Greater Than Z = 0 & N = V
BLE label Branch if signed Less than or Z = 1 or N = !
Number Interpretation
Which is greater?
0xFFFFFFFF or 0x00000001

 If they represent signed numbers, the latter is


greater
(1 > -1).
 If they represent unsigned numbers, the former
is greater
(4294967295 > 1).

22
Which is Greater: 0xFFFFFFFF or
0x00000001?
software’s responsibility to tell computer how to interpret data:
written in C, declare the signed vs unsigned variable
written in Assembly, use signed vs unsigned branch instructions
signed int x, y ; MOVS r6,
x = -1; #0xFFFFFFFF
y = 1; MOVS r5,
if (x > y) #0x00000001
... CMP r5, r6
BLE: Branch if less thanBLE Then_Clause
or equal, signed ≤
...
unsigned int x, MOVS r6,
y ; #0xFFFFFFFF
x = 4294967295; MOVS r5,
y = 1; #0x00000001
if (x > y) CMP r5, r6
BLS unsigned
... BLS: Branch if lower or same, Then_Clause

23 ...
If-then Statement

C Program
if (a < 0 ) {
a = 0 – a;
}
x = x + 1;

Implementation 1:

; r1 = a, r2 = x
CMP r1, #0 ; Compare a with 0
BGE endif ; Go to endif if a
≥ 0
then RSB r1, r1, #0 ; a = - a
endif ADD r2, r2, #1 ; x = x + 1
24
If-then Statement

C Program
if (a < 0 ) {
a = 0 – a;
}
x = x + 1;

Implementation 2:

; r1 = a, r2 = x
CMP r1, #0 ; Compare a with 0
RSBLT r1, r1, #0 ; a = 0 - a if a <
0
ADD r2, r2, #1 ; x = x + 1

25
Compound Boolean Expression
x > 20 && x < 25
x == 20 || x == 25
!(x == 20 || x == 25)

C Program Assembly Program


// x is a signed ; r0 = x
integer CMP r0, #20 ; compare x and 20
if(x <= 20 || x >= 25) BLE then ; go to then if x ≤
{ 20
a = 1 CMP r0, #25 ; compare x and 25
} BLT endif ; go to endif if x <
25
then MOV r1, #1 ; a = 1
endif

26
If-then-else

C Program
if (a ==
1)
b = 3;
else
b = 4;

; r1 = a, r2 = b
CMP r1, #1 ; compare a and 1
BNE else ; go to else if a ≠
1
then MOV r2, #3 ; b = 3
B endif ; go to endif
else MOV r2, #4 ; b = 4
endif
27
For Loop

C Program
int i;
int sum = 0;
for(i = 0; i < 10; i+
+){
sum += i;
}

Implementation 1:
MOV r0, #0 ; i
MOV r1, #0 ; sum

B check
loop ADD r1, r1, r0
ADD r0, r0, #1
check CMP r0, #10
BLT loop
28 endloop
For Loop

C Program
int i;
int sum = 0;
for(i = 0; i < 10; i+
+){
sum += i;
}

Implementation 2:
MOV r0, #0 ; i
MOV r1, #0 ; sum

loop CMP r0, #10


BGE endloop
ADD r1, r1, r0
ADD r0, r0, #1
B loop
29 endloop
Combined Program Status Registers (xPSR)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

N Z C V Q IT[7:6] T Reserved IT[5:0] Interrupt/Exception Number

Reserved

Thumb state flag IT[7:0]: If-Then bits

Stick saturation flag for SSAT and USAT

Overflow flag

Carry/Borrow flag

Zero flag

Negative or less than flag

30
Combined Program Status Registers
(xPSR)
Application PSR Reserved
(APSR)
N Z C V Q

Interrupt PSR Reserved ISR number


(IPSR)

Execution PSR Reserved


ICI/IT T ICI/IT
(PSR)

Combined PSR Reserved ISR number


(xPSR)
N Z C V Q ICI/IT T ICI/IT

bit31 bit24 bit16 bit8 bit0


Condition Codes
 The possible condition codes are listed below:
Suffix Description Flags tested
EQ Equal Z=1
NE Not equal Z=0
CS/HS Unsigned higher or same C=1
CC/LO Unsigned lower C=0
MI Negative N=1
PL Positive or Zero N=0
VS Overflow V=1
VC No overflow V=0
HI Unsigned higher C=1 & Z=0
LS Unsigned lower or same C=0 or Z=1
GE Signed Greater or equal N=V
LT Signed Less than N!=V
GT Signed Greater than Z=0 & N=V
LE Signed Less than or equalZ=1 or N!=V
AL Always
Note AL is the default and does not need to be specified
32
Conditional Execution

Add instruction Condition Flag tested


ADDEQ r3, r2, Add if EQual Add if Z = 1
r1
ADDNE r3, r2, Add if Not Equal Add if Z = 0
r1
ADDHS r3, r2, Add if Unsigned Higher or Same Add if C = 1
r1
ADDLO r3, r2, Add if Unsigned LOwer Add if C = 0
r1
ADDMI r3, r2, Add if Minus (Negative) Add if N = 1
r1
ADDPL r3, r2, Add if PLus (Positive or Zero) Add if N = 0
r1
ADDVS r3, r2, Add if oVerflow Set Add if V = 1
r1
ADDVC r3, r2, Add if oVerflow Clear Add if V = 0
r1
ADDHI r3, r2, Add if Unsigned HIgher Add if C = 1 & Z = 0
r1
ADDLS r3, r2, Add if Unsigned Lower or Same Add if C = 0 or Z =
r1 33 1
ADDGE r3, r2, Add if Signed Greater or Equal Add if N = V
Conditional Execution
a ⟶ r0
y ⟶ r1
if (a <= 0)
CMP r0, #0
y = -1;
MOVLE r1, #-1 ; executed if
else
LE
y = 1;
MOVGT r1, #1 ; executed if
GT
CMP r0, #0 LE: Signed Less than or Equal
BGT else GT: Signed Greater Than
MOV r1, #-1
B son
else
MOV r1, #1
son

34
Conditional Execution

a ⟶ r0
y ⟶ r1
CMP r0, #1
if (a==1 || a==7 || a==11)
CMPNE r0, #7 ; executed if r0 !
y = 1;
= 1
else
CMPNE r0, #11 ; executed if r0 !
y = -1;
= 7
MOVEQ r1, #1
MOVNE r1, #-1
NE: Not Equal
EQ: Equal

35
Compound Boolean Expression
C Program Assembly Program

// x is a signed ; r0 = x, r1 = a
integer CMP r0, #20 ; compare x and 20
if(x <= 20 || x >= 25) MOVLE r1, #1 ; a=1 if less or
{ equal
a = 1; CMP r0, #25 ; CMP if greater than
} MOVGE r1, #1 ; a=1 if greater or
equal
CMP r1, #20 endif
BLE islem
CMP r1, #25
BLO son

islem
MOV r2, #1

son
end1 B end1

36
Example 1: Greatest Common Divider
(GCD)
Euclid’s Algorithm
uint32_t a, b;
while (a != b ) { gcd CMP r0, r1
if (a > b) SUBHI r0, r0, r1
a = a – b; SUBLO r1, r1, r0
else BNE gcd
b = b – a;
}

; suppose r0 = a and r1 = b
gcd CMP r0, r1 ; a >
b?
BEQ end ; if a = b,
done
BLO less ; a < b
SUB r0, r0, r1 ; a = a – b
B gcd
less SUB r1, r1, r0 ; b = b – a
B gcd
end
37
Example 2

int foo(int x, int y) foo ADDS r0, r0, r1


{ BPL PosOrZ
if ( x + y < 0 ) done MOV r0, #0
return 0; MOV pc, lr
else PosOrZ MOV r0, r1
return 1; B done
}

foo ADDS r0, r0, r1 ; r1 = x + y, setting CCs


MOVPL r0, #1 ; return 1 if n bit = 0
MOVMI r0, #0 ; return 0 if n bit = 1
MOV pc, lr ; exit foo function

38
Combination
Instructi Fla
Operands Brief description
on gs
CBZ Rn, label Compare and Branch if Zero -
Compare and Branch if Non
CBNZ Rn, label -
Zero
 Except that it does not change the condition code flags, CBZ
Rn, label is equivalent to:
CMP Rn, #0
BEQ label
 Except that it does not change the condition code flags,
CBNZ Rn, label is equivalent to:
CMP Rn, #0
BNE label

39
Break and Continue

Example code for break Example code for continue


for(int i = 0; i < 5; i++){ for(int i = 0; i < 5; i++){
if (i == 2) break; if (i == 2) continue;
printf(“%d, ”, i) printf(“%d, ”, i)
} }

Output: ?? Output: ??

40
Break and Continue

Example code for break Example code for continue


for(int i = 0; i < 5; i++){ for(int i = 0; i < 5; i++){
if (i == 2) break; if (i == 2) continue;
printf(“%d, ”, i) printf(“%d, ”, i)
} }

Output: 0, 1, Output: 0, 1, 3, 4

41
Break and Continue

C Program Assembly Program


// Find string length ; r0 = string memory
char str[] = "hello"; address
int len = 0; ; r1 = string length
MOV r1, #0 ; len =
for( ; ; ) { 0
if (*str == '\0')
break; loop LDRB r2, [r0]
str++; CBNZ r2, notZero
len++; B endloop
} notZero ADD r0, r0, #1 ; str++
ADD r1, r1, #1 ; len++
B loop
endloop

42
Branch Instructions
Instructio Flag
Operands Brief description
n s
B label Branch -
BL label Branch with Link -
BLX Rm Branch indirect with Link -
BX Rm Branch indirect -
 B label: causes a branch to label.
 BL label: instruction copies the address of the next
instruction into r14 (lr, the link register), and causes a
branch to label.
 BX Rm: branch to the address held in Rm
 BLX Rm: copies the address of the next instruction into r14
(lr, the link register) and branch to the address held in Rm

43
 Reference:
 Embedded Systems with ARM Cortex-
M Microcontrollers in Assembly
Language and C 3rd

Dr. Yifeng Zhu


Electrical and Computer Engineering
University of Maine

44

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