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Data Tranfer Techinques

This document discusses different techniques for transferring data between a microprocessor and input/output devices. It describes synchronous and asynchronous data transfer formats. It also discusses parallel and serial modes of data transfer. The document outlines programmed and interrupt-driven data transfer schemes controlled by the microprocessor, as well as device-controlled DMA (direct memory access) transfers. DMA transfers allow fast direct transfer of data between I/O devices and memory without involving the microprocessor.

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Sanchi Goyal
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76 views

Data Tranfer Techinques

This document discusses different techniques for transferring data between a microprocessor and input/output devices. It describes synchronous and asynchronous data transfer formats. It also discusses parallel and serial modes of data transfer. The document outlines programmed and interrupt-driven data transfer schemes controlled by the microprocessor, as well as device-controlled DMA (direct memory access) transfers. DMA transfers allow fast direct transfer of data between I/O devices and memory without involving the microprocessor.

Uploaded by

Sanchi Goyal
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Data Transfer Techniques

FORMATS OF DATA TRANSFER


Synchronous Data Transfer: Synchronous means at the same time. In this format of data transfer transmitter and receiver device are synchronized with the same clock pulse. This type of data transfer format is used in between the devices that match in speed. This method is invariably used in between memory and microprocessor as they are compatible. Asynchronous Data Transfer: Asynchronous means at a regular interval. In this method data transfer is not based on predetermined timing pattern in this technique the status of the IO device is checked by the microprocessor before the data is transferred. This method is invariably used in between microprocessor and IO devices.

MODES OF DATA TRANSFER


THE MICROPROCESSOR receives or transmits binary data in either of two mode:-

PARALLEL MODE:- In a parallel mode , the entire word is transferred at one time .the device commonly used for data transfer are keyboards seven segment LEDs data converters and memory. SERIAL MODE:- In the serial mode , data are transferred one bit at a time over a single line between the microprocessors and a peripheral. It is commonly used with peripherals such as CRT terminals , printers, cassette tapes and modems for telephone.

NEEDS OF DATA TRANSFER SCHEME


A wide variety of IO devices having wide range of speed and other different characteristics are available .A slow responding IO device cannot transfer data when microprocessor issues instruction for it as it takes some time to get ready. Data codes and formats in peripheral differ from the word format of in the c.p.u and memory Transfers rates of peripherals is usually slower than the transfer rates of c.p.u. Operating modes of peripheral are different from each other and each must be controlled so as not to disturb the operation of each other peripherals connected to c.p.u

TYPES OF DATA TRANSFER SCHEME


Different types of data transfer techniques are available which can be broadly divided into two categories:-

MICROPROCESSOR CONTROLLED :- HERE data transfer is controlled by microprocessor. Microprocessor is primarily responsible for data transfer whether from I/o to the c.p.u or to the memory or vice versa . DEVICE CONTROLLED:- Here data transfer is controlled by IO device .data is transferred in between IO device and memory without the intervention of c.p.u.such a transfer increases rate of transfer and makes the system more efficient

MICROPROCESSOR BASED DATA TRANSFER SCHEME


HERE data transfer is controlled by microprocessor. Microprocessor is primarily responsible for data transfer whether from I/o to the c.p.u or to the memory or vice versa .MICROPROCESSOR BASED scheme is further divided into two parts:-

PROGRAMMED DATA TRANSFER SCHEME INTERRUPT CONTROL DATA TRANSFER SCHEME

PROGRAMMED DATA TRANSFER SCHEME


THESE SCHEME IS controlled by the c.p.u . Data are transferred from an IO device to the c.p.u or to the memory through c.p.u or vice versa under the control of programs which are stored in memory.This programs are executed by the c.p.u and is invariably used when small amount of data is to be transferred.Here also synchronous and asynchronous mode of transfer is used.Every data transfer operation involving an IO device requires the execution of an instruction by the c.p.u. Typically the transfer is between two programmable registers:one a C.P.U register and other attached to the IO device.

Issue read command to IO module

Read status of IO module

Check status

Read word from IO module

Write word into memory

done

Next instruction

TYPES OF PROGRAMMED DATA TRANSFER


UNCONDITIONAL POLLING DATA TRANSFER USING READY SIGNAL

DATA TRANSFER WITH HANDSHAKE SIGNAL

DRAWBACK OF PROGRAMMED DATA TRANSFER SCHEME


THE programmed IO transfer method is quite insufficient . Consider a typical computer can execute the two instruction that read and check status in 1 micro second.

Assume that the input device transfers its data at an average rate of 100 bytes pe c.p.u will then check the flag 10000 times between each transfer The c.p.u is wasting time while checking the flag instead of doing some useful work.

INTERRUPT DRIVEN DATA TRANSFER


The problem with programmed IO is that c.p.u has to wait along time for the Io device of the concern to be ready for reception or transmission of data .The c.p.u while waiting, must repeatedly interrogate the status of the IO device . As a result the level of the performance of the entire system is severely degraded.

An alternative is interrupt driven IO data transfer.

Issue read command to IO module

C.P.U-------IO

interrupt Read status of IO module

IO----------c.p.u

Check status READY Read word from IO module

Write word into memory NO done

Next instruction

DRAWBACKS OF PROGRAMMED AND INTERRUPT DRIVEN DATA TRANSFER


The IO transfer rates is limited by the speed by which the CPU can test and service a device.
The CPU is tied up in managing an IO transfer; a number of instruction must be executed for each IO transfer.
Consider the transfer of block of data using programmed IO CPU is dedicated to the task of IO and can move data at a rather high rate at the cost of doing nothing else. Interrupt IO frees up the CPU to some extent at the expense of IO transfer rate never the less both methods have an adverse impact on CPU activity and IO transfer rate. Hence a more efficient technique was required and then Device data transfer scheme i.e DMA data transfer was introduced.

DEVICE CONTROL DATA TRANSFER


The transfer of data between the mass storage device and a system memory is often limited by the speed of microprocessor. Removing the the microprocessor during such a transfer and letting the peripheral manage the transfer to or from memory would improve the speed of transfer and hence will make the system more efficient. This transfer technique is called DMA Data Transfer. During DMA transfer processor is idle, so it has no longer control on the system buses. A DMA Controller takes over the buses and manage the transfer directly between the peripheral and the memory. It is fastest scheme then Programmed Data Transfer Scheme and the CPU regains the control of buses after data transfer.

Interrupt
RAM BG C.P.U BR RD RD WR ADD DATA
READ CONTROL DATA BUS

WR

ADD

DATA

ADDR

ADDRESS BUS

RD WR DS RS BR BG

ADD DATA
DMA ACK

DMA CONT
DMA

IO PERIPHERAL DEVICE

INTERRUPT

DMA TRANSFER OPERATION


THE c.p.u communicates with the DMA through the address and data buses as with any interface unit.

The DMA has its own address which activates the DS and RS lines
The c.p.u initializes the DMA through data lines

Once the DMA receives the start control command it can start the transfer between the peripheral devices and memory. When the peripheral device sends a DMA request the DMA controller activates the BR line, informing the c.p.u to relinquish the busses.
The c.p.u responds with its BG lines informing the DMA that its busses are disabled. The DMA then puts the current value of its address register into the address bus, initiates the WR or RD signal and then sends the DMA ACK to the peripheral device.

RD and WR lines are bi-directional.


When the peripheral device receives a DMA ACK it puts a word in the data bus or receives a word from the data bus (for REAWhen BG=0 the RD and WR are input lines,and acts in master mode and when BG=1 it acts as an output line from the DMA controller to the RAM. D). Thus the DMA controls the read and write operation and supplies the address for the memory.

TYPES OF D.M.A DATA TRANSFER


THERE are two types of DMA data transfer :BURST MODE OF DATA TRANSFER:-A scheme of data transfer , in which the IO device withdraws the DMA request only after it has transferred all the bytes. By this technique a block of data is transferred. It is used mainly in MAGNETIC DISK DRIVES.

CYCLE STEALING MODE OF DATA TRANSFER:- In this technique a long block of data is transferred by a sequence of DMA cycle.in this method after transferring one byte or several bytes the IO device withdraws DMA request. This method reduces interference in C.P.U ACTIVITIES

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