HDL Programming using verilog

Unit-1: Overview of Digital Design with Verilog

HDL

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 Overview of Digital Design with
Verilog HDL
• Evolution of Computer – Aided Digital Design
– Moore’s law, SSl, MSI, LSI
– EDA
– VLSI, Simulators, Fabrication ICs.

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 Overview of Digital Design with
Verilog HDL
• Emergence of HDLs
– Fortran, C (Sequential)
– HDL (Concurrent) in 1983 at Gateway design
Automation (
Defense Advanced Research Projects Agency) –
Verilog, VHDL
– RTL
– Logic synthesis tool
– FPGA, PALs
– IEEE 1364-1995, IEEE 1364-2001 std
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 Typical
Design Flow

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 Overview of Digital Design with
Verilog HDL
• Importance of HDL
– Design described at Abstract level
– Uses logic synthesis tool for RTL
– Gate netlist
– Optimizes area and timing
– Functional verification - Simulation reduces
design cycle
– Analogous to Computer programming (Textual
description)
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 Overview of Digital Design with
Verilog HDL
• Popularity of Verilog HDL
– General purpose hardware description
– C like statements
– Different level of abstractions to mixed design
(gates, switches, RTL, behavioral)
– Various tools
– HDL Libraries for synthesis and simulations
– Programming Language Interface (PLI) is powerful
feature in it.
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 Overview of Digital Design with
Verilog HDL
• Trends in HDLs
– HDL at RTL level
– EDA- translation, Optimization
– Formal verification and assertion checking
– Gate level netlist
– System level design and simulation

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 Hierarchical Modeling Concepts
• Top Down Design Methodologies
• we define the top-level block and identify the sub-blocks necessary
to build the top-level block. We further subdivide the sub-blocks until
we come to leaf cells, which are the cells that cannot further be
divided.
• Bottom up design methodologies
• we first identify the building blocks that are available to us. We build
bigger cells, using these building blocks. These cells are then used for
higher-level blocks until we build the top-level block in the design.

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• Top Down Design Methodologies

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Bottom up design methodologies

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4-bit Ripple Carry Counter

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Design Hierarchy of ripple carry counter

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Modules
• A module is the basic building block in Verilog.
• A module can be an element or a collection of lower-level
design blocks.
• Typically, elements are grouped into modules to provide
common functionality that is used at many places in the
design.
• A module provides the necessary functionality to the higher-
level block through its port interface (inputs and outputs), but
hides the internal implementation.
• This allows the designer to modify module internals without
affecting the rest of the design 14
Module Syntax

T FF Module definition

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Instances
• A module provides a template from which you can create
actual objects.
• When a module is invoked, Verilog creates a unique object
from the template.
• Each object has its own name, variables, parameters and I/O
interface.
• The process of creating objects from a module template is
called instantiation, and the objects are called instances.

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BEHAVIORAL MODELLING
Module half_adder(a,b, sum,carry);
input a,b;
output reg sum,carry;
always@( * )
begin
sum=a^b;
carry=a&b;
end
endmodule

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DATA-FLOW MODELLING
module half_adder(a,b, sum,carry);
input a,b;
output sum,carry;
assign sum=a^b;
assign carry=a&b;
endmodule

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STRUCTURAL MODELLING
module half_adder (a,b,sum,carry);
input a,b;
output sum,carry;
xor(sum,a,b);
and(carry,a,b);
endmodule

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Components of Simulation

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Components of Simulation

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 Basic Concepts

Lexical Conventions
 The basic lexical conventions used by Verilog HDL are similar
to those in the C programming language.
 Verilog contains a stream of tokens.
 Tokens can be comments, delimiters, numbers, strings,
identifiers, and keywords.
 Verilog HDL is a case-sensitive language.
 All keywords are in lowercase.

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Whitespace
 Blank spaces (\b) , tabs (\t) and newlines (\n) comprise the
whitespace.
 Whitespace is ignored by Verilog except when it separates
tokens.
 Whitespace is not ignored in strings.

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Comments
 Comments can be inserted in the code for readability and
documentation.
 There are two ways to write comments.
 A one-line comment starts with "//".
 Verilog skips from that point to the end of line.
 A multiple-line comment starts with "/*” and ends with "*/".
Multiple-line comments cannot be nested.

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Operators
 Operators are of three types, unary, binary, and ternary.
 Unary operators precede the operand.
 Binary operators appear between two operands.
 Ternary operators have two separate operators that separate
three operands.

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Number Specification
 There are two types of number specification in Verilog: sized and
unsized.
 Sized numbers are represented as
<size> '<base format> <number>
 <size> is written only in decimal and specifies the number of bits
in the number.
 Legal base formats are decimal ('d or 'D), hexadecimal ('h or 'H),
binary ('b or 'B) and octal ('o or 'O).
 The number is specified as consecutive digits from 0, 1, 2, 3,
4,5,6,7,8,9, a, b, c, d, e, f.
 Only a subset of these digits is legal for a particular base.
Uppercase letters are legal for number specification.
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Number Specification
 Unsized numbers: Numbers that are specified without a <base
format> specification are decimal numbers by default.
 Numbers that are written without a <size> specification have a
default number of bits that is simulator- and machine-specific
(must be at least 32).

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 X or Z values: Verilog has two symbols for unknown and high
impedance values.
 These values are very important for modeling real circuits.
 An unknown value is denoted by an x.
 A high impedance value is denoted by z.

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 An x or z sets four bits for a number in the hexadecimal base,
three bits for a number in the octal base, and one bit for a
number in the binary base.
 If the most significant bit of a number is 0, x, or z, the number
is automatically extended to fill the most significant bits,
respectively, with 0, x, or z.
 This makes it easy to assign x or z to whole vector.
 If the most significant digit is 1, then it is also zero extended.

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Negative numbers
 They can be specified by putting a minus sign before the size for a
constant number.
 Size constants are always positive.
 It is illegal to have a minus sign between <base format> and
<number>.

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Underscore characters and question marks
 An underscore character "_" is allowed anywhere in a number except
the first character.
 Underscore characters are allowed only to improve readability of
numbers and are ignored by Verilog.
 A question mark “?" is the Verilog HDL alternative for z in the context
of numbers.
 The ? is used to enhance readability in the casex and casez statements,
where the high impedance value is a don't care condition.

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Strings
 A string is a sequence of characters that are enclosed by double quotes.
 The restriction on a string is that it must be contained on a single line,
that is, without a carriage return.
 It cannot be on multiple lines.
 Strings are treated as a sequence of one-byte ASCII values.

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Identifiers and Keywords
 Keywords are special identifiers reserved to define the language
constructs.
 Keywords are in lowercase.
 Identifiers are names given to objects so that they can be referenced in the
design.
 Identifiers are made up of alphanumeric characters, the underscore ( _ )
and the dollar sign ( $ ) and are case sensitive.
 Identifiers start with an alphabetic character or an underscore.
 They cannot start with a number or a $ sign
 The $ sign as the first character is reserved for system tasks, which are
explained later.

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Escaped Identifiers
 Escaped identifiers begin with the backslash ( \ ) character and end
with whitespace (space, tab, or newline).
 All characters between backslash and whitespace are processed
literally.
 Any printable ASCII character can be included in escaped
identifiers.
 The backslash or whitespace is not considered a part of the identifier.

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Data Types
 Value Set: Verilog supports four values and eight strengths to
model the functionality of real hardware.
 The four value levels are listed in Table

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 Value Set:
 In addition to logic values, strength levels are often used to resolve
conflicts between drivers of different strengths in digital circuits.
 Value levels o and 1 can have the strength levels listed in Table

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 Value Set:
 If two signals of unequal strengths are driven on a wire, the stronger
signal prevails.
 For example, if two signals of strength strong1 and weak0 contend,
the result is resolved as a strong1.
 If two signals of equal strengths are driven on a wire, the result is
unknown.
 If two signals of strength strongl and strong0 conflict, the result is
an x.
 Strength levels are particularly useful for accurate modeling of
signal contention,

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 Nets
 Nets represent connections between hardware elements.
 Nets have values continuously driven on them by the outputs of devices
that they are connected to.

 Net a will continuously assume the value computed at the output of gate g1,
which is b & c
 Nets are declared primarily with the keyword wire.
 Nets are one-bit values by default unless they are declared explicitly as
vectors.
 The terms wire and net are often used interchangeably.
 The default value of a net is z (except the trireg net, which defaults to x ).
 Nets get the output value of their drivers. If a net has no driver, it gets the
value z. 47
 Note that net is not a keyword but represents a class of data types
such as wire, wand, wor, tri, triand, trior, trireg, etc.
 The wire declaration is used most frequently.

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Registers
 Registers represent data storage elements.
 Registers retain value until another value is placed onto them.
 Do not confuse the term registers in Verilog with hardware registers
built from edge-triggered flip-flops in real circuits.
 In Verilog, the term register merely means a variable that can hold a
value.
 Unlike a net, a register does not need a driver.
 Verilog registers do not need a clock as hardware registers do.
 Values of registers can be changed anytime in a simulation by
assigning a new value to the register.
 Register data types are commonly declared by the keyword reg.
 The default value for a reg data type is x.
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Vectors
 Nets or reg data types can be declared as vectors (multiple bit widths).
 If bit width is not specified, the default is scalar (1-bit).

 Vectors can be declared at [high# : low#] or [low# : high#), but the left
number in the squared brackets is always the most significant bit of the
vector.
 In the example shown above, bit 0 is the most significant bit of vector
virtual_addr.
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 For the vector declarations shown above, it is possible to address bits
or parts of vectors.

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Integer, Real, and Time Register Data Types:
Integer:
 An integer is a general purpose register data type used for manipulating
quantities.
 Integers are declared by the keyword integer.
 Although it is possible to use reg as a general-purpose variable, it is more
convenient to declare an integer variable for purposes such as counting.
 The default width for an integer is the host-machine word size, which is
implementation specific but is at least 32 bits.
 Registers declared as data type reg store values as unsigned quantities,
whereas integers store values as signed quantities.

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 Real
 Real number constants and real register data types are declared with the
keyword real.
 They can be specified in decimal notation (e.g., 3.14) or in scientific
notation (e.g., 3e6, which is 3 x 106 ).
 Real numbers cannot have a range declaration, and their default value is 0.
 When a real value is assigned to an integer, the real number is rounded off
to the nearest integer.

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 Time
 Verilog simulation is done with respect to simulation time.
 A special time register data type is used in Verilog to store simulation
time.
 A time variable is declared with the keyword time.
 The width for time register data types is implementation specific but is
at least 64 bits.
 The system function $time is invoked to get the current simulation
time.

 Simulation time is measured in terms of simulation seconds. The unit is

denoted by s.
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 Arrays
 Arrays are allowed in Verilog for reg, integer, time, and vector
register data types.
 Arrays are not allowed for real variables.
 Arrays are accessed by <array_name> [<subscript>].
 Multidimensional arrays are not permitted in Verilog.

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 It is important not to confuse arrays with net or register vectors.

 A vector is a single element that is n-bits wide.

 On the other hand, arrays are multiple elements that are 1-bit or n-bits

wide.

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 Memories
 Register files, RAMs, and ROMs.
 Memories are modeled in Verilog simply as an array of registers.
 Each element of the array is known as a word.
 Each word can be one or more bits.
 It is important to differentiate between n 1-bit registers and one n-bit
register.
 A particular word in memory is obtained by using the address as a
memory array subscript.

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 Parameters
 Verilog allows constants to be defined in a module by the keyword
parameter.
 Parameters cannot be used as variables.
 Parameter values for each module instance can be overridden
individually at compile time.
 This allows the module instances to be customized.

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 Module definitions may be written in terms of parameters.

 Hardcoded numbers should be avoided.

 Parameters can be changed at module instantiation or by using the

defparam statement.

 Thus, use of parameters makes the module definition flexible.

 Module behavior can be altered simply by changing the value of a

parameter.

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 Strings
 Strings can be stored in reg.
 The width of the register variables must be large enough to hold the
string. Each character in the string takes up 8 bits (1 byte).
 If the width of the register is greater than the size of the string, Verilog
fills bits to the left of the string with zeros.
 If the register width is smaller than the string width,
 Verilog truncates the leftmost bits of the string.
 It is always safe to declare a string that is slightly wider than necessary.

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 Special characters serve a special purpose in displaying strings, such
as newline, tabs and displaying argument values.
 Special characters can be displayed in strings only when they are
preceded by escape characters, as shown in Table

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System Tasks and Compiler Directives

System Tasks
 Verilog provides standard system tasks to do certain routine
operations.
 All system tasks appear in the form $<keyword>.
 Operations such as displaying on the screen, monitoring values of nets,
stopping, and finishing are done by system tasks.
 Displaying information $display is the main system task for displaying
values of variables or strings or expressions.
 Usage: $display(p1, p2, p3,....., pn);
 p1, p2, p3,..., pn can be quoted strings or variables or expressions.

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System Tasks
 The format of $display is very similar to printf in C.
 A $display inserts a newline at the end of the string by default.
 A $display without any arguments produces a newline.
 Strings can be formatted by using the format specifications listed in
Table .

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System Tasks

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$display task

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$display task

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 Monitoring information
 Verilog provides a mechanism to monitor a signal when its value
changes.
 This facility is provided by the $monitor task.
 Usage: $monitor(p1,p2.p3,...,pn);
 The parameters p1, p2, ... , pn can be variables, signal names, or
quoted strings.
 A format similar to the $display task is used in the $monitor task.
 $monitor continuously monitors the values of the variables or signals
specified in the parameter list and displays all parameters in the list
whenever the value of any one variable or signal changes.
 Unlike $display, $monitor needs to be invoked only once.
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 Monitoring information
 Only one monitoring list can be active at a time.
 If there is more than one $monitor statement in your simulation, the
last $monitor statement will be the active statement. (The earlier
$monitor statements will be overridden).
 Two tasks are used to switch monitoring on and off.
 Usage: $monitoron; $monitoroff;
 The $monitoron tasks enables monitoring, and the $monitoroff task
disables monitoring during a simulation.
 Monitoring is turned on by default at the beginning of the simulation
and can be controlled during the simulation with the $monitoron and
$monitoroff tasks.
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Monitoring information
Note the use of $time in the $monitor statement.

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 Stopping and finishing in a simulation
 The task $stop is provided to stop during a simulation.
 Usage: $stop;
 The $stop task puts the simulation in an interactive mode.
 The designer can then debug the design from the interactive mode.
 The $stop task is used whenever the designer wants to suspend the
simulation and examine the values of signals in the design.
 The $finish task terminates the simulation.
 Usage: $finish;

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 Compiler Directives
 Compiler directives are provided in Verilog.
 All compiler directives are defined by using the '<keyword>
construct.
 Two most useful compiler directives: ‘define and ‘include

'define directive
 The 'define directive is used to define text macros in Verilog.
 This is similar to the #define construct in C.
 The defined constants or text macros are used in the Verilog code by
preceding them with a ' (back tick).
 The Verilog compiler substitutes the text of the macro wherever it
encounters a '<macro_name>. 72
'define directive

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 ‘include
 The 'include directive allows you to include entire contents of a
Verilog source file in another Verilog file during compilation.
 This works similarly to the #include in the C programming language.
 This directive is typically used to include header files, which
typically contain global or commonly used definitions

 Two other directives, 'ifdef and 'timescale, are used frequently. It

will be discussed in later units. 74
Modules
Modules and Ports

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 Modules
• A module definition always begins with the keyword module.
• The module name, port list, port declarations, and optional parameters
must come first in a module definition.
• Port list and port declarations are present only if the module has any
ports to interact with the external environment.
• The five components within a module are - variable declarations,
dataflow statements, instantiation of lower modules, behavioral blocks,
and tasks or functions.
• These components can be in any order and at any place in the module
definition.
• The endmodule statement must always come last in a module
definition.
• All components except module, module name, and endmodule are
optional and can be mixed and matched as per design needs.
• Verilog allows multiple modules to be defined in a single file.
• The modules can be defined in any order in the file.
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 Ports
 Ports provide the interface by which a module can communicate with
its environment.
 For example, the input/output pins of an IC chip are its ports.
 The environment can interact with the module only through its ports.
 The internals of the module are not visible to the environment.
 This provides a very powerful flexibility to the designer.
 The internals of the module can be changed without affecting the
environment as long as the interface is not modified.
 Ports are also referred to as terminals.
 A module definition contains an optional list of ports.
 If the module does not exchange any signals with the environment,
there are no ports in the list. 78
4-bit full adder

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 Port Declaration
 All ports in the list of ports must be declared in the module. Ports
can be declared as follows:

 Each port in the port list is defined as input, output, or inout,

based on the direction of the port signal.

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Port Declaration

 Note that all port declarations are implicitly declared as wire in

Verilog.
 Thus, if a port is intended to be a wire, it is sufficient to declare it as
output, input, or inout. Input or inout ports are normally declared as
wires.
 However, if output ports hold their value, they must be declared as
reg. 81
  However, if output ports hold their value, they must be declared as
reg.
 For example, in the definition of DFF, we wanted the output q to
retain its value until the next clock edge.

 Ports of the type input and inout cannot be declared as reg because reg
variables store values and input ports should not store values but simply
reflect the changes in the external signals they are connected to.

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 Port Connection Rules
 One can visualize a port as consisting of two units, one unit that is
internal to the module another that is external to the module.
 The internal and external units are connected.
 There are rules governing port connections when modules are
instantiated within other modules.
 The Verilog simulator complains if any port connection rules are
violated.

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Port Connection Rules

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Port Connection Rules

Inputs:
 Internally, input ports must always be of the type net.
 Externally, the inputs can be connected to a variable which is a reg or a
net.
Outputs:
 Internally, outputs ports can be of the type reg or net.
 Externally, outputs must always be connected to a net.
 They cannot be connected to a reg.
Inouts:
 Internally, inout ports must always be of the type net.
 Externally, inout ports must always be connected to a net.
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Port Connection Rules
Width matching:
 It is legal to connect internal and external items of different sizes
when making inter-module port connections.
 However, a warning is typically issued that the widths do not match.
Unconnected ports:
 Verilog allows ports to remain unconnected.
 For example, certain output ports might be simply for debugging,
and you might not be interested in connecting them to the external
signals.
 You can let a port remain unconnected by instantiating a module as
shown below.
fulladd4 fa0 (SUM, , A, B, C_IN); // Output port c_out is unconnected86
 Example of illegal port connection

// Illegal connection because output port sum in module

fulladd4 // is connected to a register variable SUM in module
Top.

Note:
 This problem is rectified if the variable SUM is declared as a net (wire).
 A similar problem would occur if an input port were declared as a reg in
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design under test.
 Connecting Ports to External Signals

 There are two methods of making connections between signals

specified in the module instantiation and the ports in a module
definition.
 The two methods cannot be mixed.
 Connecting by ordered list
 Connecting ports by name

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Connecting by ordered list

 Connecting by ordered list is the most intuitive method for most

beginners.
 The signals to be connected must appear in the module instantiation
in the same order as the ports in the port list in the module
definition.
 Notice in module fulladd4 that the external signals SUM, C_OUT,
A, B, and C_IN appear in exactly the same order as the ports sum,
c_out, a, b, and c_in in module definition of fulladd4

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Example: Connecting by ordered list

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Connecting ports by name:

 For large designs where modules have, 50 ports, remembering the

order of the ports in the module definition is impractical and error
prone.
 Verilog provides the capability to connect external signals to ports by
the port names, rather than by position.
 Note that you can specify the port connections in any order as long as
the port name in the module definition correctly matches the external
signal.

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Connecting ports by name:
 Only those ports that are to be connected to external signals must be
specified in port connection by name.
 Unconnected ports can be dropped.
 For example, if the port c_out were to be kept unconnected, the
instantiation of fulladd4 would look as follows.

 The port c_out is simply dropped from the port list.

 Another advantage of connecting ports by name is that as long as the
port name is not changed, the order of ports in the port list of a module
can be rearranged without changing the port connections in module
instantiations.
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Hierarchical Names:
 Verilog supports a hierarchical design methodology.
 Every module instance, signal, or variable is defined with an
identifier.
 A particular identifier has a unique place in the design hierarchy.
 Hierarchical name referencing allows us to denote every identifier
in the design hierarchy with a unique name.
 A hierarchical name is a list of identifiers separated by dots (“.") for
each level of hierarchy.
 Thus, any identifier can be addressed from any place in the design
by simply specifying the complete hierarchical name of that
identifier.
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Hierarchical Names:
 The top-level module is called the root module because it is not
instantiated anywhere. It is the starting point.
 To assign a unique name to an identifier, start from the top-level
module and trace the path along the design hierarchy to the desired
identifier.

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Hierarchical Names:
 For SR Latch simulation, stimulus is the top-level module.
 Since the top-level module is not instantiated anywhere, it is called
the root module.
 The identifiers defined in this module are q, qbar, set, and reset.
 The root module instantiates m1, which is a module of type
SR_latch.
 The module m1 instantiates nand gates nl and n2.
 Q, Qbar, S, and R are port signals in instance m1.
 Hierarchical name referencing assigns a unique name to each
identifier.
 To assign hierarchical names, use the module name for root module
and instance names for all module instances below the root module.
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Hierarchical Names:
 Example shows hierarchical names for all identifiers in the above
simulation.
 Notice that there is a dot (.) for each level of hierarchy from the root
module to the desired identifier.

 Each identifier in the design is uniquely specified by its hierarchical

path name.
 To display the level of hierarchy, use the special character %m in the
$display task.
See String Format Specifications table, for details. (Slide no. 65)
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THANK YOU

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