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Programmabl e Interval Timer 8253 / 8254

The document discusses the 8254 programmable interval timer chip. It provides block diagrams and descriptions of the chip's modes of operation including interrupt on terminal count, one-shot, rate generator, and square wave generator modes. It also covers the control word format, reading operations using simple reads, counter latch commands, and read-back commands, and describes the status register.

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53 views

Programmabl e Interval Timer 8253 / 8254

The document discusses the 8254 programmable interval timer chip. It provides block diagrams and descriptions of the chip's modes of operation including interrupt on terminal count, one-shot, rate generator, and square wave generator modes. It also covers the control word format, reading operations using simple reads, counter latch commands, and read-back commands, and describes the status register.

Uploaded by

Diva3792
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Programmabl e Interval timer 8253 / 8254

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WHY 8253???

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8253 VS 8254

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82 54 BL OC K

BLOCK DIAGRAM OF 8254

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CS RD WR A1 A0
0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 1 1 1 1 X 0 0 1 1 0 0 1 1 X X 0 1 0 1 0 1 0 1 X X

OPERATION
WRITE COUNTER 0 WRITE COUNTER 1 WRITE COUNTER 2 WRITE CONTROL WORD READ COUNTER 0 READ COUNTER 1 READ COUNTER 2 NO OPERATION ( TRISTATED ) NO OPERATION ( TRISTATED ) 8254 NOT SELECTED

1 X 5/6/12

8254 PIN DIAGRAM

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CONTROL WORD FORMAT

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Mode 0:

The output becomes a logic 0 when the control word is written Remains low even after count value loaded in counter

Modes of INTERRUPT ON TERMINAL COUNT operation

Counter starts decrementing after falling edge of clock

The OUT goes high upon reaching the terminal Click to edit high till reloading count & remainsMaster subtitle style

OUT can be used as interrupt

Writing a count register , when previous counting is in process first byte when loaded stops the previous count, second byte when loaded starts new count

Gate high normal counting 5/6/12

Mode 0: INTERRUPT ON TERMINAL COUNT

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Mode 1: One-shot mode.


monostable multivibrator gate input is used as trigger input output remains high till the count is loaded After application of trigger, output goes low and remains low till count becomes zero Another count loaded, when output already low it does not disturb counting until a new trigger is applied at the gate New counting starts after new trigger pulse

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Mode 1: One-shot mode

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Mode 2: RATE GENERATOR / DIVIDE BY N COUNTER

When N is loaded as count after N pulses OUT goes low for only one clock cycle then, count N is reloaded OUT becomes high for N clock pulses

The number of clock pulses between the two low pulses is equal to the count loaded

gate logic 0 no counting Gate logic 1 normal counting

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Mode 3: SQUARE WAVE RATE GENERATOR


When count N loaded is even output remains HIGH for half the count and LOW for the rest half of the count

When count N loaded is odd output remains HIGH for (N+1)/2 and low for (N-1)/2.

Repeated operation gives square wave

Click to edit Master subtitle style

Generates a continuous square-wave with G set to 1. If count is even, 50% duty cycle otherwise OUT is high 1 cycle longer.

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Mode 3: square wave generator

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Mode 4: Software triggered Strobe


After mode is set output goes high When count is loaded counting down starts On reaching terminal count output goes low for only one clock cycle, and then again output goes HIGH The above said low pulse can be used as a strobe for interfacing MP with peripherals When GATE is LOW counting is inhibited and count is latched If a new count is loaded while counting, 5/6/12 previous counting stops and new

Mode 4: Software triggered Strobe

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Mode 5: Hardware triggered Strobe


This mode generates a strobe in response to the rising edge at the trigger Mode is used to generate a delayed strobe in response to an externally generated signal Once mode is programmed and counter loaded, OUT goes HIGH Counter starts counting after the rising edge of the Click to edit Master subtitle style trigger (GATE) The OUTPUT goes LOW for one clock period, when the terminal count is reached Output will not go LOW until the counter content becomes zero after the rising edge of any trigger GATE is used as trigger input

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2020

Mode 5: Hardware triggered Strobe

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Click to edit Master subtitle style

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Read Operations

There are three possible methods for reading the counters: a simple read operation the Counter Latch Command the Read-Back Command

Click to edit operation : Simple readMaster subtitle style

The Counter which is selected with the A1, A0 inputs, the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic.

Otherwise, the count may be in the process of changing when it is read, giving an undefined 5/6/12

Counter Latch Command: select one SC0, SC1 bits

of the three Counters two other bits, D5 and D4, distinguish this command from a Control Word If a Counter is latched and then, some time later, latched again before the countClick to editthe second style is read, Master subtitle Counter Latch Command is ignored.

The count read will be the count at the time the first Counter Latch Command was 5/6/12issued.

Read-back control command:


The read-back control, word is used, when it is necessary for the contents of more than one counter to be read at a same time. Count : logic 0, select one of the Click to edit Master subtitle style Counter to be latched Status : logic 0, Status must be latched to be read status of a counter and is accessed by a read from that counter

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Status register:
shows the state of the output pin check the counter is in NULL state (0) or not how the counter is programmed

Click to edit Master subtitle style

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