Hands-on experiences in:
Computer architecture in both processor core and uncore subsystems; performance modeling; cache coherence protocol design, specification, and verification; analysis of intricate protocol issues such as deadlock and starvation avoidance and memory ordering; simulation-based functional verification, formal verification; RTL coding; FPGA prototyping; binary translation-based emulation; modification of QEMU internals; multi-core programming; low-level programming with assembly; translators from one language to another; debugging complex software.
My resume is attached below, which is also available at:
https://dl.dropboxusercontent.com/u/76236261/ctchou-resume.pdf...
Hands-on experiences in:
Computer architecture in both processor core and uncore subsystems; performance modeling; cache coherence protocol design, specification, and verification; analysis of intricate protocol issues such as deadlock and starvation avoidance and memory ordering; simulation-based functional verification, formal verification; RTL coding; FPGA prototyping; binary translation-based emulation; modification of QEMU internals; multi-core programming; low-level programming with assembly; translators from one language to another; debugging complex software.
My resume is attached below, which is also available at:
https://dl.dropboxusercontent.com/u/76236261/ctchou-resume.pdf...
