Project ACRN: SR-IOV implementation
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This document discusses SR-IOV (Single Root I/O Virtualization) in ACRN. It begins with an introduction to SR-IOV, describing how it allows PCIe devices to be isolated and have near bare-metal performance through the use of Physical Functions (PFs) and Virtual Functions (VFs). It then outlines the SR-IOV architecture in ACRN, including how it detects and initializes SR-IOV devices, assigns VFs to VMs, and manages the lifecycle of VFs. Finally, it provides an agenda for an SR-IOV demo using an Intel 82576 NIC and concludes with a Q&A section.
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Project ACRN: SR-IOV implementation
- 1. SR-IOV On ACRN Yuan LIU Liu, Yuan1 <[email protected]> 04/01/2020
- 2. Agenda ❑SR-IOV Introduction ❑SR-IOV Architecture On ACRN ❑SR-IOV Demo – Intel 82576
- 3. SR-IOV Introduction SR-IOV(single root input/output virtualization) can isolate PCIe devices and make the devices to have good performance, close to bare-metal. The SR-IOV framework consists of two basic units, one is called PF(Physical Function) that supports SR-IOV extended capability and manages entire physical device, another is called VF (Virtual Function) and it is a "light-weight" PCIe function which is used to assigned to a VM as a pass-through device. https://projectacrn.github.io/latest/tutorials/sriov_virtualization.html
- 4. SR-IOV Overview • SI - System image like guest VM. • VI - Virtualization Intermediary known as VMM or hypervisor. • SR-PCIM - Single Root PCI Manager is a software entity for SR-IOV management. • PF - A PF is a PCIe Function that supports the SR- IOV capability and is accessible to an SR-PCIM, a VI, or an SI. • VF - A VF is a “light-weight” PCIe Function that is directly accessible by an SI.
- 6. SR-IOV Register ⚫ VF Migration Capable ⚫ Indicates that the PF supports VF Migration. ⚫ ARI Capable Hierarchy Preserved ⚫ For PCI Express Endpoint, it indicates if the ARI Capable Hierarchy bit is preserved across certain power state transitions. ⚫ For RCiEP, it is not applicable. ⚫ VF 10-Bit Tag Requester Supported ⚫ Indicates if VFs support 10-Bit Tag Requester capability. ⚫ VF Migration Interrupt Message Number ⚫ Indicates the MSI/MSI-X vector used for migration interrupts.
- 7. SR-IOV Register ⚫ SR-IOV Control ⚫ VF Enable ⚫ VF Migration Enable ⚫ VF Migration Interrupt Enable ⚫ VF MSE(Memory Space Enable) ⚫ ARI Capable Hierarchy ⚫ VF 10-Bit Tag Requester Enable ⚫ SR-IOV Status ⚫ VF Migration Status
- 8. SR-IOV Register ⚫ InitialVFs ⚫ It indicates to the number of VFs that are initially associated with the PF. ⚫ For Devices operating in Single-Root mode, this field is HwInit and must contain the same value as TotalVFs. ⚫ TotalVFs ⚫ It indicates the maximum number of VFs that could be associated with the PF. ⚫ For Devices operating in Single-Root mode, this field is HwInit and must contain the same value as InitialVFs. ⚫ NumVFs ⚫ It controls the number of VFs that are visible. ⚫ It may only be written while VF Enable is Clear. ⚫ NumVFs <= InitialVFs = TotalVFs.
- 9. SR-IOV Register The programming model for a device may have vendor-specific dependencies between sets of Functions. If PF p and PF q are in the same Function Dependency List, than any SI that is assigned VF p,n shall also be assigned to VF q,n. PF 0 depends on PF1 and PF1 depends on PF 0. PF 2 is independent from other PFs. VF 0,1 and VF 1,1 are same with PF 0 and PF 1 dependency, so need to assign VF 0,1 and VF 1,1 to a same VM. VF 0,2 is independent, same with PF 2, it can be assigned separately. Dependency relationship can be determined by sysfs entry: /sys/bus/pci/devices/…/dep_link
- 10. SR-IOV Register First VF Offset is a constant and defines the Routing ID offset of the first VF. VF Stride defines the Routing ID offset from one VF to the next one for all VFs. First VF Offset and VF Stride are set by device, software access with Read Only. After configuring NumVFs and ARI Capable Hierarchy, software may read First VF Offset and VF Stride to determine how many bus numbers would be consumed by the PF’s VFs.
- 11. SR-IOV Register This field contains the Device ID that should be presented for every VF to the SI. VF Device ID may be different from the PF Device ID.
- 12. SR-IOV Register ⚫ Supported Page Size ⚫ This field indicates the page sizes supported by the PF. ⚫ PFs are required to support 4-KB, 8-KB, 64-KB, 256-KB, 1-MB, and 4-MB page sizes. ⚫ System Page Size ⚫ It is used to align all VF BAR resources on a System Page Size boundary. ⚫ Software must set the value of the System Page Size to one of the page sizes set in the Supported Page Sizes.
- 13. SR-IOV Register
- 14. SR-IOV Register If VF Migration Capable is Set and TotalVFs is not zero, this register shall contain a PF BAR relative pointer to the VF Migration State Array. The VF Migration State Array has a VF Migration State Entry for each VF.
- 15. ARI Capability ⚫ The ARI(Alternative Routing ID Interpretation Extended Capability) capability enables a device to support up to 256 functions ⚫ If software does not configure sufficient additional bus numbers, then the VFs implemented for the additional Bus numbers may not be visible. ⚫ Max bus number can be defined by numVFs, First VF Offset and VF Stride.
- 16. SR-IOV Interrupt Mechanism • PFs can support INTx, MSI or MSI-X interrupt resources • VFs only support MSI or MSI-X interrupt resources.
- 18. SR-IOV VF Migration ⚫ A VF can be optionally migrated from one PF to another PF. ⚫ VF Migration Capable and VF Migration Enable must be Set when enable VF migration. ⚫ VF Migration is an optional feature, ACRN doesn’t support it.
- 19. Agenda ❑SR-IOV Introduction ❑SR-IOV Architecture In ACRN ❑SR-IOV Demo – Intel 82576
- 21. ACRN Configuration Space Accessing
- 22. SR-IOV Architecture On ACRN 1. A hypervisor detects a SR-IOV capable PCIe device in the physical PCI device enumeration phase. 2. The hypervisor intercepts the PF’s SR-IOV capability. 3. The hypervisor waits for 100ms after VF_ENABLE is set and initializes VF devices.
- 23. SR-IOV Passthrough VF Architecture 1. The VF device needs to bind PCI- Stud driver instead VF driver before passthrough the device. 2. acrn-dm assigns the VF device with passthrough parameters to target VM. 3. Hypervisor adds new virtual device on target VM’s virtual PCI bus and initialize it with physical device. For VF virtual device, emulate Device ID/Vendor ID and MSE. 4. VF driver in target VM is able to probe the VF device.
- 25. SR-IOV VF Enable Flow
- 26. SR-IOV VF Disable Flow
- 27. SR-IOV VF Assignment Policy • All SR-IOV PF devices are managed by the Service VM. • Currently, the SR-IOV PF cannot passthrough to the User VM. • All VFs can passthrough to the User VM, but we do not recommend a passthrough to high privilege VMs because the PF device may impact the assigned VFs’ functionality and stability.
- 28. Agenda ❑SR-IOV Introduction ❑SR-IOV Architecture In ACRN ❑SR-IOV Demo – Intel 82576
- 29. Q & A