Nefrock勉強会 in大岡山「FPGAでゲーム機を作ろう！の会」Day4

Nefrock in
FPGA
Day4 2019/3/13
2
kaku@cb.cs.titech.ac.jp

l Shit registers
l Sound Effects
l The ALU: Arithmetic Logic Unit
l A Simple CPU
2019/3/13 Nefrock in 2

l
l
4
1. SISO
2. PISO
3. SIPO
4. PIPO
l
Shift Register
https://ja.wikipedia.org/wiki/
https://synapse.kyoto/glossary/glossary.php?word=

l
l
l
l
2
XOR
LSFR
(2# − 1)
LSFR
Liner Feedback Shift Register LFSR

l XOR
l
LSFR
!"# + !"% + !"& + !"" + 1
LSFR

l
LSFR
l LSFR
LSFR
l
l XOR
LSFR

LSFR
parameter TAPS = 8‘b00011101; //
output reg [NBITS-1:0] lfsr;
wire feedback = lfsr[NBITS-1] ^ INVERT;
lfsr
always @(posedge clk)
begin
if (reset)
lfsr <= {lfsr[NBITS-2:0], 1'b1}; // reset loads with all 1s
else if (enable)
lfsr <= {lfsr[NBITS-2:0], 1'b0} ^ (feedback ? TAPS : 0);
end
reset
1
16141311feedback

lfsr <= {lfsr[NBITS-2:0], 1'b0} ^ (feedback ? TAPS : 0);
1. 1
2. XOR
16
0 feedback XOR
⇒ feedback
TAPS 0 XOR
⇒ XOR
XOR
⇒ feedback 1
TAPS XOR
⇒ feedback 0 0 XOR
LSFR
x y
0 0 0
0 1 1
1 0 1
1 1 0
16141311feedback

Scrolling Starfield
wire star_enable = !hpos[8] & !vpos[8]; // 256 * 256
LFSR #(16'b1000000001011,0) lfsr_gen(
.clk(clk),
.reset(reset),
.enable(star_enable),
.lfsr(lfsr));
// # param
wire star_on = &lfsr[15:9]; // 7 1
assign rgb = display_on && star_on ? lfsr[2:0] : 0; // 3

l
LFO Low Frequency Oscillator
VCO Voltage Controlled Oscillator
LFO modulate
2019/3/13 Nefrock in 10
Sound Effects
oscillator

2019/3/13 Nefrock in 11
Sound Effects
output reg spkr = 0; // module output
input [9:0] lfo_freq; // LFO frequency (10 bits)
input [11:0] noise_freq; // noise frequency (12 bits)
input [11:0] vco_freq; // VCO frequency (12 bits)
input vco_select; // 1 = LFO modulates VCO
input noise_select; // 1 = LFO modulates Noise
input [2:0] lfo_shift; // LFO modulation depth
input [2:0] mixer; // mix enable {LFO, Noise, VCO}
LFO
always @(posedge clk) begin
// divide clock by 64
div16 <= div16 + 1;
if (div16 == 0) begin
// … update waveform timers
end
end
16 1
reg [3:0] div16; // divide-by-16 counter
reg [17:0] lfo_count; // LFO counter (18 bits)
reg lfo_state; // LFO output
reg [12:0] noise_count; // Noise counter (13 bits)
reg noise_state; // Noise output
reg [12:0] vco_count; // VCO counter (12 bits)
reg vco_state; // VCO output

2019/3/13 Nefrock in 12
LFO
// LFO oscillator
if (reset || lfo_count == 0) begin
lfo_state <= ~lfo_state;
lfo_count <= {lfo_freq, 8'b0};
end else
lfo_count <= lfo_count - 1;
// create triangle waveform from LFO
wire [11:0] lfo_triangle = lfo_count[17] ? ~lfo_count[17:6] : lfo_count[17:6];
wire [11:0] vco_delta = lfo_triangle >> lfo_shift;
256 1

2019/3/13 Nefrock in 13
VCO
// VCO oscillator
if (reset || vco_count == 0) begin
vco_state <= ~vco_state;
if (vco_select)
vco_count <= vco_freq + vco_delta;
else
vco_count <= vco_freq + 0;
end else
vco_count <= vco_count - 1; vco_delta

2019/3/13 Nefrock in 14
Noise
reg [15:0] lfsr; // LFSR output
LFSR #(16'b1000000001011,0) lfsr_gen(
.clk(clk),
.reset(reset),
.enable(div16 == 0 && noise_count == 0),
.lfsr(lfsr)
);
// Noise oscillator
if (reset || noise_count == 0) begin
if (lfsr[0])
noise_state <= ~noise_state;
if (noise_select)
noise_count <= noise_freq + vco_delta;
else
noise_count <= noise_freq + 0;
end else
noise_count <= noise_count - 1;
1

2019/3/13 Nefrock in 15
Mixer
// Mixer
spkr <= (lfo_state | ~mixer[2])
& (noise_state | ~mixer[1])
& (vco_state | ~mixer[0]);

l
1. 2
2.
3.
4.
2019/3/13 Nefrock in 16
The ALU: Arithmetic Logic Unit

l PDP-11 VAX 74181 ALU chip
1 32
1 4
8, 12, 16 …
l 74181
l ALU , AND/OR/XOR
2019/3/13 Nefrock in 17
https://ja.wikipedia.org/wiki/PDP-11 https://ja.wikipedia.org/wiki/VAX https://www.arcade-museum.com/
game_detail.php?game_id=10424

2019/3/13 Nefrock in 18
ALU
l 16
aluop
aluop 4
l 3
8 A, B
4 aluop
l Y 9
9 carry

2019/3/13 Nefrock in 19
ALU
// ALU module
module ALU(A, B, carry, aluop, Y);
parameter N = 8; // default width = 8 bits
input [N-1:0] A; // A input
input [N-1:0] B; // B input
input carry; // carry input
input [3:0] aluop; // alu operation
output [N:0] Y; // Y output + carry
// unary operations
ÒP_ZERO: Y = 0;
ÒP_LOAD_A: Y = {1'b0, A};
ÒP_LOAD_B: Y = {1'b0, B};
ÒP_INC: Y = A + 1;
ÒP_DEC: Y = A - 1;

2019/3/13 Nefrock in 20
ALU
// unary operations that generate and/or use carry
ÒP_ASL: Y = {A, 1'b0};
ÒP_LSR: Y = {A[0], 1'b0, A[N-1:1]};
ÒP_ROL: Y = {A, carry};
ÒP_ROR: Y = {A[0], carry, A[N-1:1]};
// binary operations
ÒP_OR: Y = {1'b0, A | B};
ÒP_AND: Y = {1'b0, A & B};
ÒP_XOR: Y = {1'b0, A ^ B};
// binary operations that generate and/or use carry
ÒP_ADD: Y = A + B;
ÒP_SUB: Y = A - B;
ÒP_ADC: Y = A + B + (carry?1:0);
ÒP_SBB: Y = A - B - (carry?1:0); carry

l
l CPU
l ALU
l RAM, ROM
l
l
2019/3/13 Nefrock in 21
CPU

l CPU
PC
l 1975 Taito Western Gun
l
l Apple CPU
2019/3/13 Nefrock in 22
CPU
https://www.arcade-
museum.com/game_detail.php?game_id=10420

l 8 8
256 RAM + ROM
l 256 ⇒ opcode
l opcode
1.
2.
2019/3/13 Nefrock in 24
FEMTO-8
IP : Instruction Pointer

l SELECT
l DECODE
data bus
COMPUTE READ_IP
l COMPUTE
ALU
carry, zero
l READ_IP
IP
2019/3/13 Nefrock in 26
CPU State Machine

2019/3/13 Nefrock in 27
RESET
// state 0: reset
S_RESET: begin
IP <= 8'h80; // instruction pointer = 128
write <= 0; // write disable
state <= S_SELECT; // next state
end
l RAM ROM
l ROM IP opcode
l SELECT

l IP
l IP
l DECODE
2019/3/13 Nefrock in 28
SELECT
// state 1: select opcode address
S_SELECT: begin
address <= IP;
IP <= IP + 1;
write <= 0;
state <= S_DECODE;
end

l opcode
l opcode
l casez case
2019/3/13 Nefrock in 29
DECODE
// state 2: read/decode opcode
S_DECODE: begin
opcode <= data_in; // (only use opcode next cycle)
casez (data_in)
// ALU A + B -> dest
8'b00??????: begin
state <= S_COMPUTE;
end
l 2 0
COMPUTE

l SELECT
2019/3/13 Nefrock in 30
COMPUTE
S_COMPUTE: begin
// transfer ALU output to destination
case (opdest)
`DEST_A: A <= Y[7:0];
`DEST_B: B <= Y[7:0];
`DEST_IP: IP <= Y[7:0];
`DEST_NOP: ;
endcase
// set carry for certain operations (4-7,12-15)
if (aluop[2]) carry <= Y[8];
// set zero flag
zero <= ~|Y[7:0];
// repeat CPU loop
state <= S_SELECT;
end
ALU Y
wire [1:0] opdest = opcode[5:4];
wire [3:0] aluop = opcode[3:0];
4-7 12-15 aluop
0 0

l Immediate instruction 2
1 opcode
1
2019/3/13 Nefrock in 31
Immediate instruction
wire B_or_data = opcode[6];
ALU alu(
.A(A),
.B(B_or_data ? data_in : B),
.Y(Y),
.aluop(aluop),
.carry(carry));
ALU B
// ALU A + immediate -> dest
8'b01??????: begin
address <= IP;
IP <= IP + 1;
state <= S_COMPUTE;
end
1
IP

2019/3/13 Nefrock in 32
// ALU A + read [B] -> dest
8'b11??????: begin
address <= B;
state <= S_COMPUTE;
end
// A -> write [nnnn]
8'b1001????: begin
address <= {4'b0, data_in[3:0]};
data_out <= A;
write <= 1;
state <= S_SELECT;
end
B
16
opcode 4

2019/3/13 Nefrock in 33
// swap A,B
8'b10000001: begin
A <= B;
B <= A;
state <= S_SELECT;
end

0001 branch if carry clear
0011 branch if carry set
0100 branch if zero clear
1100 branch if zero set
2019/3/13 Nefrock in 34
l IP
// conditional branch
8'b1010????: begin
if (
(data_in[0] && (data_in[1] == carry)) ||
(data_in[2] && (data_in[3] == zero)))
begin
address <= IP;
state <= S_READ_IP;
end else begin
state <= S_SELECT;
end
IP <= IP + 1; // skip immediate
end
// state 4: read new IP from memory (immediate mode)
S_READ_IP: begin
IP <= data_in;
state <= S_SELECT;
end
IP

l clock, reset, address_bus, data_bus, write_enable
l CPU
2019/3/13 Nefrock in 35
CPU
always @(posedge clk)
if (write_enable) begin
ram[address_bus[6:0]] <= from_cpu;
end
always @(*)
if (address_bus[7] == 0)
to_cpu = ram[address_bus[6:0]];
else
to_cpu = rom[address_bus[6:0]];
CPU 1
CPU cpu(.clk(clk),
.reset(reset),
.address(address_bus),
.data_in(to_cpu),
.data_out(from_cpu),
.write(write_enable));

Nefrock勉強会 in大岡山「FPGAでゲーム機を作ろう！の会」Day4

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Nefrock勉強会 in大岡山「FPGAでゲーム機を作ろう！の会」Day4