SlideShare a Scribd company logo
COMPUTER ORGANIZATION 10CS46
UNIT-7: “BASIC PROCESSING UNIT”
In this chapter we focus on the processing unit, which executes the machine
instructions and coordinates the activities of the other units. This unit is often called
instruction set processor (ISP) or simply a processor.
Some fundamental concepts
 Processor fetches one instruction at a time, and perform the operation specified.
 Instructions are fetched from successive memory locations until a branch or a
jump instruction is encountered.
 Processor keeps track of the address of the memory location containing the next
instruction to be fetched using Program Counter (PC).
 Instruction Register (IR) is the another key register in the processor
Executing an Instruction: To execute an instruction the processor has to perform the
following operations
 Fetch the contents of the memory location pointed to by the PC. The contents of
this location are loaded into the IR (fetch phase).
IR [[PC]]
 Assuming that the memory is byte addressable, increment the contents of the
PC by 4 (fetch phase).
PC [PC] + 4
 Carry out the actions specified by the instruction in the IR (execution phase).
Figureexplanation:
 ALU and all the registers are interconnected via a single common bus.
 The data and address lines of the external memory bus connected to the internal
processor bus via the memory data register, MDR, and the memory address
register, MAR respectively.
 Register MDR has two inputs and two outputs.
 Data may be loaded into MDR either from the memory bus or from the internal
processor bus.
 The data stored in MDR may be placed on either bus.
 The input of MAR is connected to the internal bus, and its output is connected to
the external bus.
 The control lines of the memory bus are connected to the instruction decoder
and control logic.
 This unit is responsible for issuing the signals that control the operation of all the
units inside the processor and for increasing with the memory bus.
 The MUX selects either the output of register Y or a constant value 4 to be
provided as input A of the ALU.
 The constant 4 is used to increment the contents of the program counter.
Figure:
2 | P a g e
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
Register Transfers
 Instruction execution involves a sequence of steps in which data are transferred
from one register to another.
 For each register two control signals are used to place the contents of that
register on the bus or to load the data on the bus into register.(in figure)
 The input and output of register Riin and Riout is set to 1, the data on the bus are
loaded into Ri.
 Similarly, when Ri out is set to 1, the contents of register Ri are placed on the
bus.
 While Riout is equal to 0, the bus can be used for transferring data from other
registers.
3 | P a g e
Example
Suppose we wish to transfer the contents of register R1 to register R4. This can be
accomplished as follows.
 Enable the output of registers R1 by setting R1out to 1. This places the contents
of R1 on the processor bus.
 Enable the input of register R4 by setting R4out to 1. This loads data from the
processor bus into register R4.
 All operations and data transfers within the take place within time periods
defined by the processor clock.
 The control signals that govern a particular transfer are asserted at the start of
the clock
4 | P a g e
Fig: input and output gating for one register bit.
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
Performing an Arithmetic or Logic Operation
The ALU is a combinational circuit that has no internal storage.
 ALU gets the two operands from MUX and bus. The result is temporarily
stored in register Z.
 What is the sequence of operations to add the contents of register R1 to those
of R2 and store the result in R3?
R1out, Yin
R2out, SelectY, Add, Zin
Zout, R3in
 All other signals are inactive.
 In step 1, the output of register R1 and the input of register Y are enabled,
causing the contents of R1 to be transferred over the bus to Y.
 Step 2, the multiplexer’s select signal is set to Select Y, causing the multiplexer to
gate the contents of register Y to input A of the ALU.
 At the same time, the contents of register R2 are gated onto the bus and, hence,
to input B.
 The function performed by the ALU depends on the signals applied to its control
lines.
 In this case, the ADD line is set to 1, causing the output of the ALU to be the sum
of the two numbers at inputs A and B.
 This sum is loaded into register Z because its input control signal is activated.
 In step 3, the contents of register Z are transferred to the destination register R3.
This last transfer cannot be carried out during step 2, because only one register
output can be connected to the bus during any clock cycle.
Fetching a Word from Memory
The processor has to specify the address of the memory location where this information
is stored and request a Read operation.
5 | P a g e
 This applies whether the information to be fetched represents an instruction
in a program or an operand specified by an instruction.
 The processor transfers the required addressto the MAR, whose output is
connected to the address lines of the memory bus.
Figure:
At the same time , the processor uses the control lines of the memory bus to indicate
that a Read operation is needed.
 When the requested data are received from the memory they are stored in
register MDR, from where they can be transferred to other registers in the
processor.
 The response time of each memory access varies (cache miss, memory-mapped
I/O,…).
 To accommodate this, the processor waits until it receives an indication that
the requested operation has been completed (Memory-Function-Completed,
MFC).
Move (R1), R2
MAR [R1]
Start a Read operation on the memory bus .
Wait for the MFC response from the memory
Load MDR from the memory bus
R2 [MDR]
 The output of MAR is enabled all the time.
 Thus the contents of MAR are always available on the address lines of the
memory bus.
 When a new address is loaded into MAR, it will appear on the memory bus at the
beginning of the next clock cycle.(in fig)
6 | P a g e
 A read control signal is activated at the same time MAR is loaded. This means
memory read operations requires three steps, which can be described by the
signals being activated as follows
R1out,MARin,Read
MDRinE,WMFC
MDRout,R2in
Execution of Branch Instructions
 A branch instruction replaces the contents of PC with the branch target address,
which is usually obtained by adding an offset X given in the branch instruction.
 The offset X is usually the difference between the branch target address and the
address immediately following the branch instruction.
Conditional branch
7 | P a g e
.......................................................................................................................................
Multiple bus organization
In a single bus only one data word can be transferred over the bus in a clock cycle .this
increases the steps required to complete the execution of the instruction. To reduce the
steps needed to complete the execution of the instruction, most commercial processor
provide multiple internal paths that enable several transfer to take place in parallel.
Hence, 3 buses are used to connect registers and the ALU of the processor.
The register file has 3ports; 1 input port & 2 output ports
8 | P a g e
So it is possible to access data of 3 reg on 1 clock cycle;
9 | P a g e
The value can be loaded in one register from bus C and data from 2 register can be
accessed to bus A and bus B. Buses A and B are used to transfer the source operands to
A and B i/ps of the ALU .After ALU operation the result is transferred to the destination
operand over the bus C.
To increment the value of PC after execution of each instruction to fetch the next
instruction , separate unit is provided this unit is called INCREMENTER . this
increments the contents of PC accordingly to the length of the instruction so that can
point to the next instruction in the sequence.
The incrementer eliminates the need of multiplexer connected at A input of ALU.
The control sequence is as shown as above. Note that the example shown here is ADD
R4 , R5 , R6. The examiner may also ask for ADD R1 , R2, R3. .
IMPORTANT TOPICS FROM EXAM POINT OF VIEW
1. ADD (R3) , R1. FOR THIS SEQUENCE OF INSTRUCTIONS THE PROCESSOR IS
DRIVEN BY CONTINUOUSLY RUNNING CLOCK SUCH THAT EACH CONTROL
STEP IS 2ns IN DURATION. HOW LONG WILL THE PROCESSOR HAVE TO WAIT
IN STEPS 2 & 5, ASSUMONG THAT A MEMORY READ OPERATION TAKES 16ns
TO COMPLETE? ALSO COMPUTE THE % OF TIME FOR WHICH THE PROCESSOR
IS IDLE DURING THE EXECUTION OF THE INSTRUCTION . (10 MARKS) (DEC-
2011 , JAN-10)
2. THREE (MULTIPLE) BUS ORGANIZATION (V.VIMP) (DEC-11,JUNE 11,12..)
3. EXPLANATION WITH NEAT DIAGRAM OF COMPLETE PROCESSOR (DEC-11)
(6 MARKS)
4. FETCHING A WORD FROM MEMORY (10 MARKS)
5. ADD R1 , (R3 ) (JULY-2011) (10 MARKS)
6. HARDWIRED CONTROL UNIT (DEC-2010) (10 MARKS)
7. HARDWIRED CONTROL UNIT & SHOW THE GENERATION OF Zin AND END
CONTROL SIGNALS. (JUNE-12) (10 MARKS)
8. CONTROL SEQUENCE FOR EXECUTION OF AN UNCONDITIONAL BRANCH
INSTRUCTION. (DEC-12) (10 MARKS)
10 | P a g e
11 | P a g e
12 | P a g e
The block diagram consists of a instruction unit , integer unit , floating-point unit,
instruction cache , data cache, bus interface unit, main memory module and i/p o/p
module.
 The instruction unit -> fetches instructions from an instruction cache or from
the main memory when the desired instructions are not available in the cache
 The complete processor provides two processing units
Integer unit &
Floating-point unit
Integer unit is used to process integer data & floating for floating point data.
These two units gets data from data cache.
Questions: (Dec 2011)
Write and explain the control sequences for the execution of the following
instruction. ADD (R3), R1. (10 marks)
13 | P a g e
Soltn: This instruction adds the contents of the memory locations specified by
register R1 and store the result in register R1 . to execute bus instruction it is
necessary to perform following action.
1. Fetch the instruction.
2. Fetch the operand from memory pointed by R3.
3. Store the result in R3.
4. Perform the addition.
Fig: control sequence for execution of the instruction ADD (R3) , R1.
Questions (exercise)
1. ADD R1 , (R3 )

More Related Content

What's hot (20)

PDF
Ch8 (1) morris mano
KIRTI89
 
PPT
Computer Organisation and Architecture
Subhasis Dash
 
PPT
Computer architecture register transfer languages rtl
Mazin Alwaaly
 
PPT
Bca 2nd sem-u-2.1-overview of register transfer, micro operations and basic c...
Rai University
 
PPTX
Addressing mode Computer Architecture
Haris456
 
PPTX
Chapter 8
Er. Nawaraj Bhandari
 
PPT
CO By Rakesh Roshan
Anurag University Hyderabad
 
PDF
8051 instruction set
Stefan Oprea
 
PDF
Computer organiztion4
Umang Gupta
 
PPTX
Chapter 4
Soumyajit Dutta
 
PPT
Data manipulation instructions
Mahesh Kumar Attri
 
PDF
COMPUTER ORGANIZATION NOTES Unit 2
Dr.MAYA NAYAK
 
PPT
central processing unit and pipeline
Rai University
 
PPT
Register transfer & microoperations moris mano ch 04
thearticlenow
 
PPT
Types of instructions
ihsanjamil
 
PPT
Instruction codes and computer registers
mahesh kumar prajapat
 
PPT
Parallel processing and pipelining
mahesh kumar prajapat
 
DOCX
Central processing unit
jyoti_lakhani
 
PDF
Arm instruction set
Mathivanan Natarajan
 
Ch8 (1) morris mano
KIRTI89
 
Computer Organisation and Architecture
Subhasis Dash
 
Computer architecture register transfer languages rtl
Mazin Alwaaly
 
Bca 2nd sem-u-2.1-overview of register transfer, micro operations and basic c...
Rai University
 
Addressing mode Computer Architecture
Haris456
 
CO By Rakesh Roshan
Anurag University Hyderabad
 
8051 instruction set
Stefan Oprea
 
Computer organiztion4
Umang Gupta
 
Chapter 4
Soumyajit Dutta
 
Data manipulation instructions
Mahesh Kumar Attri
 
COMPUTER ORGANIZATION NOTES Unit 2
Dr.MAYA NAYAK
 
central processing unit and pipeline
Rai University
 
Register transfer & microoperations moris mano ch 04
thearticlenow
 
Types of instructions
ihsanjamil
 
Instruction codes and computer registers
mahesh kumar prajapat
 
Parallel processing and pipelining
mahesh kumar prajapat
 
Central processing unit
jyoti_lakhani
 
Arm instruction set
Mathivanan Natarajan
 

Similar to 4th sem,(cs is),computer org unit-7 (20)

PPT
CO By Rakesh Roshan
Anurag University Hyderabad
 
PPT
Coa module2
cs19club
 
PDF
COMPUTER ORGANIZATION NOTES Unit 7
Dr.MAYA NAYAK
 
PDF
310471266 chapter-7-notes-computer-organization
srinoni
 
PDF
BCS302-DDCO-basic processing unit-Module 5- VTU 2022 scheme-DDCO-pdf
ciyamala kushbu
 
PPT
basic-processing-unit computer organ.ppt
ssuser702532
 
PPT
Computer Organization for third semester Vtu SyllabusModule 4.ppt
ShilpaKc3
 
PPT
Computer Organization Unit 4 Processor &Control Unit
AntonySuresh13
 
PDF
Computer Organization
JasmineShaik14
 
PPTX
COA-UNIT-III-FINAL (1).pptx
SMLAKKAVARAMRA211103
 
PPTX
Precessor organization
Asif Iqbal
 
PPTX
concept of computer organisation and architechture
bhazira0786
 
PPT
Basic processing unit by aniket bhute
Aniket Bhute
 
PPT
Unit2 control unit
Ashim Saha
 
PDF
Lecture6_Datapath_muceuok40lti_cycle.pdf
AmirMehdizadeh8
 
DOCX
Bc0040
hayerpa
 
PPTX
Presentation 4.pptx
IRAH34
 
PPT
Chapter 4 the processor
s9007912
 
PDF
cse211 power point presentation for engineering
VishnuVinay6
 
PPTX
Basic Computer Architecture slides num.3
MdRakibulIslam697135
 
CO By Rakesh Roshan
Anurag University Hyderabad
 
Coa module2
cs19club
 
COMPUTER ORGANIZATION NOTES Unit 7
Dr.MAYA NAYAK
 
310471266 chapter-7-notes-computer-organization
srinoni
 
BCS302-DDCO-basic processing unit-Module 5- VTU 2022 scheme-DDCO-pdf
ciyamala kushbu
 
basic-processing-unit computer organ.ppt
ssuser702532
 
Computer Organization for third semester Vtu SyllabusModule 4.ppt
ShilpaKc3
 
Computer Organization Unit 4 Processor &Control Unit
AntonySuresh13
 
Computer Organization
JasmineShaik14
 
COA-UNIT-III-FINAL (1).pptx
SMLAKKAVARAMRA211103
 
Precessor organization
Asif Iqbal
 
concept of computer organisation and architechture
bhazira0786
 
Basic processing unit by aniket bhute
Aniket Bhute
 
Unit2 control unit
Ashim Saha
 
Lecture6_Datapath_muceuok40lti_cycle.pdf
AmirMehdizadeh8
 
Bc0040
hayerpa
 
Presentation 4.pptx
IRAH34
 
Chapter 4 the processor
s9007912
 
cse211 power point presentation for engineering
VishnuVinay6
 
Basic Computer Architecture slides num.3
MdRakibulIslam697135
 
Ad

Recently uploaded (20)

PPTX
MULTI LEVEL DATA TRACKING USING COOJA.pptx
dollysharma12ab
 
PPTX
Precedence and Associativity in C prog. language
Mahendra Dheer
 
PDF
SE_Syllabus_NEP_Computer Science and Engineering ( IOT and Cyber Security Inc...
krshewale
 
PPTX
UNIT III CONTROL OF PARTICULATE CONTAMINANTS
sundharamm
 
PPTX
ENG8 Q1, WEEK 4.pptxoooiioooooooooooooooooooooooooo
chubbychubz1
 
PDF
An Evaluative Study on Performance Growth Plan of ICICI Mutual Fund and SBI M...
PoonamKilaniya
 
PDF
th International conference on Big Data, Machine learning and Applications (B...
Zac Darcy
 
PDF
Introduction to Robotics Mechanics and Control 4th Edition by John J. Craig S...
solutionsmanual3
 
PDF
MOBILE AND WEB BASED REMOTE BUSINESS MONITORING SYSTEM
ijait
 
PDF
Web Technologies - Chapter 3 of Front end path.pdf
reemaaliasker
 
PDF
IEEE EMBC 2025 「Improving electrolaryngeal speech enhancement via a represent...
NU_I_TODALAB
 
PPTX
Sensor IC System Design Using COMSOL Multiphysics 2025-July.pptx
James D.B. Wang, PhD
 
PDF
CFM 56-7B - Engine General Familiarization. PDF
Gianluca Foro
 
PPTX
ENSA_Module_8.pptx_nice_ipsec_presentation
RanaMukherjee24
 
PDF
PRIZ Academy - Change Flow Thinking Master Change with Confidence.pdf
PRIZ Guru
 
PDF
A presentation on the Urban Heat Island Effect
studyfor7hrs
 
PDF
NOISE CONTROL ppt - SHRESTH SUDHIR KOKNE
SHRESTHKOKNE
 
PDF
Jual GPS Geodetik CHCNAV i93 IMU-RTK Lanjutan dengan Survei Visual
Budi Minds
 
PPTX
Water resources Engineering GIS KRT.pptx
Krunal Thanki
 
PPTX
00-ClimateChangeImpactCIAProcess_PPTon23.12.2024-ByDr.VijayanGurumurthyIyer1....
praz3
 
MULTI LEVEL DATA TRACKING USING COOJA.pptx
dollysharma12ab
 
Precedence and Associativity in C prog. language
Mahendra Dheer
 
SE_Syllabus_NEP_Computer Science and Engineering ( IOT and Cyber Security Inc...
krshewale
 
UNIT III CONTROL OF PARTICULATE CONTAMINANTS
sundharamm
 
ENG8 Q1, WEEK 4.pptxoooiioooooooooooooooooooooooooo
chubbychubz1
 
An Evaluative Study on Performance Growth Plan of ICICI Mutual Fund and SBI M...
PoonamKilaniya
 
th International conference on Big Data, Machine learning and Applications (B...
Zac Darcy
 
Introduction to Robotics Mechanics and Control 4th Edition by John J. Craig S...
solutionsmanual3
 
MOBILE AND WEB BASED REMOTE BUSINESS MONITORING SYSTEM
ijait
 
Web Technologies - Chapter 3 of Front end path.pdf
reemaaliasker
 
IEEE EMBC 2025 「Improving electrolaryngeal speech enhancement via a represent...
NU_I_TODALAB
 
Sensor IC System Design Using COMSOL Multiphysics 2025-July.pptx
James D.B. Wang, PhD
 
CFM 56-7B - Engine General Familiarization. PDF
Gianluca Foro
 
ENSA_Module_8.pptx_nice_ipsec_presentation
RanaMukherjee24
 
PRIZ Academy - Change Flow Thinking Master Change with Confidence.pdf
PRIZ Guru
 
A presentation on the Urban Heat Island Effect
studyfor7hrs
 
NOISE CONTROL ppt - SHRESTH SUDHIR KOKNE
SHRESTHKOKNE
 
Jual GPS Geodetik CHCNAV i93 IMU-RTK Lanjutan dengan Survei Visual
Budi Minds
 
Water resources Engineering GIS KRT.pptx
Krunal Thanki
 
00-ClimateChangeImpactCIAProcess_PPTon23.12.2024-ByDr.VijayanGurumurthyIyer1....
praz3
 
Ad

4th sem,(cs is),computer org unit-7

  • 1. COMPUTER ORGANIZATION 10CS46 UNIT-7: “BASIC PROCESSING UNIT” In this chapter we focus on the processing unit, which executes the machine instructions and coordinates the activities of the other units. This unit is often called instruction set processor (ISP) or simply a processor. Some fundamental concepts  Processor fetches one instruction at a time, and perform the operation specified.  Instructions are fetched from successive memory locations until a branch or a jump instruction is encountered.  Processor keeps track of the address of the memory location containing the next instruction to be fetched using Program Counter (PC).  Instruction Register (IR) is the another key register in the processor Executing an Instruction: To execute an instruction the processor has to perform the following operations  Fetch the contents of the memory location pointed to by the PC. The contents of this location are loaded into the IR (fetch phase). IR [[PC]]  Assuming that the memory is byte addressable, increment the contents of the PC by 4 (fetch phase). PC [PC] + 4  Carry out the actions specified by the instruction in the IR (execution phase). Figureexplanation:  ALU and all the registers are interconnected via a single common bus.  The data and address lines of the external memory bus connected to the internal processor bus via the memory data register, MDR, and the memory address register, MAR respectively.  Register MDR has two inputs and two outputs.  Data may be loaded into MDR either from the memory bus or from the internal processor bus.  The data stored in MDR may be placed on either bus.  The input of MAR is connected to the internal bus, and its output is connected to the external bus.  The control lines of the memory bus are connected to the instruction decoder and control logic.  This unit is responsible for issuing the signals that control the operation of all the units inside the processor and for increasing with the memory bus.  The MUX selects either the output of register Y or a constant value 4 to be provided as input A of the ALU.  The constant 4 is used to increment the contents of the program counter. Figure:
  • 2. 2 | P a g e >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> Register Transfers  Instruction execution involves a sequence of steps in which data are transferred from one register to another.  For each register two control signals are used to place the contents of that register on the bus or to load the data on the bus into register.(in figure)  The input and output of register Riin and Riout is set to 1, the data on the bus are loaded into Ri.  Similarly, when Ri out is set to 1, the contents of register Ri are placed on the bus.  While Riout is equal to 0, the bus can be used for transferring data from other registers.
  • 3. 3 | P a g e Example Suppose we wish to transfer the contents of register R1 to register R4. This can be accomplished as follows.  Enable the output of registers R1 by setting R1out to 1. This places the contents of R1 on the processor bus.  Enable the input of register R4 by setting R4out to 1. This loads data from the processor bus into register R4.  All operations and data transfers within the take place within time periods defined by the processor clock.  The control signals that govern a particular transfer are asserted at the start of the clock
  • 4. 4 | P a g e Fig: input and output gating for one register bit. >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> Performing an Arithmetic or Logic Operation The ALU is a combinational circuit that has no internal storage.  ALU gets the two operands from MUX and bus. The result is temporarily stored in register Z.  What is the sequence of operations to add the contents of register R1 to those of R2 and store the result in R3? R1out, Yin R2out, SelectY, Add, Zin Zout, R3in  All other signals are inactive.  In step 1, the output of register R1 and the input of register Y are enabled, causing the contents of R1 to be transferred over the bus to Y.  Step 2, the multiplexer’s select signal is set to Select Y, causing the multiplexer to gate the contents of register Y to input A of the ALU.  At the same time, the contents of register R2 are gated onto the bus and, hence, to input B.  The function performed by the ALU depends on the signals applied to its control lines.  In this case, the ADD line is set to 1, causing the output of the ALU to be the sum of the two numbers at inputs A and B.  This sum is loaded into register Z because its input control signal is activated.  In step 3, the contents of register Z are transferred to the destination register R3. This last transfer cannot be carried out during step 2, because only one register output can be connected to the bus during any clock cycle. Fetching a Word from Memory The processor has to specify the address of the memory location where this information is stored and request a Read operation.
  • 5. 5 | P a g e  This applies whether the information to be fetched represents an instruction in a program or an operand specified by an instruction.  The processor transfers the required addressto the MAR, whose output is connected to the address lines of the memory bus. Figure: At the same time , the processor uses the control lines of the memory bus to indicate that a Read operation is needed.  When the requested data are received from the memory they are stored in register MDR, from where they can be transferred to other registers in the processor.  The response time of each memory access varies (cache miss, memory-mapped I/O,…).  To accommodate this, the processor waits until it receives an indication that the requested operation has been completed (Memory-Function-Completed, MFC). Move (R1), R2 MAR [R1] Start a Read operation on the memory bus . Wait for the MFC response from the memory Load MDR from the memory bus R2 [MDR]  The output of MAR is enabled all the time.  Thus the contents of MAR are always available on the address lines of the memory bus.  When a new address is loaded into MAR, it will appear on the memory bus at the beginning of the next clock cycle.(in fig)
  • 6. 6 | P a g e  A read control signal is activated at the same time MAR is loaded. This means memory read operations requires three steps, which can be described by the signals being activated as follows R1out,MARin,Read MDRinE,WMFC MDRout,R2in Execution of Branch Instructions  A branch instruction replaces the contents of PC with the branch target address, which is usually obtained by adding an offset X given in the branch instruction.  The offset X is usually the difference between the branch target address and the address immediately following the branch instruction. Conditional branch
  • 7. 7 | P a g e ....................................................................................................................................... Multiple bus organization In a single bus only one data word can be transferred over the bus in a clock cycle .this increases the steps required to complete the execution of the instruction. To reduce the steps needed to complete the execution of the instruction, most commercial processor provide multiple internal paths that enable several transfer to take place in parallel. Hence, 3 buses are used to connect registers and the ALU of the processor. The register file has 3ports; 1 input port & 2 output ports
  • 8. 8 | P a g e So it is possible to access data of 3 reg on 1 clock cycle;
  • 9. 9 | P a g e The value can be loaded in one register from bus C and data from 2 register can be accessed to bus A and bus B. Buses A and B are used to transfer the source operands to A and B i/ps of the ALU .After ALU operation the result is transferred to the destination operand over the bus C. To increment the value of PC after execution of each instruction to fetch the next instruction , separate unit is provided this unit is called INCREMENTER . this increments the contents of PC accordingly to the length of the instruction so that can point to the next instruction in the sequence. The incrementer eliminates the need of multiplexer connected at A input of ALU. The control sequence is as shown as above. Note that the example shown here is ADD R4 , R5 , R6. The examiner may also ask for ADD R1 , R2, R3. . IMPORTANT TOPICS FROM EXAM POINT OF VIEW 1. ADD (R3) , R1. FOR THIS SEQUENCE OF INSTRUCTIONS THE PROCESSOR IS DRIVEN BY CONTINUOUSLY RUNNING CLOCK SUCH THAT EACH CONTROL STEP IS 2ns IN DURATION. HOW LONG WILL THE PROCESSOR HAVE TO WAIT IN STEPS 2 & 5, ASSUMONG THAT A MEMORY READ OPERATION TAKES 16ns TO COMPLETE? ALSO COMPUTE THE % OF TIME FOR WHICH THE PROCESSOR IS IDLE DURING THE EXECUTION OF THE INSTRUCTION . (10 MARKS) (DEC- 2011 , JAN-10) 2. THREE (MULTIPLE) BUS ORGANIZATION (V.VIMP) (DEC-11,JUNE 11,12..) 3. EXPLANATION WITH NEAT DIAGRAM OF COMPLETE PROCESSOR (DEC-11) (6 MARKS) 4. FETCHING A WORD FROM MEMORY (10 MARKS) 5. ADD R1 , (R3 ) (JULY-2011) (10 MARKS) 6. HARDWIRED CONTROL UNIT (DEC-2010) (10 MARKS) 7. HARDWIRED CONTROL UNIT & SHOW THE GENERATION OF Zin AND END CONTROL SIGNALS. (JUNE-12) (10 MARKS) 8. CONTROL SEQUENCE FOR EXECUTION OF AN UNCONDITIONAL BRANCH INSTRUCTION. (DEC-12) (10 MARKS)
  • 10. 10 | P a g e
  • 11. 11 | P a g e
  • 12. 12 | P a g e The block diagram consists of a instruction unit , integer unit , floating-point unit, instruction cache , data cache, bus interface unit, main memory module and i/p o/p module.  The instruction unit -> fetches instructions from an instruction cache or from the main memory when the desired instructions are not available in the cache  The complete processor provides two processing units Integer unit & Floating-point unit Integer unit is used to process integer data & floating for floating point data. These two units gets data from data cache. Questions: (Dec 2011) Write and explain the control sequences for the execution of the following instruction. ADD (R3), R1. (10 marks)
  • 13. 13 | P a g e Soltn: This instruction adds the contents of the memory locations specified by register R1 and store the result in register R1 . to execute bus instruction it is necessary to perform following action. 1. Fetch the instruction. 2. Fetch the operand from memory pointed by R3. 3. Store the result in R3. 4. Perform the addition. Fig: control sequence for execution of the instruction ADD (R3) , R1. Questions (exercise) 1. ADD R1 , (R3 )