Floating point butterfly architecture based on binary signed-digit representation
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The document discusses a novel floating-point butterfly architecture using binary signed-digit (BSD) representation to enhance the performance of Fast Fourier Transform (FFT) coprocessors. It introduces a fused-dotproduct-add (FDPA) unit for efficient computation while mitigating slowness found in traditional floating-point designs, employing optimizations like carry-limited addition and modified Booth encoding. Synthesis results indicate that this new architecture achieves superior speed compared to prior designs, although it requires more area for implementation.
Floating point butterfly architecture based on binary signed-digit representation
- 1. FLOATING-POINT BUTTERFLY ARCHITECTURE BASED ON BINARY SIGNED-DIGIT REPRESENTATION ABSTRACT: Fast Fourier transform (FFT) coprocessor, having a significant impact on the performance of communication systems, has been a hot topic of research for many years. The FFT function consists of consecutive multiply add operations over complex numbers, dubbed as butterfly units. Applying floating-point (FP) arithmetic to FFT architectures, specifically butterfly units, has become more popular recently. It offloads compute-intensive tasks from general-purpose processors by dismissing FP concerns (e.g., scaling and overflow/underflow). However, the major downside of FP butterfly is its slowness in comparison with its fixed-point counterpart. This reveals the incentive to develop a high-speed FP butterfly architecture to mitigate FP slowness. This brief proposes a fast FP butterfly unit using a devised FP fused- dotproduct- add (FDPA) unit, to compute AB ± CD ±E, based on binarysigned- digit (BSD) representation. The FP three-operand BSD adder and the FP BSD constant multiplier are the constituents of the proposed FDPA unit. A carry-limited BSD adder is proposed and used in the three-operand adder and the parallel BSD multiplier so as to improve the speed of the FDPA unit. Moreover, modified Booth encoding is used to accelerate the BSD multiplier. The synthesis results show that the proposed FP butterfly architecture is much faster than previous counterparts but at the cost of more area.