B.sc cs-ii-u-3.2-basic computer programming and micro programmed control

Basic Computer Programming and
Micro Programmed Control
Course: B.Sc-CS-II
Subject: Computer Organization
And Architecture
Unit-3
1

Control Unit Implementation[1]
2
• Hardwired
• Microprogrammed
Instruction code
Combinational
Logic Circuits
Memory
Sequence Counter
.
.
Control
signals
Control
signals
Next Address
Generator
(sequencer)
CAR Control
Memory
CDR Decoding
Circuit
Memory
.
.
CAR: Control Address Register
CDR: Control Data RegisterInstruction code

Microprogrammed Control Unit
• Control signals
– Group of bits used to select paths in multiplexers, decoders,
arithmetic logic units
• Control variables
– Binary variables specify microoperations
• Certain microoperations initiated while others idle
• Control word
– String of 1’s and 0’s represent control variables
3

Microprogrammed Control Unit
• Control memory
– Memory contains control words
• Microinstructions
– Control words stored in control memory
– Specify control signals for execution of
microoperations
• Microprogram
– Sequence of microinstructions
4

Control Memory
• Read-only memory (ROM)
• Content of word in ROM at given address specifies
microinstruction
• Each computer instruction initiates series of microinstructions
(microprogram) in control memory
• These microinstructions generate microoperations to
– Fetch instruction from main memory
– Evaluate effective address
– Execute operation specified by instruction
– Return control to fetch phase for next instruction
5
Control
memory
(ROM)
Control word
(microinstruction)
Address

Microprogrammed Control Organization
• Control memory
– Contains microprograms (set of microinstructions)
– Microinstruction contains
• Bits initiate microoperations
• Bits determine address of next microinstruction
• Control address register (CAR)
– Specifies address of next microinstruction
6
Control
word
Next Address
Generator
(sequencer)
CAR
Control
Memory
(ROM)
CDR
External
input

• Next address generator (microprogram sequencer)
– Determines address sequence for control memory
• Microprogram sequencer functions
– Increment CAR by one
– Transfer external address into CAR
– Load initial address into CAR to start control operations
7

• Control data register (CDR)- or pipeline register
– Holds microinstruction read from control memory
– Allows execution of microoperations specified by control
word simultaneously with generation of next microinstruction
• Control unit can operate without CDR
8
Control
word
Next Address
Generator
(sequencer)
CAR
Control
Memory
(ROM)
External
input

Microprogram Routines
• Routine
– Group of microinstructions stored in control
memory
• Each computer instruction has its own
microprogram routine to generate
microoperations that execute the instruction
9

Microprogram Routines
• Subroutine
– Sequence of microinstructions used by other routines to
accomplish particular task
• Example
– Subroutine to generate effective address of operand for
memory reference instruction
• Subroutine register (SBR)
– Stores return address during subroutine call
10

Conditional Branching
• Branching from one routine to another depends
on status bit conditions
• Status bits provide parameter info such as
– Carry-out of adder
– Sign bit of number
– Mode bits of instruction
• Info in status bits can be tested and actions
initiated based on their conditions: 1 or 0
• Unconditional branch
– Fix value of status bit to 1
11

Mapping of Instruction[2]
• Each computer instruction has its own
microprogram routine stored in a given
location of the control memory
• Mapping
– Transformation from instruction code bits to
address in control memory where routine is located
12

Mapping of Instruction
• Example
– Mapping 4-bit operation code to 7-bit address
13
OP-codes of Instructions
ADD
AND
LDA
0000
0001
0010
Address
0 0000 00
0 0001 00
0 0010 00
Mapping bits 0 xxxx 00
ADD Routine
AND Routine
LDA Routine
Control
memory

Address Sequencing[2]
• Address sequencing capabilities required in
control unit
– Incrementing CAR
– Unconditional or conditional branch, depending on
status bit conditions
– Mapping from bits of instruction to address for
control memory
– Facility for subroutine call and return
14

Address Sequencing
15
Instruction code
Mapping
logic
Multiplexers
Control memory (ROM)
Subroutine
Register
(SBR)
Branch
logic
Status
bits
Microoperations
Control Address Register
(CAR)
Incrementer
MUX
select
select a status
bit
Branch address

Microprogram Example[3]
16
Computer
Configuration
MUX
AR
10 0
PC
10 0
Address Memory
2048 x 16
MUX
DR
15 0
Arithmetic
logic and
shift unit
AC
15 0
SBR
6 0
CAR
6 0
Control memory
128 x 20
Control unit

Microprogram Example
17
Microinstruction Format
EA is the effective address
Symbol OP-code Description
ADD 0000 AC ← AC + M[EA]
BRANCH 0001 if (AC < 0) then (PC ← EA)
STORE 0010 M[EA] ← AC
EXCHANGE 0011 AC ← M[EA], M[EA] ← AC
Computer instruction format
I Opcode
15 14 11 10
Address
0
Four computer instructions
F1 F2 F3 CD BR AD
3 3 3 2 2 7
F1, F2, F3: Microoperation fields
CD: Condition for branching
BR: Branch field
AD: Address field

Microinstruction Fields
18
F1 Microoperation Symbol
000 None NOP
001 AC ← AC + DR ADD
010 AC ← 0 CLRAC
011 AC ← AC + 1 INCAC
100 AC ← DR DRTAC
101 AR ← DR(0-10) DRTAR
110 AR ← PC PCTAR
111 M[AR] ← DR WRITE
000 None NOP
001 AC ← AC - DR SUB
010 AC ← AC ∨ DR OR
011 AC ← AC ∧ DR AND
100 DR ← M[AR] READ
101 DR ← AC ACTDR
110 DR ← DR + 1 INCDR
111 DR(0-10) ← PC PCTDR
000 None NOP
001 AC ← AC ⊕ DR XOR
010 AC ← AC’ COM
011 AC ← shl AC SHL
100 AC ← shr AC SHR
101 PC ← PC + 1 INCPC
110 PC ← AR ARTPC
111 Reserved

Microinstruction Fields
19
CD Condition Symbol Comments
00 Always = 1 U Unconditional branch
01 DR(15) I Indirect address bit
10 AC(15) S Sign bit of AC
11 AC = 0 Z Zero value in AC
BR Symbol Function
00 JMP CAR ← AD if condition = 1
CAR ← CAR + 1 if condition = 0
01 CALL CAR ← AD, SBR ← CAR + 1 if condition = 1
CAR ← CAR + 1 if condition = 0
10 RET CAR ← SBR (Return from subroutine)
11 MAP CAR(2-5) ← DR(11-14), CAR(0,1,6) ← 0

Symbolic Microinstruction
20
 Sample Format Label: Micro-ops CD BR AD
 Label may be empty or may specify symbolic address
terminated with colon
 Micro-ops consists of 1, 2, or 3 symbols separated by commas
 CD one of {U, I, S, Z}
U: Unconditional Branch
I: Indirect address bit
S: Sign of AC
Z: Zero value in AC
 BR one of {JMP, CALL, RET, MAP}
 AD one of {Symbolic address, NEXT, empty}

Fetch Routine
21
 Fetch routine
- Read instruction from memory
- Decode instruction and update PC
AR ← PC
DR ← M[AR], PC ← PC + 1
AR ← DR(0-10), CAR(2-5) ← DR(11-14), CAR(0,1,6) ← 0
Symbolic microprogram for fetch routine:
ORG 64
PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP
FETCH:
Binary microporgram for fetch routine:
1000000 110 000 000 00 00 1000001
1000001 000 100 101 00 00 1000010
1000010 101 000 000 00 11 0000000
Binary
address F1 F2 F3 CD BR AD
Microinstructions for fetch routine:

Symbolic Microprogram
22
• Control memory: 128 20-bit words
• First 64 words: Routines for 16 machine instructions
• Last 64 words: Used for other purpose (e.g., fetch routine and other subroutines)
• Mapping: OP-code XXXX into 0XXXX00, first address for 16 routines are
0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60
ORG 0
NOP
READ
ADD
ORG 4
NOP
NOP
NOP
ARTPC
ORG 8
NOP
ACTDR
WRITE
ORG 12
NOP
READ
ACTDR, DRTAC
WRITE
ORG 64
PCTAR
READ, INCPC
DRTAR
READ
DRTAR
I
U
U
S
U
I
U
I
U
U
I
U
U
U
U
U
U
U
U
CALL
JMP
JMP
JMP
JMP
CALL
JMP
CALL
JMP
JMP
CALL
JMP
JMP
JMP
JMP
JMP
MAP
JMP
RET
INDRCT
NEXT
FETCH
OVER
FETCH
INDRCT
FETCH
INDRCT
NEXT
FETCH
INDRCT
NEXT
NEXT
FETCH
NEXT
NEXT
NEXT
ADD:
BRANCH:
OVER:
STORE:
EXCHANGE:
FETCH:
INDRCT:
Label Microops CD BR AD
Partial Symbolic Microprogram

Binary Microprogram
23
Address Binary Microinstruction
Micro Routine Decimal Binary F1 F2 F3 CD BR AD
ADD 0 0000000 000 000 000 01 01 1000011
1 0000001 000 100 000 00 00 0000010
2 0000010 001 000 000 00 00 1000000
3 0000011 000 000 000 00 00 1000000
BRANCH 4 0000100 000 000 000 10 00 0000110
5 0000101 000 000 000 00 00 1000000
6 0000110 000 000 000 01 01 1000011
7 0000111 000 000 110 00 00 1000000
STORE 8 0001000 000 000 000 01 01 1000011
9 0001001 000 101 000 00 00 0001010
10 0001010 111 000 000 00 00 1000000
11 0001011 000 000 000 00 00 1000000
EXCHANGE 12 0001100 000 000 000 01 01 1000011
13 0001101 001 000 000 00 00 0001110
14 0001110 100 101 000 00 00 0001111
15 0001111 111 000 000 00 00 1000000
FETCH 64 1000000 110 000 000 00 00 1000001
65 1000001 000 100 101 00 00 1000010
66 1000010 101 000 000 00 11 0000000
INDRCT 67 1000011 000 100 000 00 00 1000100
68 1000100 101 000 000 00 10 0000000

Design of Control Unit[4]
24
microoperation fields
3 x 8 decoder
7 6 5 4 3 2 1 0
F1
3 x 8 decoder
7 6 5 4 3 2 1 0
F2
3 x 8 decoder
7 6 5 4 3 2 1 0
F3
Arithmetic
logic and
shift unit
AND
ADD
DRTAC
AC
Load
From
PC
From
DR(0-10)
Select 0 1
Multiplexers
AR
Load Clock
AC
DR
DRTAR
PCTAR

Microprogram Sequencer
25
3 2 1 0
S1 MUX1
External
(MAP)
SBR
Load
Incrementer
CAR
Input
logic
I0
T
MUX2
Select
1
I
S
Z
Test
Clock
Control memory
Microops CD BR AD
L
I1
S0
. . .. . .

Input Logic for Microprogram Sequencer
26
Input
logicI0
I
1
T
MUX2
Select
1
I
S
Z
Test
CD Field of CS
From
CPU BR field
of CS
L(load SBR with PC)
for subroutine Call
S0
S1
for next address
selection
I1I0T Meaning Source of Address S1S0 L
000 In-Line CAR+1 00 0
001 JMP CS(AD) 01 0
010 In-Line CAR+1 00 0
011 CALL CS(AD) and SBR <- CAR+1 01 1
10x RET SBR 10 0
11x MAP DR(11-14) 11 0
L
S1 = I1
S0 = I0I1 + I1’T
L = I1’I0T
Input Logic

References
1. Computer Organization and Architecture,
Designing for performance by William Stallings,
Prentice Hall of India.
2. Modern Computer Architecture, by Morris Mano,
Prentice Hall of India.
3. Computer Architecture and Organization by John P.
Hayes, McGraw Hill Publishing Company.
4. Computer Organization by V. Carl Hamacher,
Zvonko G. Vranesic, Safwat G. Zaky, McGraw Hill
Publishing Company.

B.sc cs-ii-u-3.2-basic computer programming and micro programmed control

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