02~chapter 01 intro.ppt
- 1. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 1 1 Chapter 1 Introduction
- 2. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 2 2 What is this chapter about? Introduce fundamental concepts and various aspects of VLSI testing Focus on Importance of testing in the design and manufacturing processes Challenges in test generation and fault modeling Levels of abstraction in VLSI testing Provide overview of VLSI test technology
- 3. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 3 3 Introduction to VLSI Testing Introduction Testing During VLSI Life Cycle Test Generation Fault Models Levels of Abstraction Overview of Test Technology Concluding Remarks
- 4. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 4 4 Introduction Integrated Circuits (ICs) have grown in size and complexity since the late 1950’s Small Scale Integration (SSI) Medium Scale Integration (MSI) Large Scale Integration (LSI) Very Large Scale Integration (VLSI) Moore’s Law: scale of ICs doubles every 18 months Growing size and complexity poses many and new testing challenges 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1960s 1970s 1980s 1990s 2000s Number of Transistors VLSI LSI M S I S S I
- 5. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 5 5 Importance of Testing Moore’s Law results from decreasing feature size (dimensions) from 10s of m to 10s of nm for transistors and interconnecting wires Operating frequencies have increased from 100KHz to several GHz Decreasing feature size increases probability of defects during manufacturing process A single faulty transistor or wire results in faulty IC Testing required to guarantee fault-free products
- 6. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 6 6 Importance of Testing Rule of Ten: cost to detect faulty IC increases by an order of magnitude as we move from: device PCB system field operation – Testing performed at all of these levels Testing also used during Manufacturing to improve yield – Failure mode analysis (FMA) Field operation to ensure fault-free system operation – Initiate repairs when faults are detected
- 7. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 7 7 Testing During VLSI Life Cycle Testing typically consists of Applying set of test stimuli to Inputs of circuit under test (CUT), and Analyzing output responses – If incorrect (fail), CUT assumed to be faulty – If correct (pass), CUT assumed to be fault-free Pass/Fail Circuit Under Test (CUT) Input Test Stimuli Output Response Analysis Output1 Outputm Input1 Inputn
- 8. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 8 8 Testing During VLSI Development Design verification targets design errors Corrections made prior to fabrication Remaining tests target manufacturing defects A defect is a flaw or physical imperfection that can lead to a fault Design Verification Wafer Test Final Testing Package Test Design Specification Design Fabrication Quality Assurance Packaging
- 9. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 9 9 Design Verification Different levels of abstraction during design CAD tools used to synthesize design from RTL to physical level Simulation used at various level to test for Design errors in behavioral or RTL Design meeting system timing requirements after synthesis Design Specification Behavioral (Architecture) Level Register-Transfer Level Logical (Gate) Level Physical (Transistor) Level
- 10. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 10 10 Yield and Reject Rate We expect faulty chips due to manufacturing defects Called yield 2 types of yield loss Catastrophic – due to random defects Parametric – due to process variations Undesirable results during testing Faulty chip appears to be good (passes test) – Called reject rate Good chip appears to be faulty (fails test) – Due to poorly designed tests or lack of DFT ed s fabricat er of part total numb parts acceptable number of yield final test s passing er of part total numb t final tes ts passing faulty par number of e reject rat
- 11. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 11 11 Electronic System Manufacturing A system consists of PCBs that consist of – VLSI devices PCB fabrication similar to VLSI fabrication Susceptible to defects Assembly steps also susceptible to defects Testing performed at all stages of manufacturing Bare Board Test Board Test System Test Unit Test PCB Fabrication PCB Assembly System Assembly Unit Assembly
- 12. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 12 12 System-Level Operation Faults occur during system operation Exponential failure law Interval of normal system operation is random number exponentially distributed Reliability Probability that system will operate normally until time t Failure rate, , is sum of individual component failure rates, i t n e t T P ) ( k i i 0 t0 t1 t2 t3 t4 t S 1 0 failures Normal system operation
- 13. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 13 13 System-Level Operation Mean Time Between Failures (MTBF) Repair time (R) also assumed to obey exponential distribution is repair rate Mean Time To Repair (MTTR) Fraction of time that system is operating normally called system availability High reliability systems have system availabilities greater than 0.9999 – Referred to as “four 9s” 1 0 dt e MTBF t 1 MTTR MTTR MTBF MTBF ilability system ava t e t R P ) (
- 14. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 14 14 System-Level Testing Testing required to ensure system availability Types of system-level testing On-line testing – concurrent with system operation Off-line testing – while system (or portion of) is taken out of service – Performed periodically during low-demand periods – Used for diagnosis (identification and location) of faulty replaceable components to improve repair time
- 15. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 15 15 Test Generation A test is a sequence of test patterns, called test vectors, applied to the CUT whose outputs are monitored and analyzed for the correct response Exhaustive testing – applying all possible test patterns to CUT Functional testing – testing every truth table entry for a combinational logic CUT – Neither of these are practical for large CUTs Fault coverage is a quantitative measure of quality of a set of test vectors
- 16. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 16 16 Test Generation Fault coverage for a given set of test vectors 100% fault coverage may be impossible due to undetectable faults Reject rate = 1 – yield(1 – fault coverage) A PCB with 40 chips, each with 90% fault coverage and 90% yield, has a reject rate of 41.9% – Or 419,000 defective parts per million (PPM) ts er of faul total numb aults detected f number of rage fault cove le faults undetectab number of ts er of faul total numb aults detected f number of efficiency ction fault dete
- 17. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 17 17 Test Generation Goal: find efficient set of test vectors with maximum fault coverage Fault simulation used to determine fault coverage Requires fault models to emulate behavior of defects A good fault model: Is computationally efficient for simulation Accurately reflects behavior of defects No single fault model works for all possible defects
- 18. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 18 18 Fault Models A given fault model has k types of faults k = 2 for most fault models A given circuit has n possible fault sites Multiple fault model –circuit can have multiple faults (including single faults Number of multiple fault = (k+1)n-1 – Each fault site can have 1-of-k fault types or be fault-free – The “-1” represents the fault-free circuit Impractical for anything but very small circuits Single fault model – circuit has only 1 fault Number of single faults = k×n Good single fault coverage generally implies good multiple fault coverage
- 19. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 19 19 Fault Models Equivalent faults One or more single faults that have identical behavior for all possible input patterns Only one fault from a set of equivalent faults needs to be simulated Fault collapsing Removing equivalent faults – Except for one to be simulated Reduces total number of faults – Reduces fault simulation time – Reduces test pattern generation time
- 20. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 20 20 Stuck-at Faults x1 x2 x3 y a b c d e f g h i x1x2x3 000 001 010 011 100 101 110 111 y 0 1 0 0 0 1 1 1 a SA0 0 1 0 0 0 1 0 0 a SA1 0 1 1 1 0 1 1 1 b SA0 0 1 0 1 0 1 0 1 b SA1 0 0 0 0 1 1 1 1 c SA0 0 0 0 0 0 0 1 1 c SA1 1 1 0 0 1 1 1 1 d SA0 0 1 0 0 0 1 0 0 d SA1 0 1 0 0 1 1 1 1 e SA0 0 1 0 1 0 1 1 1 e SA1 0 0 0 0 0 0 1 1 f SA0 0 0 0 0 0 0 1 1 f SA1 0 1 0 1 0 1 1 1 g SA0 0 1 0 0 0 1 0 0 g SA1 1 1 1 1 1 1 1 1 h SA0 0 0 0 0 0 0 1 1 h SA1 1 1 1 1 1 1 1 1 i SA0 0 0 0 0 0 0 0 0 i SA1 1 1 1 1 1 1 1 1 Any line can be Stuck-at-0 (SA0) Stuck-at-1 (SA1) # fault types: k=2 Example circuit: # fault sites: n=9 # single faults =2×9=18 Truth table for fault-free behavior and behavior of all possible stuck-at faults
- 21. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 21 21 Stuck-at Faults x1 x2 x3 y a b c d e f g h i x1x2x3 000 001 010 011 100 101 110 111 y 0 1 0 0 0 1 1 1 a SA0 0 1 0 0 0 1 0 0 a SA1 0 1 1 1 0 1 1 1 b SA0 0 1 0 1 0 1 0 1 b SA1 0 0 0 0 1 1 1 1 c SA0 0 0 0 0 0 0 1 1 c SA1 1 1 0 0 1 1 1 1 d SA0 0 1 0 0 0 1 0 0 d SA1 0 1 0 0 1 1 1 1 e SA0 0 1 0 1 0 1 1 1 e SA1 0 0 0 0 0 0 1 1 f SA0 0 0 0 0 0 0 1 1 f SA1 0 1 0 1 0 1 1 1 g SA0 0 1 0 0 0 1 0 0 g SA1 1 1 1 1 1 1 1 1 h SA0 0 0 0 0 0 0 1 1 h SA1 1 1 1 1 1 1 1 1 i SA0 0 0 0 0 0 0 0 0 i SA1 1 1 1 1 1 1 1 1 Valid test vectors Faulty circuit differs from good circuit Necessary vectors: 011 detects f SA1, e SA0 100 detects d SA1 – Detect total of 10 faults – 001 and 110 detect remaining 8 faults Truth table for fault-free behavior and behavior of all possible stuck-at faults
- 22. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 22 22 Stuck-at Faults x1 x2 x3 y a b c d e f g h i x1x2x3 000 001 010 011 100 101 110 111 y 0 1 0 0 0 1 1 1 a SA0 0 1 0 0 0 1 0 0 a SA1 0 1 1 1 0 1 1 1 b SA0 0 1 0 1 0 1 0 1 b SA1 0 0 0 0 1 1 1 1 c SA0 0 0 0 0 0 0 1 1 c SA1 1 1 0 0 1 1 1 1 d SA0 0 1 0 0 0 1 0 0 d SA1 0 1 0 0 1 1 1 1 e SA0 0 1 0 1 0 1 1 1 e SA1 0 0 0 0 0 0 1 1 f SA0 0 0 0 0 0 0 1 1 f SA1 0 1 0 1 0 1 1 1 g SA0 0 1 0 0 0 1 0 0 g SA1 1 1 1 1 1 1 1 1 h SA0 0 0 0 0 0 0 1 1 h SA1 1 1 1 1 1 1 1 1 i SA0 0 0 0 0 0 0 0 0 i SA1 1 1 1 1 1 1 1 1 4 sets of equivalent faults # collapsed faults = 2×(PO+FO)+GI-NI PO= # primary outputs FO= # fanout stems GI= # gate inputs NI= # inverters Truth table for fault-free behavior and behavior of all possible stuck-at faults
- 23. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 23 23 Stuck-at Faults # collapsed faults = 2×(PO+FO)+GI-NI PO= number of primary outputs FO= number of fanout stems GI= total number of gate inputs for all gates including inverters NI= total number of inverters For example circuit, # collapsed faults = 10 PO= 1, FO= 1, GI= 7, and NI= 1 Fault collapsing typically reduces number of stuck-at faults by 50% - 60%
- 24. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 24 24 AB 00 01 10 11 Z 1 0 0 0 N1 stuck-open 1 0 last Z 0 N1 stuck-short IDDQ 0 0 0 N2 stuck-open 1 last Z 0 0 N2 stuck-short IDDQ 0 0 0 P1 stuck-open last Z 0 0 0 P1 stuck-short 1 0 IDDQ 0 P2 stuck-open last Z 0 0 0 P2 stuck-short 1 IDDQ 0 0 VDD VSS B P1 P2 N2 N1 A Z Transistor Faults Any transistor can be Stuck-short – Also known as stuck-short Stuck-open – Also known as stuck-open # fault types: k=2 Example circuit # fault sites: n=4 # single faults =2×4=8 2-input CMOS NOR gate Truth table for fault-free circuit and all possible transistor faults
- 25. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 25 25 AB 00 01 10 11 Z 1 0 0 0 N1 stuck-open 1 0 last Z 0 N1 stuck-short IDDQ 0 0 0 N2 stuck-open 1 last Z 0 0 N2 stuck-short IDDQ 0 0 0 P1 stuck-open last Z 0 0 0 P1 stuck-short 1 0 IDDQ 0 P2 stuck-open last Z 0 0 0 P2 stuck-short 1 IDDQ 0 0 VDD VSS B P1 P2 N2 N1 A Z Transistor Faults Stuck-short faults cause conducting path from VDD to VSS Can be detect by monitoring steady-state power supply current IDDQ Stuck-open faults cause output node to store last voltage level Requires sequence of 2 vectors for detection – 0010 detects N1 stuck-open 2-input CMOS NOR gate Truth table for fault-free circuit and all possible transistor faults
- 26. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 26 26 Transistor Faults # collapsed faults = 2×T -TS+GS -TP+GP T = number of transistors TS= number of series transistors GS= number of groups of series transistors TP= number of parallel transistors GP= number of groups of parallel transistors For example circuit, # collapsed faults = 6 T=4, TS= 2, GS= 1, TP= 2, & GP= 1 Fault collapsing typically reduces number of transistor faults by 25% to 35%
- 27. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 27 27 Shorts and Opens Wires can be Open – Opens in wires interconnecting transistors to form gates behave like transistor stuck-open faults – Opens in wires interconnecting gates to form circuit behave like stuck-at faults – Opens are detected by vectors detecting transistor and stuck-at faults Short to an adjacent wire – Also known as a bridging fault
- 28. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 28 28 AS BS 0 0 0 1 1 0 1 1 AD BD 0 0 0 1 1 0 1 1 Wired-AND 0 0 0 0 0 0 1 1 Wired-OR 0 0 1 1 1 1 1 1 A dominates B 0 0 0 0 1 1 1 1 B dominates A 0 0 1 1 0 0 1 1 A dominant-AND B 0 0 0 0 1 0 1 1 B dominant-AND A 0 0 0 1 0 0 1 1 A dominant-OR B 0 0 0 1 1 1 1 1 B dominant-OR A 0 0 1 1 1 0 1 1 Bridging Faults Three different models Wired-AND/OR Dominant Dominant-AND/OR Detectable by IDDQ testing AS BS AD BD source bridging fault destination AS BS AD BD Wired-AND AS BS AD BD Wired-OR AS BS AD BD A dominates B AS BS AD BD B dominates A A dominant-AND B AS BS AD BD A dominant-OR B AS BS AD BD B dominant-AND A AS BS AD BD B dominant-OR A AS BS AD BD
- 29. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 29 29 Delay Faults and Crosstalk Path-delay fault model considers cumulative propagation delay through CUT 2 test vectors create transition along path Faulty circuit has excessive delay Delays and glitches can be caused by crosstalk between interconnect due to inductance and capacitive coupling 0 0 x1 0 1 x2 v2 v1 1 1 x3 y 2 3 3 2 t=0 t=2 t=7
- 30. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 30 30 Pattern Sensitivity and Coupling Faults Common in high density RAMs Pattern sensitivity fault Contents of memory cell is affected by contents of neighboring cells Coupling fault Transition in contents of one memory cell causes change in contents of another cell
- 31. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 31 31 Test Algorithm March Test Sequence March LR w/o BDS ↨(w0); ↓(r0, w1); ↑(r1, w0, r0, r0, w1); ↑(r1, w0); ↑(r0, w1, r1, r1, w0); ↑(r0) March LR with BDS ↨(w00); ↓(r00, w11); ↑(r11, w00, r00, r00, w11); ↑(r11, w00); ↑(r00, w11, r11, r11, w00); ↑(r00, w01, w10, r10); ↑(r10, w01, r01); ↑(r01) Pattern Sensitivity and Coupling Faults Common in memory cells of high density RAMs Pattern sensitivity fault Contents of cell affected by contents of neighboring cells Coupling fault Transition in one cell causes change in another cell Detected with specific memory test algorithms Background Data Sequence (BDS) used for word- oriented memories Notation: w0 = write 0 (or all 0’s) r1 = read 1 (or all 1’s) ↑= address up ↓= address down ↨ = address either way
- 32. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 32 32 Analog Fault Models Catastrophic faults Shorts and opens Parametric faults Parametric variations in passive and active components cause components to be out of tolerance range Active components can sustain defects that affect DC and/or AC operation
- 33. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 33 33 Levels of Abstraction High levels have few implementation details needed for effective test generation Fault models based on gate & physical levels Example: two circuits for same specification Ckt B test vectors do not detect 4 faults in Ckt A f(a,b,c)=m(1,7)+d(3) = abc + abc + Xabc 0 0 0 1 1 1 1 0 0 1 1 X 1 ab c 0 0 0 1 1 1 1 0 0 1 1 X 1 ab c f = abc + abc f = ab + bc Test Vectors {111,110,101,011,010,000} Test Vectors {111,101,010,000} f SA1 b c a SA1 SA1 SA1 a b f c Circuit A Circuit B Circuit A Circuit B
- 34. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 34 34 Overview of VLSI Test Technology Automatic Test Equipment (ATE) consists of Computer – for central control and flexible test & measurement for different products Pin electronics & fixtures – to apply test patterns to pins & sample responses Test program – controls timing of test patterns & compares response to known good responses
- 35. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 35 35 Overview of VLSI Test Technology Automatic Test Pattern Generation (ATPG) Algorithms generating sequence of test vectors for a given circuit based on specific fault models Fault simulation Emulates fault models in CUT and applies test vectors to determine fault coverage Simulation time (significant due to large number of faults to emulate) can be reduced by – Parallel, deductive, and concurrent fault simulation
- 36. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 36 36 Overview of VLSI Test Technology Design for Testability (DFT) Generally incorporated in design Goal: improve controllability and/or observability of internal nodes of a chip or PCB Three basic approaches Ad-hoc techniques Scan design – Boundary Scan Built-In Self-Test (BIST)
- 37. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 37 37 Design of Testability Ad-hoc DFT techniques Add internal test points (usually multiplexers) for – Controllability – Observability Added on a case-by-case basis – Primarily targets “hard to test” portions of chip Internal node to be controlled Normal system data Test data input Test mode select 0 1 controllability test point observability test point Primary output Normal system data Internal node to be observed Test mode select 0 1
- 38. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 38 38 Design for Testability Scan design Transforms flip-flops of chip into a shift register Scan mode facilitates – Shifting in test vectors – Shifting out responses Good CAD tool support Transforming flip-flops to shift register ATPG FFs Combinational Logic Primary Inputs Primary Outputs FF Di Clk Qi FFs Combinational Logic Primary Inputs Primary Outputs Scan Data In Scan Data Out FF Clk Qi Di Qi-1 Scan Mode 0 1 1 2 3
- 39. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 39 39 TAP pin I/O Function TCK input Test clock TMS input Test Mode Select TDI input Test Data In TDO output Test Data Out Design for Testability Boundary Scan – scan design applied to I/O buffers of chip Used for testing interconnect on PCB – Provides access to internal DFT capabilities IEEE standard 4-wire Test Access Port (TAP) input data to IC capture FF Capture update FF Update Input Scan In Shift Scan Out Output Input BS Cell Control BS Cell Pad tri-state control from IC Output BS Cell 0 1 0 1
- 40. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 40 40 Design for Testability Built-In Self-Test (BIST) Incorporates test pattern generator (TPG) and output response analyzer (ORA) internal to design – Chip can test itself Can be used at all levels of testing – Device PCB system field operation TPG Circuit Under Test Primary Inputs Primary Outputs BIST Mode ORA Pass Fail 0 1
- 41. EE141 VLSI Test Principles and Architectures Ch. 1 - Introduction - P. 41 41 Concluding Remarks Many new testing challenges presented by Increasing size and complexity of VLSI devices Decreasing feature size This chapter presented introduction to VLSI testing Remaining chapters present more details as well as solutions to these challenges
Editor's Notes
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