SlideShare a Scribd company logo
Digital IC studied in second Year
Control
Unit
Arithmetic
Logic Unit
Microcompyter
Memory Mapping Circuit
𝐴15
𝐴8
𝐴𝐿𝐸
𝐴𝐷7
𝐴𝐷0
𝑊𝑅
𝑅𝐷
𝐼𝑂/𝑀
𝐸𝑁
𝑳𝑨𝑻𝑪𝑯
𝐴8 − 𝐴15
𝐴0 − 𝐴6
𝐴7
𝐷0− 𝐷7
𝑅 𝐷
𝑊 𝑅
𝐂𝐡𝐢𝐩𝐒𝐞𝐥𝐞𝐜𝐭𝐂𝐢𝐫𝐜𝐮𝐢𝐭
𝐶𝑆 2
𝐶𝑆1
𝐷0− 𝐷7
𝐴0 − 𝐴6
Microprocessor
or
Microcontroller
SRAM 128
X 8
=1024Bit
Memory mapping
1Kb=1024bits
No of lines =
1024/8=128 lines
1Kbit Memory
1Kbits = m X n
= 128 X 8
data lines
D0
D1
D2
D3
D4
D5
D6
D7
1Kbit Memory
W0
W127
}n data lines
W0 is first line address and
W127 is last line address
But do the microprocessor
has 128 address lines?
NO. 8085 Microprocessor
has 16 address lines A0-A15
in which A0 – A6 can be
used to select 128 address
lines because 27
=128
A0
A1
A2
A3
A4
A5
A6
A7
What is the use of and ?
are chip select signal to select the chip. When =1 and =0, this chip will get selected and the data
can be either read from or write into it by sending the proper signal to this SRAM chip.
How to generate Chip Select Signal?
If Microprocessor has address lines AD0 - AD15. AD0 – AD6 are used to select the address of
memory locations of SRAM chip and AD7 – AD15 are used to generate the Chip Select signal.
What is the use of RD and WR signal?
Since it is SRAM, the data can be read from and write into it by using
memory read and memory write signal of microprocessor.
Memory Read and Memory Write signal
generator
Memory Mapping
𝐴15
𝐴8
𝐴𝐿𝐸
𝐴𝐷7
𝐴𝐷0
𝑊𝑅
𝑅𝐷
𝐼𝑂/𝑀
𝐸𝑁
𝑳𝑨𝑻𝑪𝑯
𝐴8 − 𝐴15
𝐴0 − 𝐴6
𝐴7
𝐷0− 𝐷7
𝑅 𝐷
𝑊 𝑅
𝐂𝐡𝐢𝐩𝐒𝐞𝐥𝐞𝐜𝐭𝐂𝐢𝐫𝐜𝐮𝐢𝐭
𝐶𝑆 2
𝐶𝑆1
𝐷0− 𝐷7
𝐴0 − 𝐴6
Microprocessor
or
Microcontroller
SRAM 128
X 8
=1024Bit
Power on RESET
• Highest Priority
Interrupt
• It should be high
for 2 clock cycles
• After reset, 8051
starts at 0x0000H
RESET
Program Counter
• A register in a computer processor that contains the address (location) of
the instruction being executed at the current time.
• As each instruction gets fetched, the program counter increases its stored
value by 1.
• After each instruction is fetched, the program counter points to the next
instruction in the sequence.
• When the computer restarts or is reset, the program counter normally
reverts to 0.
Stack and Stack Pointer
• The stack is a LIFO (last in, first out) data structure implemented in
the RAM area.
• Used to store addresses and data when the microprocessor branches to a
subroutine.
• Then the return address used to get pushed on this stack.
• Also to swap values of two registers and register pairs we use the stack as
well.
• Two operations are performed on a stack .
• PUSH : The SP register gets decreased by 2 and new data item used to insert
on to the top of the stack.
POP : the data item will have to be deleted
from the top of the stack and the SP register
will get increased by the value of 2.
The contents of SP specify the top most
useful location in the stack.
Subroutine
• When the same function is required more than once
in a program, it is frequently written as a subroutine,
that is, a subprogram that can be used any number of
times by the main program.
• Subroutines are a powerful programming construct
that allow a program to break down a complex task
into smaller, more manageable pieces.
• A subroutine is a block of code that can be called from
anywhere in the program, and then returns control
back to the calling code when it is done.
Microcomputer System
Harvard Architecture
1. Separate Storage for Instruction and data.
2. Separate buses are used to fetch
instructions and data.
3. the CPU can fetch instruction and
read/write data simultaneously.
4. It is basically developed to overcome the
bottleneck of Von Neumann’s Architecture.
1. Instructions, and data both are
stored in the same memory.
2. Same buses are used to fetch
instructions and data.
3. The CPU cannot fetch instruction
and data simultaneously.
Von Neumann Architecture
Main Memory System
Central Processing Unit
Operational
Registers
Program
Counter
Arithmetic
and Logic
Unit
Control Unit
Input/Output System
Data
Instruction
Data Address
Instruction
Address
RISC : Reduced Instruction Set Architecture
1. Simpler instruction, hence
simple instruction
decoding.
2. Instruction comes
undersize of one word.
3. Instruction takes a single
clock cycle to get executed.
4. More general-purpose
registers.
5. Simple Addressing Modes.
6. Fewer Data types.
CISC : Complex Instruction Set Architecture
1. Complex instruction, hence
complex instruction decoding.
2. Instructions are larger than
one-word size.
3. Instruction may take more
than a single clock cycle to get
executed.
4. Less number of general-
purpose registers as
operations get performed in
memory itself.
5. Complex Addressing Modes.
6. More Data types.
RISC : Reduced Instruction Set
Architecture
Advantages
• Simpler instructions: RISC
processors use a smaller set of
simple instructions, which makes
them easier to decode and
execute quickly. This results in
faster processing times.
• Faster execution: Because RISC
processors have a simpler
instruction set, they can execute
instructions faster than CISC
processors.
• Lower power consumption: RISC
processors consume less power
than CISC processors, making
them ideal for portable devices.
CISC : Complex Instruction Set
Architecture
Advantages
• Reduced code size: CISC processors
use complex instructions that can
perform multiple operations,
reducing the amount of code
needed to perform a task.
• More memory efficient: Because
CISC instructions are more
complex, they require fewer
instructions to perform complex
tasks, which can result in more
memory-efficient code.
• Widely used: CISC processors have
been in use for a longer time than
RISC processors, so they have a
larger user base and more available
software.
RISC : Reduced Instruction Set
Architecture
Disadvantages
• More instructions
required: RISC processors
require more instructions to
perform complex tasks than
CISC processors.
• Increased memory usage: RISC
processors require more
memory to store the additional
instructions needed to
perform complex tasks.
• Higher cost: Developing and
manufacturing RISC processors
can be more expensive than
CISC processors.
CISC : Complex Instruction Set
Architecture
Disadvantages
• Slower execution: CISC
processors take longer to execute
instructions because they have
more complex instructions and
need more time to decode them.
• More complex design: CISC
processors have more complex
instruction sets, which makes
them more difficult to design and
manufacture.
• Higher power consumption: CISC
processors consume more power
than RISC processors because of
their more complex instruction
sets.
Primary Memory
• The primary memory of a
computer is the main memory
that is utilized to store data
temporarily.
• Primary memory is temporary.
• Primary memory is faster than
secondary memory because it
is directly accessible to the
CPU.
• Primary memory is directly
accessible by Processor/CPU.
• Nature of Parts of Primary
memory varies, RAM- volatile
in nature. ROM- Non-volatile.
Secondary memory
• Secondary memory defines to
additional storage devices that
are utilized to store data
permanently.
• Secondary memory is
permanent.
• Secondary memory is non-
volatile, which means it retains
data even when the power is
off.
• Secondary memory is not
directly accessible by the CPU.
• It’s always Non-volatile in
nature.
Primary Memory
• Primary memory devices
are more expensive than
secondary storage devices
• The memory devices used
for primary memory are
semiconductor memories.
• It can hold data/information
currently being used by the
processing unit.
• The capacity of primary
memory is usually within
the range of 16 to 32 GB.
Secondary memory
• Secondary memory devices are
less expensive when compared
to primary memory devices.
• The secondary memory
devices are magnetic and
optical memories.
• It can hold data/information
that are not currently being
used by the processing unit.
• It stores a considerable
amount of data and
information. The capacity of
secondary memory ranges
from 200 GB to some terabytes
Primary Memory
• Primary memory is also
known as Main memory or
Internal memory.
• It can be accessed by a data
bus.
• Examples: RAM, ROM,
Cache memory, PROM,
EPROM, Registers, etc.
Secondary memory
• Secondary memory is also
known as External memory
or Auxiliary memory.
• It can be accessed using I/O
channels.
• Examples: Hard Disk,
Floppy Disk, Magnetic Tapes
, etc
Cache Memory
• The most important use of cache memory is
that it is used to reduce the average time to
access data from the main memory.
• The concept of cache works because there
exists locality of reference (the same items or
nearby items are more likely to be accessed
next) in processes.
Characteristics of Cache Memory
• Extremely fast memory type that acts as a buffer
between RAM and the CPU.
• Holds frequently requested data and instructions,
ensuring that they are immediately available to
the CPU when needed.
• Costlier than main memory or disk memory but
more economical than CPU registers.
• Used to speed up processing and synchronize
with the high-speed CPU.
Cache Performance
• If the processor finds that the memory location
is in the cache, a Cache Hit has occurred and
data is read from the cache.
• If the processor does not find the memory
location in the cache, a cache miss has
occurred. For a cache miss, the cache allocates
a new entry and copies in data from the main
memory, then the request is fulfilled from the
contents of the cache.
Virtual memory with Memory Management
• Virtual memory is a memory management
technique used by operating systems to give
the appearance of a large, continuous block of
memory to applications, even if the physical
memory (RAM) is limited. It allows larger
applications to run on systems with less RAM.
Virtual memory with Memory Management
• The main objective of virtual memory is to support
multiprogramming, The main advantage that virtual
memory provides is, a running process does not need to
be entirely in memory.
• Programs can be larger than the available physical
memory. Virtual Memory provides an abstraction of main
memory, eliminating concerns about storage limitations.
• A memory hierarchy, consisting of a computer system’s
memory and a disk, enables a process to operate with only
some portions of its address space in RAM to allow more
processes to be in memory.
Types of virtual memory
• Paging
– Paging divides memory into small fixed-size blocks called pages. When
the computer runs out of RAM, pages that aren’t currently in use are
moved to the hard drive, into an area called a swap file. The swap file
acts as an extension of RAM. When a page is needed again, it is swapped
back into RAM, a process known as page swapping. This ensures that the
operating system (OS) and applications have enough memory to
• Segmentation
– Segmentation divides virtual memory into segments of different sizes.
Segments that aren’t currently needed can be moved to the hard drive.
The system uses a segment table to keep track of each segment’s status,
including whether it’s in memory, if it’s been modified, and its physical
address. Segments are mapped into a process’s address space only when
needed.run.
Feature Virtual Memory Physical Memory (RAM)
Definition
An abstraction that extends the
available memory by using disk
storage
The actual hardware (RAM) that stores
data and instructions currently being
used by the CPU
Location On the hard drive or SSD On the computer’s motherboard
Speed Slower (due to disk I/O operations) Faster (accessed directly by the CPU)
Capacity Larger, limited by disk space
Smaller, limited by the amount of RAM
installed
Cost
Lower (cost of additional disk
storage)
Higher (cost of RAM modules)
Data Access Indirect (via paging and swapping) Direct (CPU can access data directly)
Volatility Non-volatile (data persists on disk) Volatile (data is lost when power is off)
Ad

More Related Content

Similar to 1 microcontroller 8051 detailed explanation (20)

Microprocessor System qwefqwgqwgqwgqwgqegew
Microprocessor System qwefqwgqwgqwgqwgqegewMicroprocessor System qwefqwgqwgqwgqwgqegew
Microprocessor System qwefqwgqwgqwgqwgqegew
ObbiHandira
 
Group 3
Group 3Group 3
Group 3
agarland
 
Computers for Scenarios
Computers for ScenariosComputers for Scenarios
Computers for Scenarios
AnnaBradford
 
introduction to embedded-converted new one
introduction to embedded-converted new oneintroduction to embedded-converted new one
introduction to embedded-converted new one
DrVikasMahor
 
Basics of micro controllers for biginners
Basics of  micro controllers for biginnersBasics of  micro controllers for biginners
Basics of micro controllers for biginners
Gerwin Makanyanga
 
Module-3 ADVANCED MICROCONTROLLER IMP.pptx
Module-3 ADVANCED MICROCONTROLLER IMP.pptxModule-3 ADVANCED MICROCONTROLLER IMP.pptx
Module-3 ADVANCED MICROCONTROLLER IMP.pptx
RiniBhandari
 
Computer Architecture | Computer Fundamental and Organization
Computer Architecture | Computer Fundamental and OrganizationComputer Architecture | Computer Fundamental and Organization
Computer Architecture | Computer Fundamental and Organization
Smit Luvani
 
Microprocessor
MicroprocessorMicroprocessor
Microprocessor
Embeddedbvp
 
Ch04-new.pptx
Ch04-new.pptxCh04-new.pptx
Ch04-new.pptx
EnghamzaKhalailah
 
Mces MOD 1.pptx
Mces MOD 1.pptxMces MOD 1.pptx
Mces MOD 1.pptx
RadhaC10
 
Basic Computer Architecture
Basic Computer ArchitectureBasic Computer Architecture
Basic Computer Architecture
Yong Heui Cho
 
Exploring Of System Hardware
Exploring Of System HardwareExploring Of System Hardware
Exploring Of System Hardware
Muhammad Nauman
 
12429908.ppt
12429908.ppt12429908.ppt
12429908.ppt
ssuser4ca1eb
 
INFORMATION TECHNOLOGY HARDWARE LESSON GRD 12.pptx
INFORMATION TECHNOLOGY HARDWARE LESSON GRD 12.pptxINFORMATION TECHNOLOGY HARDWARE LESSON GRD 12.pptx
INFORMATION TECHNOLOGY HARDWARE LESSON GRD 12.pptx
disoloaneglenda
 
Chap4.ppt
Chap4.pptChap4.ppt
Chap4.ppt
SaniyaSultana9
 
The Central Processing Unit(CPU) for Chapter 4
The Central Processing Unit(CPU) for Chapter 4The Central Processing Unit(CPU) for Chapter 4
The Central Processing Unit(CPU) for Chapter 4
MKKhaing
 
Chap4.ppt
Chap4.pptChap4.ppt
Chap4.ppt
mvpk14486
 
Chap4.ppt
Chap4.pptChap4.ppt
Chap4.ppt
Praches1
 
Cao u1
Cao u1Cao u1
Cao u1
vishnu murthy
 
Module-01 8051 Microcontroller for engineering
Module-01 8051 Microcontroller for engineeringModule-01 8051 Microcontroller for engineering
Module-01 8051 Microcontroller for engineering
KiranG764628
 
Microprocessor System qwefqwgqwgqwgqwgqegew
Microprocessor System qwefqwgqwgqwgqwgqegewMicroprocessor System qwefqwgqwgqwgqwgqegew
Microprocessor System qwefqwgqwgqwgqwgqegew
ObbiHandira
 
Computers for Scenarios
Computers for ScenariosComputers for Scenarios
Computers for Scenarios
AnnaBradford
 
introduction to embedded-converted new one
introduction to embedded-converted new oneintroduction to embedded-converted new one
introduction to embedded-converted new one
DrVikasMahor
 
Basics of micro controllers for biginners
Basics of  micro controllers for biginnersBasics of  micro controllers for biginners
Basics of micro controllers for biginners
Gerwin Makanyanga
 
Module-3 ADVANCED MICROCONTROLLER IMP.pptx
Module-3 ADVANCED MICROCONTROLLER IMP.pptxModule-3 ADVANCED MICROCONTROLLER IMP.pptx
Module-3 ADVANCED MICROCONTROLLER IMP.pptx
RiniBhandari
 
Computer Architecture | Computer Fundamental and Organization
Computer Architecture | Computer Fundamental and OrganizationComputer Architecture | Computer Fundamental and Organization
Computer Architecture | Computer Fundamental and Organization
Smit Luvani
 
Mces MOD 1.pptx
Mces MOD 1.pptxMces MOD 1.pptx
Mces MOD 1.pptx
RadhaC10
 
Basic Computer Architecture
Basic Computer ArchitectureBasic Computer Architecture
Basic Computer Architecture
Yong Heui Cho
 
Exploring Of System Hardware
Exploring Of System HardwareExploring Of System Hardware
Exploring Of System Hardware
Muhammad Nauman
 
INFORMATION TECHNOLOGY HARDWARE LESSON GRD 12.pptx
INFORMATION TECHNOLOGY HARDWARE LESSON GRD 12.pptxINFORMATION TECHNOLOGY HARDWARE LESSON GRD 12.pptx
INFORMATION TECHNOLOGY HARDWARE LESSON GRD 12.pptx
disoloaneglenda
 
The Central Processing Unit(CPU) for Chapter 4
The Central Processing Unit(CPU) for Chapter 4The Central Processing Unit(CPU) for Chapter 4
The Central Processing Unit(CPU) for Chapter 4
MKKhaing
 
Module-01 8051 Microcontroller for engineering
Module-01 8051 Microcontroller for engineeringModule-01 8051 Microcontroller for engineering
Module-01 8051 Microcontroller for engineering
KiranG764628
 

Recently uploaded (20)

Smart Storage Solutions.pptx for production engineering
Smart Storage Solutions.pptx for production engineeringSmart Storage Solutions.pptx for production engineering
Smart Storage Solutions.pptx for production engineering
rushikeshnavghare94
 
Level 1-Safety.pptx Presentation of Electrical Safety
Level 1-Safety.pptx Presentation of Electrical SafetyLevel 1-Safety.pptx Presentation of Electrical Safety
Level 1-Safety.pptx Presentation of Electrical Safety
JoseAlbertoCariasDel
 
QA/QC Manager (Quality management Expert)
QA/QC Manager (Quality management Expert)QA/QC Manager (Quality management Expert)
QA/QC Manager (Quality management Expert)
rccbatchplant
 
Reagent dosing (Bredel) presentation.pptx
Reagent dosing (Bredel) presentation.pptxReagent dosing (Bredel) presentation.pptx
Reagent dosing (Bredel) presentation.pptx
AlejandroOdio
 
some basics electrical and electronics knowledge
some basics electrical and electronics knowledgesome basics electrical and electronics knowledge
some basics electrical and electronics knowledge
nguyentrungdo88
 
Degree_of_Automation.pdf for Instrumentation and industrial specialist
Degree_of_Automation.pdf for  Instrumentation  and industrial specialistDegree_of_Automation.pdf for  Instrumentation  and industrial specialist
Degree_of_Automation.pdf for Instrumentation and industrial specialist
shreyabhosale19
 
Data Structures_Searching and Sorting.pptx
Data Structures_Searching and Sorting.pptxData Structures_Searching and Sorting.pptx
Data Structures_Searching and Sorting.pptx
RushaliDeshmukh2
 
International Journal of Distributed and Parallel systems (IJDPS)
International Journal of Distributed and Parallel systems (IJDPS)International Journal of Distributed and Parallel systems (IJDPS)
International Journal of Distributed and Parallel systems (IJDPS)
samueljackson3773
 
IntroSlides-April-BuildWithAI-VertexAI.pdf
IntroSlides-April-BuildWithAI-VertexAI.pdfIntroSlides-April-BuildWithAI-VertexAI.pdf
IntroSlides-April-BuildWithAI-VertexAI.pdf
Luiz Carneiro
 
Development of MLR, ANN and ANFIS Models for Estimation of PCUs at Different ...
Development of MLR, ANN and ANFIS Models for Estimation of PCUs at Different ...Development of MLR, ANN and ANFIS Models for Estimation of PCUs at Different ...
Development of MLR, ANN and ANFIS Models for Estimation of PCUs at Different ...
Journal of Soft Computing in Civil Engineering
 
Smart_Storage_Systems_Production_Engineering.pptx
Smart_Storage_Systems_Production_Engineering.pptxSmart_Storage_Systems_Production_Engineering.pptx
Smart_Storage_Systems_Production_Engineering.pptx
rushikeshnavghare94
 
Compiler Design Unit1 PPT Phases of Compiler.pptx
Compiler Design Unit1 PPT Phases of Compiler.pptxCompiler Design Unit1 PPT Phases of Compiler.pptx
Compiler Design Unit1 PPT Phases of Compiler.pptx
RushaliDeshmukh2
 
Value Stream Mapping Worskshops for Intelligent Continuous Security
Value Stream Mapping Worskshops for Intelligent Continuous SecurityValue Stream Mapping Worskshops for Intelligent Continuous Security
Value Stream Mapping Worskshops for Intelligent Continuous Security
Marc Hornbeek
 
Structural Response of Reinforced Self-Compacting Concrete Deep Beam Using Fi...
Structural Response of Reinforced Self-Compacting Concrete Deep Beam Using Fi...Structural Response of Reinforced Self-Compacting Concrete Deep Beam Using Fi...
Structural Response of Reinforced Self-Compacting Concrete Deep Beam Using Fi...
Journal of Soft Computing in Civil Engineering
 
Lidar for Autonomous Driving, LiDAR Mapping for Driverless Cars.pptx
Lidar for Autonomous Driving, LiDAR Mapping for Driverless Cars.pptxLidar for Autonomous Driving, LiDAR Mapping for Driverless Cars.pptx
Lidar for Autonomous Driving, LiDAR Mapping for Driverless Cars.pptx
RishavKumar530754
 
Mathematical foundation machine learning.pdf
Mathematical foundation machine learning.pdfMathematical foundation machine learning.pdf
Mathematical foundation machine learning.pdf
TalhaShahid49
 
AI-assisted Software Testing (3-hours tutorial)
AI-assisted Software Testing (3-hours tutorial)AI-assisted Software Testing (3-hours tutorial)
AI-assisted Software Testing (3-hours tutorial)
Vəhid Gəruslu
 
new ppt artificial intelligence historyyy
new ppt artificial intelligence historyyynew ppt artificial intelligence historyyy
new ppt artificial intelligence historyyy
PianoPianist
 
DATA-DRIVEN SHOULDER INVERSE KINEMATICS YoungBeom Kim1 , Byung-Ha Park1 , Kwa...
DATA-DRIVEN SHOULDER INVERSE KINEMATICS YoungBeom Kim1 , Byung-Ha Park1 , Kwa...DATA-DRIVEN SHOULDER INVERSE KINEMATICS YoungBeom Kim1 , Byung-Ha Park1 , Kwa...
DATA-DRIVEN SHOULDER INVERSE KINEMATICS YoungBeom Kim1 , Byung-Ha Park1 , Kwa...
charlesdick1345
 
Raish Khanji GTU 8th sem Internship Report.pdf
Raish Khanji GTU 8th sem Internship Report.pdfRaish Khanji GTU 8th sem Internship Report.pdf
Raish Khanji GTU 8th sem Internship Report.pdf
RaishKhanji
 
Smart Storage Solutions.pptx for production engineering
Smart Storage Solutions.pptx for production engineeringSmart Storage Solutions.pptx for production engineering
Smart Storage Solutions.pptx for production engineering
rushikeshnavghare94
 
Level 1-Safety.pptx Presentation of Electrical Safety
Level 1-Safety.pptx Presentation of Electrical SafetyLevel 1-Safety.pptx Presentation of Electrical Safety
Level 1-Safety.pptx Presentation of Electrical Safety
JoseAlbertoCariasDel
 
QA/QC Manager (Quality management Expert)
QA/QC Manager (Quality management Expert)QA/QC Manager (Quality management Expert)
QA/QC Manager (Quality management Expert)
rccbatchplant
 
Reagent dosing (Bredel) presentation.pptx
Reagent dosing (Bredel) presentation.pptxReagent dosing (Bredel) presentation.pptx
Reagent dosing (Bredel) presentation.pptx
AlejandroOdio
 
some basics electrical and electronics knowledge
some basics electrical and electronics knowledgesome basics electrical and electronics knowledge
some basics electrical and electronics knowledge
nguyentrungdo88
 
Degree_of_Automation.pdf for Instrumentation and industrial specialist
Degree_of_Automation.pdf for  Instrumentation  and industrial specialistDegree_of_Automation.pdf for  Instrumentation  and industrial specialist
Degree_of_Automation.pdf for Instrumentation and industrial specialist
shreyabhosale19
 
Data Structures_Searching and Sorting.pptx
Data Structures_Searching and Sorting.pptxData Structures_Searching and Sorting.pptx
Data Structures_Searching and Sorting.pptx
RushaliDeshmukh2
 
International Journal of Distributed and Parallel systems (IJDPS)
International Journal of Distributed and Parallel systems (IJDPS)International Journal of Distributed and Parallel systems (IJDPS)
International Journal of Distributed and Parallel systems (IJDPS)
samueljackson3773
 
IntroSlides-April-BuildWithAI-VertexAI.pdf
IntroSlides-April-BuildWithAI-VertexAI.pdfIntroSlides-April-BuildWithAI-VertexAI.pdf
IntroSlides-April-BuildWithAI-VertexAI.pdf
Luiz Carneiro
 
Smart_Storage_Systems_Production_Engineering.pptx
Smart_Storage_Systems_Production_Engineering.pptxSmart_Storage_Systems_Production_Engineering.pptx
Smart_Storage_Systems_Production_Engineering.pptx
rushikeshnavghare94
 
Compiler Design Unit1 PPT Phases of Compiler.pptx
Compiler Design Unit1 PPT Phases of Compiler.pptxCompiler Design Unit1 PPT Phases of Compiler.pptx
Compiler Design Unit1 PPT Phases of Compiler.pptx
RushaliDeshmukh2
 
Value Stream Mapping Worskshops for Intelligent Continuous Security
Value Stream Mapping Worskshops for Intelligent Continuous SecurityValue Stream Mapping Worskshops for Intelligent Continuous Security
Value Stream Mapping Worskshops for Intelligent Continuous Security
Marc Hornbeek
 
Lidar for Autonomous Driving, LiDAR Mapping for Driverless Cars.pptx
Lidar for Autonomous Driving, LiDAR Mapping for Driverless Cars.pptxLidar for Autonomous Driving, LiDAR Mapping for Driverless Cars.pptx
Lidar for Autonomous Driving, LiDAR Mapping for Driverless Cars.pptx
RishavKumar530754
 
Mathematical foundation machine learning.pdf
Mathematical foundation machine learning.pdfMathematical foundation machine learning.pdf
Mathematical foundation machine learning.pdf
TalhaShahid49
 
AI-assisted Software Testing (3-hours tutorial)
AI-assisted Software Testing (3-hours tutorial)AI-assisted Software Testing (3-hours tutorial)
AI-assisted Software Testing (3-hours tutorial)
Vəhid Gəruslu
 
new ppt artificial intelligence historyyy
new ppt artificial intelligence historyyynew ppt artificial intelligence historyyy
new ppt artificial intelligence historyyy
PianoPianist
 
DATA-DRIVEN SHOULDER INVERSE KINEMATICS YoungBeom Kim1 , Byung-Ha Park1 , Kwa...
DATA-DRIVEN SHOULDER INVERSE KINEMATICS YoungBeom Kim1 , Byung-Ha Park1 , Kwa...DATA-DRIVEN SHOULDER INVERSE KINEMATICS YoungBeom Kim1 , Byung-Ha Park1 , Kwa...
DATA-DRIVEN SHOULDER INVERSE KINEMATICS YoungBeom Kim1 , Byung-Ha Park1 , Kwa...
charlesdick1345
 
Raish Khanji GTU 8th sem Internship Report.pdf
Raish Khanji GTU 8th sem Internship Report.pdfRaish Khanji GTU 8th sem Internship Report.pdf
Raish Khanji GTU 8th sem Internship Report.pdf
RaishKhanji
 
Ad

1 microcontroller 8051 detailed explanation

  • 1. Digital IC studied in second Year
  • 3. Memory Mapping Circuit 𝐴15 𝐴8 𝐴𝐿𝐸 𝐴𝐷7 𝐴𝐷0 𝑊𝑅 𝑅𝐷 𝐼𝑂/𝑀 𝐸𝑁 𝑳𝑨𝑻𝑪𝑯 𝐴8 − 𝐴15 𝐴0 − 𝐴6 𝐴7 𝐷0− 𝐷7 𝑅 𝐷 𝑊 𝑅 𝐂𝐡𝐢𝐩𝐒𝐞𝐥𝐞𝐜𝐭𝐂𝐢𝐫𝐜𝐮𝐢𝐭 𝐶𝑆 2 𝐶𝑆1 𝐷0− 𝐷7 𝐴0 − 𝐴6 Microprocessor or Microcontroller SRAM 128 X 8 =1024Bit
  • 4. Memory mapping 1Kb=1024bits No of lines = 1024/8=128 lines 1Kbit Memory 1Kbits = m X n = 128 X 8 data lines D0 D1 D2 D3 D4 D5 D6 D7 1Kbit Memory W0 W127 }n data lines W0 is first line address and W127 is last line address But do the microprocessor has 128 address lines? NO. 8085 Microprocessor has 16 address lines A0-A15 in which A0 – A6 can be used to select 128 address lines because 27 =128 A0 A1 A2 A3 A4 A5 A6 A7
  • 5. What is the use of and ? are chip select signal to select the chip. When =1 and =0, this chip will get selected and the data can be either read from or write into it by sending the proper signal to this SRAM chip. How to generate Chip Select Signal? If Microprocessor has address lines AD0 - AD15. AD0 – AD6 are used to select the address of memory locations of SRAM chip and AD7 – AD15 are used to generate the Chip Select signal.
  • 6. What is the use of RD and WR signal? Since it is SRAM, the data can be read from and write into it by using memory read and memory write signal of microprocessor.
  • 7. Memory Read and Memory Write signal generator
  • 8. Memory Mapping 𝐴15 𝐴8 𝐴𝐿𝐸 𝐴𝐷7 𝐴𝐷0 𝑊𝑅 𝑅𝐷 𝐼𝑂/𝑀 𝐸𝑁 𝑳𝑨𝑻𝑪𝑯 𝐴8 − 𝐴15 𝐴0 − 𝐴6 𝐴7 𝐷0− 𝐷7 𝑅 𝐷 𝑊 𝑅 𝐂𝐡𝐢𝐩𝐒𝐞𝐥𝐞𝐜𝐭𝐂𝐢𝐫𝐜𝐮𝐢𝐭 𝐶𝑆 2 𝐶𝑆1 𝐷0− 𝐷7 𝐴0 − 𝐴6 Microprocessor or Microcontroller SRAM 128 X 8 =1024Bit
  • 9. Power on RESET • Highest Priority Interrupt • It should be high for 2 clock cycles • After reset, 8051 starts at 0x0000H RESET
  • 10. Program Counter • A register in a computer processor that contains the address (location) of the instruction being executed at the current time. • As each instruction gets fetched, the program counter increases its stored value by 1. • After each instruction is fetched, the program counter points to the next instruction in the sequence. • When the computer restarts or is reset, the program counter normally reverts to 0.
  • 11. Stack and Stack Pointer • The stack is a LIFO (last in, first out) data structure implemented in the RAM area. • Used to store addresses and data when the microprocessor branches to a subroutine. • Then the return address used to get pushed on this stack. • Also to swap values of two registers and register pairs we use the stack as well. • Two operations are performed on a stack . • PUSH : The SP register gets decreased by 2 and new data item used to insert on to the top of the stack. POP : the data item will have to be deleted from the top of the stack and the SP register will get increased by the value of 2. The contents of SP specify the top most useful location in the stack.
  • 12. Subroutine • When the same function is required more than once in a program, it is frequently written as a subroutine, that is, a subprogram that can be used any number of times by the main program. • Subroutines are a powerful programming construct that allow a program to break down a complex task into smaller, more manageable pieces. • A subroutine is a block of code that can be called from anywhere in the program, and then returns control back to the calling code when it is done.
  • 14. Harvard Architecture 1. Separate Storage for Instruction and data. 2. Separate buses are used to fetch instructions and data. 3. the CPU can fetch instruction and read/write data simultaneously. 4. It is basically developed to overcome the bottleneck of Von Neumann’s Architecture. 1. Instructions, and data both are stored in the same memory. 2. Same buses are used to fetch instructions and data. 3. The CPU cannot fetch instruction and data simultaneously. Von Neumann Architecture Main Memory System Central Processing Unit Operational Registers Program Counter Arithmetic and Logic Unit Control Unit Input/Output System Data Instruction Data Address Instruction Address
  • 15. RISC : Reduced Instruction Set Architecture 1. Simpler instruction, hence simple instruction decoding. 2. Instruction comes undersize of one word. 3. Instruction takes a single clock cycle to get executed. 4. More general-purpose registers. 5. Simple Addressing Modes. 6. Fewer Data types. CISC : Complex Instruction Set Architecture 1. Complex instruction, hence complex instruction decoding. 2. Instructions are larger than one-word size. 3. Instruction may take more than a single clock cycle to get executed. 4. Less number of general- purpose registers as operations get performed in memory itself. 5. Complex Addressing Modes. 6. More Data types.
  • 16. RISC : Reduced Instruction Set Architecture Advantages • Simpler instructions: RISC processors use a smaller set of simple instructions, which makes them easier to decode and execute quickly. This results in faster processing times. • Faster execution: Because RISC processors have a simpler instruction set, they can execute instructions faster than CISC processors. • Lower power consumption: RISC processors consume less power than CISC processors, making them ideal for portable devices. CISC : Complex Instruction Set Architecture Advantages • Reduced code size: CISC processors use complex instructions that can perform multiple operations, reducing the amount of code needed to perform a task. • More memory efficient: Because CISC instructions are more complex, they require fewer instructions to perform complex tasks, which can result in more memory-efficient code. • Widely used: CISC processors have been in use for a longer time than RISC processors, so they have a larger user base and more available software.
  • 17. RISC : Reduced Instruction Set Architecture Disadvantages • More instructions required: RISC processors require more instructions to perform complex tasks than CISC processors. • Increased memory usage: RISC processors require more memory to store the additional instructions needed to perform complex tasks. • Higher cost: Developing and manufacturing RISC processors can be more expensive than CISC processors. CISC : Complex Instruction Set Architecture Disadvantages • Slower execution: CISC processors take longer to execute instructions because they have more complex instructions and need more time to decode them. • More complex design: CISC processors have more complex instruction sets, which makes them more difficult to design and manufacture. • Higher power consumption: CISC processors consume more power than RISC processors because of their more complex instruction sets.
  • 18. Primary Memory • The primary memory of a computer is the main memory that is utilized to store data temporarily. • Primary memory is temporary. • Primary memory is faster than secondary memory because it is directly accessible to the CPU. • Primary memory is directly accessible by Processor/CPU. • Nature of Parts of Primary memory varies, RAM- volatile in nature. ROM- Non-volatile. Secondary memory • Secondary memory defines to additional storage devices that are utilized to store data permanently. • Secondary memory is permanent. • Secondary memory is non- volatile, which means it retains data even when the power is off. • Secondary memory is not directly accessible by the CPU. • It’s always Non-volatile in nature.
  • 19. Primary Memory • Primary memory devices are more expensive than secondary storage devices • The memory devices used for primary memory are semiconductor memories. • It can hold data/information currently being used by the processing unit. • The capacity of primary memory is usually within the range of 16 to 32 GB. Secondary memory • Secondary memory devices are less expensive when compared to primary memory devices. • The secondary memory devices are magnetic and optical memories. • It can hold data/information that are not currently being used by the processing unit. • It stores a considerable amount of data and information. The capacity of secondary memory ranges from 200 GB to some terabytes
  • 20. Primary Memory • Primary memory is also known as Main memory or Internal memory. • It can be accessed by a data bus. • Examples: RAM, ROM, Cache memory, PROM, EPROM, Registers, etc. Secondary memory • Secondary memory is also known as External memory or Auxiliary memory. • It can be accessed using I/O channels. • Examples: Hard Disk, Floppy Disk, Magnetic Tapes , etc
  • 21. Cache Memory • The most important use of cache memory is that it is used to reduce the average time to access data from the main memory. • The concept of cache works because there exists locality of reference (the same items or nearby items are more likely to be accessed next) in processes.
  • 22. Characteristics of Cache Memory • Extremely fast memory type that acts as a buffer between RAM and the CPU. • Holds frequently requested data and instructions, ensuring that they are immediately available to the CPU when needed. • Costlier than main memory or disk memory but more economical than CPU registers. • Used to speed up processing and synchronize with the high-speed CPU.
  • 23. Cache Performance • If the processor finds that the memory location is in the cache, a Cache Hit has occurred and data is read from the cache. • If the processor does not find the memory location in the cache, a cache miss has occurred. For a cache miss, the cache allocates a new entry and copies in data from the main memory, then the request is fulfilled from the contents of the cache.
  • 24. Virtual memory with Memory Management • Virtual memory is a memory management technique used by operating systems to give the appearance of a large, continuous block of memory to applications, even if the physical memory (RAM) is limited. It allows larger applications to run on systems with less RAM.
  • 25. Virtual memory with Memory Management • The main objective of virtual memory is to support multiprogramming, The main advantage that virtual memory provides is, a running process does not need to be entirely in memory. • Programs can be larger than the available physical memory. Virtual Memory provides an abstraction of main memory, eliminating concerns about storage limitations. • A memory hierarchy, consisting of a computer system’s memory and a disk, enables a process to operate with only some portions of its address space in RAM to allow more processes to be in memory.
  • 26. Types of virtual memory • Paging – Paging divides memory into small fixed-size blocks called pages. When the computer runs out of RAM, pages that aren’t currently in use are moved to the hard drive, into an area called a swap file. The swap file acts as an extension of RAM. When a page is needed again, it is swapped back into RAM, a process known as page swapping. This ensures that the operating system (OS) and applications have enough memory to • Segmentation – Segmentation divides virtual memory into segments of different sizes. Segments that aren’t currently needed can be moved to the hard drive. The system uses a segment table to keep track of each segment’s status, including whether it’s in memory, if it’s been modified, and its physical address. Segments are mapped into a process’s address space only when needed.run.
  • 27. Feature Virtual Memory Physical Memory (RAM) Definition An abstraction that extends the available memory by using disk storage The actual hardware (RAM) that stores data and instructions currently being used by the CPU Location On the hard drive or SSD On the computer’s motherboard Speed Slower (due to disk I/O operations) Faster (accessed directly by the CPU) Capacity Larger, limited by disk space Smaller, limited by the amount of RAM installed Cost Lower (cost of additional disk storage) Higher (cost of RAM modules) Data Access Indirect (via paging and swapping) Direct (CPU can access data directly) Volatility Non-volatile (data persists on disk) Volatile (data is lost when power is off)