180 nm Tape out experience using Open POWER ISA
- 1. Libre-SOC Power ISA 180nm ASIC Concept to completion: Why we chose nmigen and OpenPOWER What happened along the way IIT Roorkee 2021 Sponsored by NLnetâs PET Programme July 16, 2021 Luke Kenneth Casson Leighton The Libre-SOC OpenPOWER 180nm ASIC
- 2. Why start a new SoC? I Intel Management Engine, Apple QA issues, Spectre I Zero transparency: commodity hardware cannot be audited. I Endless proprietary drivers, âsimplestâ solution: License proprietary hard macros (with proprietary firmware) Adversely affects product development cost due to opaque driver bugs (Samsung S3C6410 / S5P100) I Alternative: Intel and Valve-Steam collaboration âMost productive business meeting ever!â https://tinyurl.com/valve-steam-intel I Ultimately it is a strategic business objective to develop entirely Libre hardware, firmware and drivers. Luke Kenneth Casson Leighton The Libre-SOC OpenPOWER 180nm ASIC
- 3. Why OpenPOWER? I Good ecosystem essential linux kernel, u-boot, compilers, OSes, Reference Implementation(s) I Supportive Foundation and Members need to be able to submit ISA augmentations (for proper peer review) I No NDAs, full transparency must be acceptable due to being funded under NLnetâs PET Programme I OpenPOWER: established for decades, excellent Foundation, Microwatt as Reference, approachable and friendly. Luke Kenneth Casson Leighton The Libre-SOC OpenPOWER 180nm ASIC
- 4. Choosing an HDL I 3 months careful evaluation: Chisel3, MyHDL, Verilog, VHDL, migen, nmigen I Love the OO capabilities of Chisel3, shame about the TIOBE Index (below 20th) I MyHDL is in python, but limits to a subset of python. Also, community not as large as for nmigen. I migen extremely inconvenient: errors created and not caught until ASIC synthesis level! I Verilog is 1980s (like BASIC and FORTRAN) - considered âmachine codeâ I VHDL is great (has records) but still no OO capability I Ultimately nmigen chosen due to large community, and because python is 3rd on the TIOBE index (contd) Luke Kenneth Casson Leighton The Libre-SOC OpenPOWER 180nm ASIC
- 5. Why nmigen? I Uses python to build an AST (Abstract Syntax Tree). Actually hands that over to yosys (to create ILANG file) after which verilog can (if necessary) be created I Deterministic synthesiseable behaviour (Signals are declared with their reset pattern: no more forgetting âif rstâ block). I python OO programming techniques can be deployed. classes and functions created which pass in parameters which change what HDL is created (IEEE754 FP16 / 32 / 64 for example) I python-based for-loops can e.g. read CSV files then generate a hierarchical nested suite of HDL Switch / Case statements (this is how the Libre-soc PowerISA decoder is implemented) I extreme OO abstraction can even be used to create âdynamic partitioned Signalsâ that have the same operator-overloaded âaddâ, âsubtractâ, âgreater-thanâ operators Luke Kenneth Casson Leighton The Libre-SOC OpenPOWER 180nm ASIC
- 6. Software Engineering Techniques I Entire project run along standard Libre Software Project Management: public bugtracker, public mailing lists, public IRC, public git repositories, Charter http://libre-soc.org/charter/ I None of our engineers are Hardware trained! They are all software developers who learned HDL! I The other way round makes life much harder. I Like Microwatt, we develop unit tests, use git revision control, and bugtrackers (TODO, still - set up Continuous Integration) I Unlike Microwatt, we also have a wiki for all documentation (backed by a git repository with full revision control) I Software Engineering techniques are critical for large project management! unit tests, unit tests, unit tests... Luke Kenneth Casson Leighton The Libre-SOC OpenPOWER 180nm ASIC
- 7. Auditability and Transparency I Funded by NLnetâs âPrivacy and Enhanced Trust Programmeâ I Matches well with business objectives to provide customers with ability to inspect down to Gate Level (GDS-II files) I (Impossible for Intel etc to do, due to 3rd party licensing of 50-60 pieces of HDL). I Sorbonne University LIP6.fr http://coriolis2.lip6.fr is an entirely Libre-licensed VLSI toolchain I (coriolis2 is âZero configâ from HDL to GDS-II) I Chips4Makers.io Cell Library - FlexLib - has âSymbolicâ and âRealâ versions. Symbolic is public and published, uses FreePDK45 âRealâ is NDAâd with Foundry. I Therefore: Libre-SOC team can work side-by-side with LIP6.fr WITHOUT signing a Foundry NDA. Luke Kenneth Casson Leighton The Libre-SOC OpenPOWER 180nm ASIC
- 8. Development Process I nmigen HDL, in python, converted to verilog using yosys I developed several thousand unit tests at every level I Jean-Paul Chaput improved coriolis2 to cope with automated layout of 130,000 Cells. Antenna, buffers, etc. I Chips4Makers FlexLib Cell Library also needed development, including a custom 4k SRAM block (under NDA, sorry) I Professor Galayko developed a Voltage-Controlled PLL, capable of between 150 and 900 mhz. I Marie-Minerve Louerat developed and ran HITAS (Static Timing Analysis tool). I Tried simulating the laid-out ASIC, required too much resources. Instead, simulated smaller ASICs Luke Kenneth Casson Leighton The Libre-SOC OpenPOWER 180nm ASIC
- 9. ASIC diagram sent to TSMC Luke Kenneth Casson Leighton The Libre-SOC OpenPOWER 180nm ASIC
- 10. The end Thank you Questions? I Discussion: http://lists.libre-soc.org I Libera IRC #libre-soc I http://libre-soc.org/ I http://nlnet.nl/PET I https://libre-soc.org/nlnet/#faq Luke Kenneth Casson Leighton The Libre-SOC OpenPOWER 180nm ASIC