8 bit Multiplier Accumulator

1
PROJECT REPORT
Multiplier Accumulator Circuit
Submitted by:
Daksh Raj Chopra
ID: 40054446
Nitin Singh
ID: 40067571
Rahul Malhotra
ID: 40036643
Submitted to:
Asim J. Al-Khalili
Distinguished Emeritus Professor
Electrical and Computer Engineering

2
TABLE OF CONTENTS
1. INTRODUCTION 5
1.1 Requirements 5
1.2 Project Breakdown 5
2. Combinational Circuits 6
2.1 And Gate 6
2.2 OR Gate 6
2.3 XOR Gate 6
2.4 Half Adder 7
2.5 Full Adder 8
2.6 Multiplier 9
2.7 Ripple carry Adder 11
2.8 Manchester Carry Adder 11
2.9 Multiplexer 11
3. Sequential Circuits 12
3.1 D-Flip Flop 12
3.2 Registers 12
4. Result and simulation 15
4.1 Block Diagram
4.2 Simulation result 16
5. Contribution 17
6. APPENDIX A: VHDL SOURCE 18

3
LIST OF FIGURES
Figure 2.1 Half Adder Circuit 7
Figure 2.2 Simulation result of the half adder 7
Figure 2.3 Full Adder using two half adder 8
Figure 2.4 Simulation result of the full adder 9
Figure 2.5 Multiplier Design using Wallace tree 10
Figure 2.6 Simulation result of the multiplier 10
Figure 2.7 n-bit Ripple Carry Adder 11
Figure 2.8 Simulation result of the 25 bit register 11
Figure 3.1 Circuit diagram of the D-flip flop using Nand and Nor 12
Figure 3.2 Design of n-bit register 13
Figure 3.3 Simulation result of the 8-bit register 13
Figure 4.1 Block Diagram of the Project 15
Figure 4.2 Simulation result of the project 16

4
LIST OF TABLES
Table 2.1 AND gate truth table 6
Table 2.2 OR gate truth table 6
Table 2.3 XOR gate truth table 6
Table 2.4 Half Adder truth table 7
Table 2.5 Full Adder truth table 8
Table 3.1 D-flip flop truth table 12

5
1. Introduction
The objective of this project is to design a multiplier that can calculate the multiplication of two 8
bit numbers and save the result in a 16 bit register. In order to design a multiplier we need 2 8 bit
register, 1 16 bit register. Two input AND gate, A full adder and a half adder. After calculation the
result of 10 consecutive multiplication, that need to save in a accumulator and then addition
perform and save the result in a different register. The goal is to design and simulate the result.
1.1 Requirements: The goal of this project is to design a multiplier accumulator circuit: in 3
stages:
1) Design an 8 bits register. A 16 bits register and a 25 bits register.
8bits of data are arriving on lines A & B in parallel on registers RA and RB. Numbers are
unsigned binary numbers. A total of 10 numbers will arrive in succession on each line. Data
are loaded into registers RA & RB by the command line LOAD.
2) Design a parallel multiplier
Use the parallel multiplier designed to multiply the multiplier (RA) and the multiplicand
(RB). Store the result in register, RD.
3) Design an Adder.
The Adder is used to add the ten results from the multiplier.
The output result will be in register RE.
We need to write the VHDL code, compile it, simulate VHDL design code, test it, synthesize
it.
1.2 Project Breakdown: The design need to be breakdown into a small blocks and start simulate
each block before final simulation of multiplier. The different block of the design is two 8-bit
registers, a multiplier, a 16 bit register, a 25 bit adder and a 25 bit register.

6
2. Combinational Circuits
This chapter includes the combinational circuits we used in the projects. The basic information of
the combinational circuits and simulation results includes in this chapter.
2.1 And Gate: A two input AND gate is required to perform the multiplication of two binary bit.
Here, in the project, we need AND gate in the half adder, full adder and multiplier. The truth table
and Boolean function of an AND gate is given below.
Y= A.B
Table 2.1 AND gate truth table
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
2.2 OR Gate: A two input OR gate is required to perform the function the addition of two binary
bit. We need a two input OR gate in the full adder to get the carry out. The truth table and Boolean
function of a OR gate is given below.
Y=A+B
Table 2.2 OR gate truth table
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
2.3 XOR gate: XOR perform the given Boolean function on the input. We need XOR gate to get
the sum of the half adder. The Boolean function and truth table of a XOR gate is given below.
Y=A’B+ AB’
Table 2.3 XOR gate truth table
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

7
2.4 Half Adder: Half adder is a combinational logic that calculate the sum of two bit and produce
a sum and a carry. It is a basic building block that perform the following Boolean function. We are
using half adder to add some of the partial product that have only two input bits. The truth table,
Boolean function and circuit diagram of the half adder is following.
Sum=A’B+AB’
Carry =A.B
Table 2.4 Half adder truth table
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
The XOR and AND gate are used in the half adder.
Figure.2.1 Half adder Circuit
Simulation result of the half adder is given below:
Figure.2.2 Simulation result of the half adder

8
2.5 Full Adder: Full adder is a combinational circuit that calculate the sum of three input bits and
produce a sum and a carry as output. The full adder is required in the project to perform the addition
on the partial products of the multiplier. The truth table, K-map, Boolean function and circuit
diagram of the full adder is following. We used two half adder and a OR gate to generate the sum
and carry of the full adder.
Table 2.5 Full Adder truth table
S = x’y’z + x’yz’ + xy’z’ + xyz
C= xy+yz+zx
Figure.2.3 Full adder using two half adder
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 1
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

9
Simulation result of the full adder is given below:
Figure.2.4 Simulation result of the full adder
2.6 Multiplier: The requirement of the project is to design a Multiplier that can perform the
multiplication on two 8-bits number.Multiplication of two 8 bits binary number will produce a 16-
bit binary number. Different kind of multiplier cab be used for that such as Add and shift multiplier,
Parallel multiplier, Array multiplier, Wallace tree multiplier. In order to get the optimized design,
we need to see the delay and area. We are considering the delay here and using Wallace tree
multiplier which us fastest multiplier. However, it takes maximum area but timing is more
important factor.
AND gate is being used to generate the partial products.
Number of partial products will be = N*M
Where, N= Length of Multiplicand, M= Length of Multiplier
Here in the project, the length of both multiplicand and multiplier is 8 bit. So, number of partial
products will be 64. The number of AND gates required to calculate the partial products are 64.
A7 A6 A5 A4 A3 A2 A1 A0
X B7 B6 B5 B4 B3 B2 B1 B0
-------------------------------------------------
A7.B0 A6.B0 A5.B0 A4.B0 A3.B0 A2.B0 A1.B0 A0.B0
+ A7.B1 A6.B1 A5.B1 A4.B1 A3.B1 A2.B1 A1.B1 A0.B1
+A7.B7 A6.B7 A5.B7 A4.B7 A3.B7 A2.B7 A1.B7 A0.B7
----------------------------------------------------------------------------------------
P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
After getting the 64 partial products, we need to add the partial products. There are 48 Full adders
and 8 Half adders used to add the partial products.
Patial
Productsto
be added

10
The area of the multiplier is 64 AND gates, 48 full adders and 8 half adders. The design of the
Wallace tree multiplier is given below. We will get a 16 bit output from the Wallace tree multiplier.
The project requirement is to save this 16 bit binary number into a 16 bit register and further.
Figure.2.5 Multiplier design using Wallace tree
The simulation results of the multiplier is given below:
Figure.2.6 Simulation result of the multiplier

11
2.7 Ripple carry Adder: The Ripple carry adder is designed by cascading full adders in series.
In, project we required a 25 bit adder to add the final outputs of the multiplier. The design of a n-
bit ripple carry adder is given below.
Figure.2.7 n-bit Ripple carry adder
The delay of a n bit adder is n full adder delay. So, 25 bit adder has a 25 full adder delay which is
very large.
The simulation result of the ripple carry adder is given below.
Figure.2.8 Simulation result of 25 bit Ripple carry adder
2.8 Manchester carry Adder: Manchester carry adder has very small delay and useful to reduce
the delay if the circuit. Carry propagate and generate action is taken place initially and go to the
select line of the multiplexer. The half adder is used to propagate and generate. The Boolean
function for propagate and generate is given below.
Gi = Ai Bi --carry generate of ith stage
Pi = Ai Bi --carry propagate of ith stage
Si = Pi Ci --sum of ith stage
Ci+1 = Gi + PiCi --carry out of ith stage
The design of a 16 bit Manchester carry adder is given below. The 25 bit Manchester carry adder
can be constructed by adding cells in series.
2.9 Multiplexer: Mux is a combinational circuit that select one of the input and forward the input
to the output. Select line is used to select the input. A multiplexer 2^n has [n] select lines. Here, to
design the Manchester adder, we need a 2^1 mux. The Select circuit diagram and truth table and
Boolean function of 2^1 mux is given below.

12
3. Sequential Circuits
3.1 D-Flip Flop: D-flip flop is a sequential circuit that is used to get the data from D input and
produce the same date as output with one cycle delay. We are using D flip flop which is also known
as data flip flop or delay flip Flop, to design the 8 bit registers, 16 bit registers and 25 bit registers.
The circuit diagram and the truth table of the D-flip flop is given below.
Figure.3.1 Circuit diagram of D-flip flop using Nand and Nor
Table 3.2 D-flip flop truth table
Q D Q(t+1)
0 0 0
0 1 1
1 0 0
1 1 1
3.2 Registers: Parallel In Parallel Out (PIPO) registers are the type of storage devices in which
both data loading as well as data retrieval processes occur in parallel mode. Figure shows a PIPO
register capable of storing n-bit input data word (Data in). Here each flip-flop stores an individual
bit of the data in appearing as its input (FF1 stores B1 appearing at D1; FF2 stores B2 appearing
at D2 … FFn stores Bn appearing at Dn) at the instant of first clock pulse. Further, at the same
instant, the bit stored in each individual flip-flop also appears at their respective output pins (Q1 =
D1; Q2 = D2 … Qn = Bn). This indicates that both data storage as well as data recovery occur at
a single (and at the same) clock pulse in PIPO registers.

13
Figure.3.2 Design of n-bit register
In our project we are using two 8-bit registers RA & RB , one 16-bit register :- RD , one 25 bit
register RE. RA and RB registers load 10 different 8-bit numbers into the multiplier. The output
of the 8x8 bit multiplier which is 16 bit is loaded into the register RD. Output of the adder is loaded
into the 25-bit register RE.
Simulation result of the 8-bit register is following.
Figure.3.3 Simulation result of the 8-bit register
Simulation results of the 16 bit register is following.

14
Simulation result of the 25 bit register is following.

15
4. Result and Simulation
We connected all the components and get the final result.
4.1 Block Diagram: The block diagram of the final project is given below.
Figure.4.1 Block Diagram of the Project
RB
8x8 MULTIPLIER
16 bitRegister
25 bit ADDER
25 bit register
RA

16
Register RA and RB will have 8-bit binary number ten times. The output of register RA and
register RB will become the input of the multiplier and produce a 16 bit output that will store in a
16 bit register. The 16 bit register will be one of the input of the 25 bit adder. Another input of the
25 bit adder will be from 25 bit register. The adder perform the operation on both the input and
store (updated value) the output into the 25 bit register. This operation will perform 10 times.
4.2 Simulation result: The simulation result of the project is following.
Figure.4.2 Simulation result of the project

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5. Contribution
The project has been planned under three major blocks.
A).Designing of the circuit
B). Coding of the circuit
C). Documentation of the project
During the project whenever we face any issue, we all tried to find a solution for that and share the
knowledge during the project meeting. In the start, everyone done all the basic building blocks
such as gates and adders. After that Rahul Malhotra worked on register part, Daksh Raj Chopra
worked on the Multiplier part and Nitin Singh worked on adder part. After completed their work,
we decided to merge all the blocked and implemented the final project. We port map by sitting all
together and get the simulation result.
In the documentation part, everyone written about the part they did and then we merge the data.

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APPENDIX A
Code for 8-bit Register
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY Reg_B_8 IS
PORT(
d : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ld : IN STD_LOGIC; -- load/enable.
clr : IN STD_LOGIC; -- async. clear.
clk : IN STD_LOGIC; -- clock.
RB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) -- output
);
END Reg_B_8;
ARCHITECTURE description OF register8 IS
BEGIN
process(clk, clr)
begin
if (clr = '1') then
q <= "00000000";
elsif (clk'event and clk = '1') then
if ld = '1' then
q <= d;
end if;
end if;
end process;

19
END description;
LIBRARY ieee;
ENTITY Reg_16 is
port( d : IN bit_vector(15 DOWNTO 0);
ld : IN bit; -- load/enable.
clr : IN bit; -- async. clear.
clk : IN bit; -- clock.
q : OUT bit_vector(15 DOWNTO 0) -- output
);
END Reg_16;
ARCHITECTURE description OF Reg_16 IS
BEGIN
process(clk, clr)
begin
if (clr = '1') then
q <= "0000000000000000";
if ld = '1' then
q <= d;
end if;
end if;

20
end process;
END description;
LIBRARY ieee;
ENTITY Reg_25 is
);
END Reg_25;
ARCHITECTURE description OF Reg_25 IS
BEGIN
process(clk, clr)
begin
if (clr = '1') then
q <= "0000000000000000000000000";
if ld = '1' then
q <= d;
end if;

21
end if;
end process;
END description;
Code for Counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--begin entity
entity clkcounter is
port
( clk ,reset : in std_logic;
load : out std_logic );
end clkcounter;
architecture counter_arch of clkcounter is
signal f: std_logic_vector (3 downto 0);
begin
process (clk,reset)
begin
if reset = '0' then
f <= "0000";
elsif clk'event and clk = '1' then
if f < "1100" then
f <= f + 1;
load <= '1';
else load <= '1';
end if;
end if;
end process;
end counter_arch;
Code for Half Adder
entity H_ADDER is
port (A,B: in BIT ; SUM , CRY : out BIT);
end H_ADDER;
architecture STRUCTURAL of H_ADDER is
component xor_2
port(A,B: in BIT; Z: out BIT);
end component;

22
component and_2
port(A,B: in BIT; Z: out BIT);
end component;
begin
X1: xor_2 port map( A,B,SUM );
X2: and_2 port map( A,B,CRY );
end STRUCTURAL ;
Code for Full Adder
entity full_adder is
port (A,B,C: in BIT ; SUM , CRY: out BIT);
end full_adder;
architecture STRUCTURAL of full_adder is
component H_ADDER
port(A,B: in BIT ;SUM , CRY: out BIT);
end component;
component or_2
port(A,B: in BIT ; Z: out BIT);
end component;
signal SUM1,CRY1,CRY2: BIT ;
begin
HA1: H_ADDER port map (A,B,SUM1,CRY1);
HA2: H_ADDER port map (SUM1,C,SUM,CRY2);
OR1: or_2 port map (CRY1,CRY2,CRY);
end STRUCTURAL;

23
Code for Ripple Carry Adder
entity RCA is
port (A: in bit_vector (15 downto 0 );
B: in bit_vector (24 downto 0);
C2 : in bit;
S: out bit_vector (24 downto 0 );
C :out bit_vector (24 downto 0 ));
end RCA;
architecture structure of RCA is
component full_adder
port (A,B,C: in BIT ; SUM , CRY: out BIT);
end component;
signal C1: bit_vector (24 downto 0);
begin
A1: full_adder port map(A(0),B(0),C2,S(0),C1(0));
A2: full_adder port map (A(1),B(1),C1(0),S(1),C1(1));

24
A17: full_adder port map ('0',B(16),C1(15),S(16),C1(16));
end structure;
Code for 8-bit Multiplier
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity multiplier_8 is
port (R1, R2 : in bit_vector (7 downto 0);
RD: out bit_vector (15 downto 0));
end multiplier_8;
architecture stuructural of multiplier_8 is
component and_2
port (A,B: in bit;
Z:out bit);
end component;
component H_ADDER
port (A,B: in bit;

25
SUM, CRY: out bit);
end component;
component full_adder
port (A,B,C: in bit;
SUM,CRY: out bit);
end component;
component Reg_8
PORT(
d : IN bit_vector(7 DOWNTO 0);
);
end component;
component Reg_16
PORT(
); -- output
END component;
signal RA: bit_vector(7 downto 0);

26
signal RB: bit_vector(7 downto 0);
signal P1,P2,P3,P4,P5,P6,P7,P8: bit_vector(0 to 7);
Signal RC:bit_vector (15 downto 0);
signal CR: bit_vector (55 downto 0);
signal XA: bit_vector ( 42 downto 1);
-- signal RD: bit_vector ( 15 downto 0);
signal ld,clr,clk:bit;
begin
Reg1:Reg_8 port map (R1,ld,clr,clk,RA);
Reg2: Reg_8 port map (R2,ld,clr,clk,RB);
A57: and_2 port map ( RA(0), RB(0), P1(0));

27

28

29
RC(0)<=P1(0);
HA1: H_ADDER port map (P1(1), P2(0), RC(1), CR(0));
FA1: full_adder port map (P1(2), P2(1), P3(0), XA(1), CR(1));
HA2: H_ADDER port map (XA(1), CR(0), RC(2), CR(2));
FA3: full_adder port map (XA(2), P4(0), CR(1), XA(3), CR(4));

30
FA28: full_adder port map (XA(26), CR(25), CR(26), XA(27), CR(33));
FA33: full_adder port map (XA(32), CR(33), CR(34), RC(9), CR(40));

31
FA46: full_adder port map (P7(7), P8(6), CR(50), XA(42), CR(53));
FA48: full_adder port map (P8(7), CR(53), CR(54), RC(14), RC(15));
reg3: Reg_16 port map (RC,ld,clr,clk,RD);
end stuructural;
Code for Accumulator (25 – bit Output)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity multiplieracc_final is
port ( A ,B : in bit_vector(7 downto 0) ;
clk : in bit ;
reset,load : in bit ;
D : out bit_vector(24 downto 0));
end multiplieracc_final;
architecture structural of multiplieracc_final is
component Reg_8
PORT(

32
);
end component;
component Reg_16
PORT(
); -- output
END component;
component Reg_25 is
);
END component;
component multiplier_8 is

33
port (R1, R2 : in bit_vector (7 downto 0);
RD : out bit_vector (15 downto 0));
end component;
component rca is
port (A: in bit_vector (15 downto 0 );
B: in bit_vector (24 downto 0);
C2 : in bit;
S: out bit_vector (24 downto 0 );
C :out bit_vector (24 downto 0 ));
end component;
signal RA ,RB : bit_vector(7 downto 0);
signal RC , C : bit_vector(15 downto 0);
signal RD ,sum ,cout: bit_vector(24 downto 0);
begin
reg8A_1 :Reg_8 port map ( A,load,reset,clk , RA );
reg8b_1 :Reg_8 port map ( B ,load,reset,clk, RB );
multiplier_1 : multiplier_8 port map ( RA ,RB , C ) ;
reg16C_1: Reg_16 port map ( C,load,reset,clk , RC);
final_adder1 : rca port map ( RC , RD ,'0', sum , cout);
reg25D_1: Reg_25 port map ( sum,load,reset,clk , RD);
D <= RD;
end structural;
Code for Stimulus
libraryIEEE;

34
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entity stim is
Port( RA , RB : out bit_vector(7 downto 0));
end stim;
architecture Behavioral of stim is
begin
process
begin
--00
RA <= "00000010" ;
RB <= "00000100";
wait for10 ns;
RA <= 00000010;
RB <= 00000100;
wait for10 ns;
RA <= 00000110;
RB <= 00000001;
wait for10 ns;
RA <= 00000011;
RB <= 00000101;
wait for10 ns;
RA <= 00000011;
RB <= 00000010;
wait for10 ns;
RA <= 00000100;
RB <= 00000101;

35
wait for10 ns;
RA <= 00000101;
RB <= 00000011;
wait for10 ns;
RA <= 00000011;
RB <= 00000011;
wait for10 ns;
RA <= 00000011;
RB <= 00001001;
wait for10 ns;
RA <= 00000101;
RB <= 00000111;
wait for10 ns;
end process;
end Behavioral;
Code for test bench
entity test_bench
end test_bench;
architecture concurrent of test_bench is
component multiplier_8 port (R1, R2 : in bit_vector(7 downto 0);
RD : out bit_vector( 15 downto 0));
end component;
component stim
port(a, b : out bit);
end component;
for inst_stim: stim use entity WORK.stim(behavioral);
forinst_and2: and_2 use entity WORK.multiplier_8(structural);
signal x, y : bit_vector (7 downto 0) ;

36
begin
inst_stim: stim port map (x, y);
inst_and2: multiplier_2 port map (x, y, z);
end concurrent ;

8 bit Multiplier Accumulator

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