8086 architecture
- 1. Architecture
- 2. 29,000 Transistors 16 bit Processor 16 Bit Registers Registers can hold unsigned data in the range of 0-65536. Can address 2^16 = 64 KB Memory (RAM) Addresses Segmented Memory
- 3. Physical address = Segment starting address + offset Segment Register Pointer/Index Register (16 bit) (16 bit) Segment Address (16bit) Offset Address (16 bit) + Physical Address (20 bit) Left Shift 4 times Segment Address (16bit) 0000 20 bit
- 4. 2^20 =1048576 (1MB) Example: Segment Address = 1005H Offset Address = 5555H Segment Address 0001 0000 0000 0101 4 Times Left Shifted 0001 0000 0000 0101 0000 Segment address + Offset Address/ 0101 0101 0101 0101 Effective Address ---------------------------------------- Physical Address 0001 0101 0101 1010 0101 ------------------------------------------ 1 5 5 A 5
- 5. Two independent functional units Bus Interface Unit Execution Unit Bus Interface Unit Memory Address and Data bus Interface Segment registers Instruction Pointer (IP) Register Instruction queue
- 6. Execution Unit Data Registers Pointer and Index Registers Flag Register -PSW ALU Control Unit
- 9. Fetches the Instruction from memory store it in Instruction Queue. Read data from port or memory. Write data to port or memory. Handles transfers of data and addresses on the buses
- 10. Direct the BIU where to fetch instructions or data Decodes instructions. Executes instruction. Control circuit directs internal operations. 16-bit ALU -- add, subtract, AND, OR, XOR, increment, decrement, complement or shift binary numbers. Does not use buses.
- 11. First In First Out register set – Queue 6 byte Queue BIU fetches up to 6 bytes of upcoming instruction. Stores the pre fetched bytes in IQ when EU executes current instruction. When EU is ready ,it reads the Instruction bytes from IQ Fasten the instruction fetching process
- 12. General Data Registers Segment Registers Pointers and Index Registers Flag Register
- 13. AX,BX,CX,DX – 16 Bit registers. Contains 2 8-bit registers. AH,BH,CH,DH – Higher order 8 bit of a word. AL,BL,CL,DL – Lower order 8 bit of a word. AX,AH,AL –16 bit and 8bit accumulators. BX,BH,BL – Base register. Stores effective address for address calculation. CX,CH,CL – default counter or count register in loop/string instruction. DX,DH,DL- Data register-Implicit operand or destination or port number.
- 14. 1MB memory is divided into 16 logical segments Each segment contains 64KB of memory. Four segment registers Store segment starting address Code segment (CS) Addresses segment with processor Instructions or code Instruction pointer(IP) contain offset address Automatically updated during far jump, far call and far return instructions. Cannot be changed directly.
- 15. Stack segment (SS) Address stack segment of memory Memory used to store stack data Processor uses stack for temporarly storing important data.(eg. Content of processor register). BP or SP contains offset/effective address.
- 16. Data segment (DS) Address segment with program data. Data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. Extra data Segment(ES) It also address segment with program data. By default DI register contain offset address in string manipulation instructions.
- 17. Pointer Registers: Contain offset address IP -offset for code segment (CS) Stack Pointer(SP), Base Pointer(BP) - offset for stack segment(SS) Index Registers : Used for indexed, based indexed and register indirect addressing Source Index(SI) - source data addresses in string manipulation instructions. Destination Index (DI) - destination data address in string manipulation instructions.
- 18. 16 bit Program Status Word (PSW) 7 bits are unused 9 bits are used as 9 flags 6 Condition Flags 3 Control Flags
- 19. Reflect the result of previous ALU operation. Sign Flag(SF) – MSB of the result. Negative number – 1 Zero Flag (ZF)- set to 1 if result is zero Parity Flag (PF)- set to 1 if low–order 8 bits contain an even number of 1’s . Carry Flag(CF) –set to 1 if there is carry in addition and if borrow is needed in subtraction. Auxiliary carry Flag (AF) –If there is a carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AC flag is set . Overflow Flag (OF) – Set to 1 if the result signed operation is overflow to the sign bit.
- 20. 1. 2345H+ 3219H 0010 0011 0100 0101 0011 0010 0001 1001 ---------------------------------- 0101 0101 0101 1110 ---------------------------------- SF=ZF =PF= CF=AF=OF=0 2. 5439H+ 456AH 0101 0100 0011 1001 0100 0101 0110 1010 ---------------------------------- 1001 1001 1010 0011 SF=PF=AF=OF=1 ZF=CF=0
- 21. Interrupt Flag (IF): It is an interrupt enable/disable flag. If it is set, the maskable interrupt can be recognized otherwise ignored. Trap Flag (TF): It is used for single step control. If it is set one instruction of a program is executed at a time for debugging. Direction Flag (DF): It is used in string operation. If it is set, string bytes are accessed from higher memory address to lower memory address.
- 22. 1.Given that segment register CS = 5203 ,IP =005A. Calculate the physical address of next instruction to be executed. 2. Given that the EA of a datum is 2359 and the DS=4908,what is the physical address of the datum? 3. If the segment register (SS) : 2402. To address the memory whose physical address of 244A0 corresponding to this segment, what will be the offset/effective address.
- 23. 3. Find the sum and flag values for AF,SF,ZF,CF,OF,PF after adding 62A0 to each of the following: (a) 4321 (b) CFA0 (c) 9D60 4. Find the difference and flag values for SF,ZF,CF,OF,PF after subtracting adding 4AE0 from each of the following. (a) 5D90 (b) 1234