An efficient constant multiplier architecture based on vertical horizontal binary common sub-expression elimination algorithm for reconfigurable fir filter synthesis

The document presents a proposal for an efficient constant multiplier architecture using the vertical-horizontal binary common sub-expression elimination (VHBCSE) algorithm to design a reconfigurable finite impulse response (FIR) filter with real-time coefficient adaptability. This approach applies a 2-bit binary common sub-expression elimination algorithm vertically and then a variable-bit approach horizontally, resulting in reduced switching activity of the multiplier block adders by 6.2% to 19.6% compared to existing algorithms. The document includes various sections outlining the system's structure, implementation, and benefits.