B sc3 unit 4 combi..lckt

KUD BSc 3rd SEM : ELECTRONICS : OPTO AND DIGITAL ELECTRONICS
BY : MAHIBOOB ALI K MULLA MSc , Mphil.
Asst.Prof.in electronics , SSGFG COLLEGE NARAGUND

E3 OPTO AND DIGITAL ELECTRONICS
UNIT-4 COMBINATIONAL LOGIC CIRCUIT

Combinational Logic Circuits :
Combinational Logic Circuits are memory less digital logic
circuits whose output at any instant in time depends only on
the combination of its inputs
Combinational Logic Circuits are only determined by the
logical function of their current input state, logic “0” or logic
“1”, at any given instant in time.
Combinational logic circuits can be very simple or very
complicated and any combinational circuit can be
implemented with only NAND and NOR gates as these are
classed as “universal” gates.

The three main ways of specifying the function of a combinational
logic circuit are:
1. Boolean Algebra – This forms the algebraic expression showing the
operation of the logic circuit for each input variable either True or
False that results in a logic “1” output.
2. Truth Table – A truth table defines the function of a logic gate by
providing a concise list that shows all the output states in tabular form
for each possible combination of input variable that the gate could
encounter.
3. Logic Diagram – This is a graphical representation of a logic circuit
that shows the wiring and connections of each individual logic gate,
represented by a specific graphical symbol, that implements the logic
circuit.

Classification of Combinational Logic
One of the most common uses of combinational logic is in Multiplexer and De-
multiplexer type circuits. Here, multiple inputs or outputs are connected to a
common signal line and logic gates are used to decode an address to select a
single data input or output switch.

Adder , Substractor,Comparator,Multiplexer,De-multiplexer,Decoder,
Encoder,DAC and ADC etc.are the combinational circuits.
Half Adder ( HA ):
The addition of 2 bits is done using a combination circuit called Half
adder. The input variables are augend and addend bits and output
variables are sum & carry bits. A and B are the two input bits.
Truth Table:

Logical Expression:
Sum = A XOR B
Carry = A AND B
Implementation:
Full Adder
Full Adder is the adder which adds three inputs and produces two
outputs. The first two inputs are A and B and the third input is an
input carry as C-IN. The output carry is designated as C-OUT and the
normal output is designated as S which is SUM.

Full Adder Truth Table:
Logical Expression for SUM:
S = C-IN XOR

COUT = AB + C-IN (A’ B + A B’)
COUT = AB + C-IN (A EX – OR B)
OR

A Half Subtractor Circuit:
A half subtractor is a logical circuit that performs a subtraction
operation on two binary digits. The half subtractor produces a sum
and a borrow bit for the next stage.
Half Subtractor with Borrow-out

Truth Table: Logical Expression
Difference = A XOR B
Borrow = overline{A}B

Full Subtractor:
A full subtractor is a combinational circuit that performs subtraction
of two bits, one is minuend and other is subtrahend, taking into
account borrow of the previous adjacent lower minuend bit. This
circuit has three inputs and two outputs. The three inputs A, B and
Bin, denote the minuend, subtrahend, and previous borrow,
respectively. The two outputs, D and Bout represent the difference
and output borrow, respectively.

Truth Table – Logical expression for difference –
D = (A XOR B) XOR Bin
Logical expression for borrow –
Bout = Bin (A XOR B)’ + A’B
Logic Circuit for Full Subtractor –

Magnitude Comparator :
A magnitude digital Comparator is a combinational circuit that
compares two digital or binary numbers in order to find out whether
one binary number is equal, less than or greater than the other binary
number. We logically design a circuit for which we will have two
inputs one for A and other for B and have three output terminals, one
for A > B condition, one for A = B condition and one for A < B
condition.

2-Bit Magnitude Comparator –
A comparator used to compare two binary numbers each of two bits
is called a 2-bit Magnitude comparator. It consists of four inputs and
three outputs to generate less than, equal to and greater than
between two binary numbers.
The truth table for a 2-bit comparator is given below:
A>B:A1B1’ + A0B1’B0’ + A1A0B0’
A=B: A1’A0’B1’B0’ + A1’A0B1’B0 +
A1A0B1B0 + A1A0’B1B0’
A<B:A1’B1 + A0’B1B0 + A1’A0’B0

The truth table for a 2-bit comparator is given below:

logic circuit for this comparator as given below:

1. Encoders –
An encoder is a combinational circuit that converts binary information
in the form of a 2N input lines into N output lines, which represent N
bit code for the input. For simple encoders, it is assumed that only one
input line is active at a time.
Decimal to BCD Encoder –
The decimal to binary encoder usually consists of 10 input lines and 4
output lines. Each input line corresponds to the each decimal digit
and 4 outputs correspond to the BCD code. This encoder accepts the
decoded decimal data as an input and encodes it to the BCD output
which is available on the output lines. The figure below shows the
logic symbol of decimal to BCD encoder :

The truth table for decimal to BCD encoder is as follows:

Logical expression for A3, A2, A1 and A0 :
A3 = Y9 + Y8
A2 = Y7 + Y6 + Y5 +Y4
A1 = Y7 + Y6 + Y3 +Y2
A0 = Y9 + Y7 +Y5 +Y3 + Y1
The above two Boolean functions can be implemented
using OR gates :

Logical expression for A3, A2, A1 and A0 :
A3 = Y9 + Y8
A2 = Y7 + Y6 + Y5 +Y4
A1 = Y7 + Y6 + Y3 +Y2
A0 = Y9 + Y7 +Y5 +Y3 + Y1
The above two Boolean functions can be implemented using OR gates :
Priority Encoder –
A 4 to 2 priority encoder has 4 inputs : Y3, Y2, Y1 & Y0 and 2 outputs :
A1 & A0. Here, the input, Y3 has the highest priority, whereas the
input, Y0 has the lowest priority. In this case, even if more than one
input is ‘1’ at the same time, the output will be the (binary) code
corresponding to the input, which is having higher priority.
The truth table for priority encoder is as follows :

The truth table for priority encoder :

Let us consider the 4 to 2 priority encoder as an example.
From the truth table, we see that when all inputs are 0, our V
bit or the valid bit is zero and outputs are not used. The x’s in
the table show the don’t care condition, i.e, it may either be
0 or 1. Here, D3 has highest priority, therefore, whatever be
the other inputs, when D3 is high, output has to be 11. And
D0 has the lowest priority, therefore the output would be 00
only when D0 is high and the other input lines are low.
Similarly, D2 has higher priority over D1 and D0 but lower
than D3 therefore the output would be 010 only when D2 is
high and D3 are low (D0 & D1 are don’t care).

Drawbacks of Normal Encoders –There is an ambiguity, when all
outputs of encoder are equal to zero.
If more than one input is active High, then the encoder produces an
output, which may not be the correct code.
So, to overcome these difficulties, we should assign priorities to each
input of encoder. Then, the output of encoder will be the ( code
corresponding to the active High inputs, which has higher priority.
Uses of Encoders – Encoders are very common electronic circuits used
in all digital systems. Encoders are used to translate the decimal values
to the binary in order to perform the binary functions such as addition,
subtraction, multiplication, etc.
Other applications especially for Priority Encoders may include
detecting interrupts in microprocessor applications.

Decoder is a combinational circuit that has ‘n’ input lines and
maximum of 2n output lines. One of these outputs will be active
High based on the combination of inputs present, when the
decoder is enabled. That means decoder detects a particular code.
The outputs of the decoder are nothing but the min terms of ‘n’
input variables lines, when it is enabled.
2 to 4 Decoder:
Let 2 to 4 Decoder has two inputs A1 & A0 and four outputs Y3, Y2,
Y1 & Y0. The block diagram of 2 to 4 decoder is shown in the
following figure.
Decoders:

One of these four outputs will be ‘1’ for each combination of inputs
when enable, E is ‘1’. The Truth table of 2 to 4 decoder is shown
below.

Enable Inputs Outputs
E A1 A0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
From Truth table, we can write the Boolean functions for each
output as

Y3=E.A1.A0
Y2=E.A1.A0′
Y1=E.A1′.A0
Y0=E.A1′.A0′
Each output is having one product term. So, there are
four product terms in total. We can implement these
four product terms by using four AND gates having
three inputs each & two inverters. The circuit diagram
of 2 to 4 decoder is shown in the following figure.

Therefore, the outputs of 2 to 4 decoder are nothing
but the min terms of two input variables A1 & A0,
when enable, E is equal to one. If enable, E is zero, then
all the outputs of decoder will be equal to zero.
Similarly, 3 to 8 decoder produces eight min terms of
three input variables A2, A1 & A0 and 4 to 16 decoder
produces sixteen min terms of four input variables A3,
A2, A1 & A0.

3 Line to 8 Line Decoder
This decoder circuit gives 8 logic outputs for 3 inputs and has a enable
pin. The circuit is designed with AND and NAND logic gates. It takes 3
binary inputs and activates one of the eight outputs. 3 to 8 line
decoder circuit is also called as binary to an octal decoder.
3 to 8 Line Decoder
Block Diagram

The decoder circuit works only when the Enable pin (E) is high. S0, S1 and S2 are
three different inputs and Y0, Y1, Y2, Y3. Y4. Y5. Y6. Y7 are the eight outputs. The
below table gives the truth table of 3 to 8 line decoder using NAND Gates.

Fig. for 3 to 8 line decoder using NAND Gates.

The 3:8 Decoder using NAND Gates.The output equations are given as Y0= ABC,
Y1=ABC” ,Y2=AB”C,Y3=AB”C”,Y4=A”BC,Y5=A”BC”,Y6=A”B”C,Y7=A”B”C”
BCD to Decimal Decoder (1-of-10) : IC-7442

The 74HC/HCT42 are BCD to decimal decoders. These decoders accept four
active HIGH BCD inputs and provide 10 mutually exclusive active LOW outputs.
The active LOW outputs facilitate addressing other MSI circuits with active LOW
input enables. They are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
The logic design of the ’42’ ensures that all outputs are HIGH when binary codes
greater than nine are applied to the inputs.
The most significant input (A3) produces an useful inhibit function when the
’42’ is used as a 1-of-8 decoder. The A3 input can also be used as the data input
in an 8-output demultiplexer application.
Features: Mutually exclusive outputs , 1-of-8 demultiplexing capability , Outputs
disabled for input codes above nine , Output capability: standard , IC Type : MSI
Applications :
Driving LED displays , Driving incandescent displays , Driving fluorescent
displays , Driving LCD displays , Driving gas discharge displays .

BCD to 7 Segment Decoder
In Binary Coded Decimal (BCD) encoding scheme each of the decimal numbers(0-9) is
represented by its equivalent binary pattern(which is generally of 4-bits).
Whereas, Seven segment display is an electronic device which consists of seven Light
Emitting Diodes (LEDs) arranged in a some definite pattern (common cathode or common
anode type), which is used to display Hexadecimal numerals(in this case decimal numbers,as
input is BCD i.e., 0-9).Two types of seven segment LED display:
Common Cathode Type: In this type of display all cathodes of the seven LEDs are connected
together to the ground or -Vcc( hence, common cathode) and LED displays digits when some
‘HIGH’ signal is supplied to the individual anodes.
Common Anode Type: In this type of display all the anodes of the seven LEDs are connected
to battery or +Vcc and LED displays digits when some ‘LOW’ signal is supplied to the
individual cathodes.
But, seven segment display does not work by directly supplying voltage to different
segments of LEDs. First, our decimal number is changed to its BCD equivalent signal then
BCD to seven segment decoder converts that signals to the form which is fed to seven
segment display.

This BCD to seven segment decoder has four input lines (A, B, C and D) and 7
output lines (a, b, c, d, e, f and g), this output is given to seven segment LED
display which displays the decimal number depending upon inputs.

Truth Table – For common cathode type BCD to seven segment decoder:

Note –
For Common Anode type seven segment LED display, we only have to
interchange all ‘0s’ and ‘1s’ in the output side i.e., (for a, b, c, d, e, f,
and g replace all ‘1’ by ‘0’ and vice versa) and solve using K-map.
Output for first combination of inputs (A, B, C and D) in Truth Table
corresponds to ‘0’ and last combination corresponds to ‘9’. Similarly
rest corresponds from 2 to 8 from top to bottom.
BCD numbers only range from 0 to 9,thus rest inputs from 10-F are
invalid inputs.
Applications –
Seven-segment displays are used to display the digits in calculators,
clocks, various measuring instruments, digital watches and digital
counters.

Multiplexers(Data Selector):
Multiplexer is a combinational circuit that has maximum of 2n
data inputs, ‘n’ selection lines and single output line. One of
these data inputs will be connected to the output based on
the values of selection lines.
Since there are ‘n’ selection lines, there will be 2n possible
combinations of zeros and ones. So, each combination will
select only one data input. Multiplexer is also called as Mux.
4x1 Multiplexer
4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two
selection lines s1 & s0 and one output Y. The block diagram of
4x1 Multiplexer is shown in the following figure.

One of these 4 inputs will be connected to the output based on the
combination of inputs present at these two selection lines. Truth
table of 4x1 Multiplexer is shown below.
Selection Lines Output
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
From Truth table, we can directly write the Boolean function for output, Y as
Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3
We can implement this Boolean function using Inverters, AND gates & OR
gate. The circuit diagram of 4x1 multiplexer is shown in the following figure.

We can easily understand the operation of the above circuit. Similarly, you can
implement 8x1 Multiplexer and 16x1 multiplexer by following the same
procedure.

De-Multiplexers (Data Distributor):
De-Multiplexer is a combinational circuit that performs the reverse
operation of Multiplexer. It has single input, ‘n’ selection lines and
maximum of 2n outputs. The input will be connected to one of these
outputs based on the values of selection lines.
Since there are ‘n’ selection lines, there will be 2n possible
combinations of zeros and ones. So, each combination can select
only one output. De-Multiplexer is also called as De-Mux.
1x4 De-Multiplexer
1x4 De-Multiplexer has one input I, two selection lines, s1 & s0 and
four outputs Y3, Y2, Y1 &Y0. The block diagram of 1x4 De-Multiplexer
is shown in the following figure.
Example: IC-74154 De-Mux.(1:16) , IC-74138(1:8)

The single input ‘I’ will be connected to one of the four outputs, Y3 to Y0 based on the values
of selection lines s1 & s0. The Truth table of 1x4 De-Multiplexer is shown below.
Selection Inputs Outputs
S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 I
0 1 0 0 I 0
1 0 0 I 0 0
1 1 I 0 0 0
From the above Truth table, we can directly write the Boolean functions for each output as

Y3=s1s0I , Y2=s1s0′I , Y1=s1′s0I , Y0=s1′s0′I .
We can implement these Boolean functions using Inverters & 3-input AND gates.
The circuit diagram of 1x4 De-Multiplexer is shown in the following figure.

Data Converters:
A data converter is an electronic circuit that converts data of one form to
another.
There are two types of data converters −
Analog to Digital Converter , Digital to Analog Converter
If we want to connect the output of an analog circuit as an input of a digital
circuit, then we have to place an interfacing circuit between them. This
interfacing circuit that converts the analog signal into digital signal is called as
Analog to Digital Converter.
Similarly, if we want to connect the output of a digital circuit as an input of an
analog circuit, then we have to place an interfacing circuit between them. This
interfacing circuit that converts the digital signal into an analog signal is called as
Digital to Analog Converter.
Note that some Analog to Digital Converters may require Digital to Analog
Converter as an internal block for their operation.

Specifications
The following are the specifications that are related to data conversions −
Resolution , Conversion Time
Resolution
Resolution is the minimum amount of change needed in an analog input voltage
for it to be represented in binary (digital) output. It depends on the number of
bits that are used in the digital output.
Mathematically, resolution can be represented as
Resolution=1/2↑N
where, ‘N’ is the number of bits that are present in the digital output.
From the above formula, we can observe that there exists an inverse relationship
between the resolution and number of bits. Therefore, resolution decreases as
the number of bits increases and vice-versa.
Resolution can also be defined as the ratio of maximum analog input voltage that
can be represented in binary and the equivalent binary number.

Mathematically, resolution can be represented as
Resolution=VFS/(2↑N) −1
where,
VFS is the full scale input voltage or maximum analog input voltage,
‘N’ is the number of bits that are present in the digital output.
Conversion Time
The amount of time required for a data converter in order to convert the data (information)
of one form into its equivalent data in other form is called as conversion time. Since we
have two types of data converters, there are two types of conversion times as follows
Analog to Digital Conversion time
Digital to Analog Conversion time
The amount of time required for an Analog to Digital Converter (ADC) to convert the analog
input voltage into its equivalent binary (digital) output is called as Analog to Digital
conversion time. It depends on the number of bits that are used in the digital output.
The amount of time required for a Digital to Analog Converter (DAC) to convert the binary
(digital) input into its equivalent analog output voltage is called as Digital to Analog
conversion time. It depends on the number of bits that are present in the binary (digital)
input.

Digital to Analog Converters:
A Digital to Analog Converter (DAC) converts a digital input signal into
an analog output signal. The digital signal is represented with a binary
code, which is a combination of bits 0 and 1. This chapter deals with
Digital to Analog Converters in detail.
The block diagram of DAC is shown in the following figure −

A Digital to Analog Converter (DAC) consists of a number of binary inputs and a
single output. In general, the number of binary inputs of a DAC will be a power
of two.
Types of DACs:
There are two types of DACs
Weighted Resistor DAC
R-2R Ladder DAC
This section discusses about these two types of DACs in detail −
Weighted Resistor DAC:
A weighted resistor DAC produces an analog output, which is almost equal to
the digital (binary) input by using binary weighted resistors in the inverting
adder circuit. In short, a binary weighted resistor DAC is called as weighted
resistor DAC.
The circuit diagram of a 3-bit binary weighted resistor DAC is shown in the
following figure

Recall that the bits of a binary number can have only one of the two values. i.e.,
either 0 or 1. Let the 3-bit binary input is b2b1b0. Here, the bits b2 and b0
denote the Most Significant Bit (MSB) and Least Significant Bit (LSB)
respectively.

The digital switches shown in the above figure will be connected to ground,
when the corresponding input bits are equal to ‘0’. Similarly, the digital switches
shown in the above figure will be connected to the negative reference voltage,
−VR when the corresponding input bits are equal to ‘1’.
In the above circuit, the non-inverting input terminal of an op-amp is connected
to ground. That means zero volts is applied at the non-inverting input terminal of
op-amp. According to the virtual short concept, the voltage at the inverting input
terminal of opamp is same as that of the voltage present at its non-inverting
input terminal. So, the voltage at the inverting input terminal’s node will be zero
volts. The nodal equation at the inverting input terminal’s node is:
0+VRb2/2↑0R+0+VRb1/2↑1R+0+VRb0/2↑2R+0−V0/Rf=0
=>V0/Rf=VRb2/2 ↑ 0R+VRb1/2 ↑ 1R+VRb0/2 ↑ 2R
=>V0=VRRf/R{b2/2 ↑ 0+b1/2 ↑ 1+b0/22} Substituting, R=2Rf𝑓 in above
equation. =>V0=VRRf/2Rf{b2/2 ↑ 0+b1/2 ↑ 1+b0/2 ↑ 2}
=>V0=VR/2{b2/2 ↑ 0+b1/2 ↑ 1+b0/2 ↑ 2}

The above equation represents the output voltage equation of a 3-bit binary
weighted resistor DAC. Since the number of bits are three in the binary (digital)
input, we will get seven possible values of output voltage by varying the binary
input from 000 to 111 for a fixed reference voltage, VR.
We can write the generalized output voltage equation of an N-bit binary
weighted resistor DAC as shown below based on the output voltage equation of
a 3-bit binary weighted resistor DAC.
=>V0=VR/2{bN−1/2↑0+bN−2/2 ↑ 1+....+b0/2 ↑( N−1)}
The disadvantages of a binary weighted resistor DAC are as follows −
The difference between the resistance values corresponding to LSB & MSB will
increase as the number of bits present in the digital input increases.
It is difficult to design more accurate resistors as the number of bits present in
the digital input increases.

R-2R Ladder DAC:
The R-2R Ladder DAC overcomes the disadvantages of a
binary weighted resistor DAC. As the name suggests, R-
2R Ladder DAC produces an analog output, which is
almost equal to the digital (binary) input by using a R-
2R ladder network in the inverting adder circuit.

The circuit diagram of a 3-bit R-2R Ladder DAC is shown in the following figure −

Recall that the bits of a binary number can have only one of the two
values. i.e., either 0 or 1. Let the 3-bit binary input is b2b1b0. Here,
the bits b2 and b0 denote the Most Significant Bit (MSB) and Least
Significant Bit (LSB) respectively.
The digital switches shown in the above figure will be connected to
ground, when the corresponding input bits are equal to ‘0’. Similarly,
the digital switches shown in above figure will be connected to the
negative reference voltage, −VR when the corresponding input bits
are equal to ‘1’.
It is difficult to get the generalized output voltage equation of a R-2R
Ladder DAC. But, we can find the analog output voltage values of R-
2R Ladder DAC for individual binary input combinations easily.

The advantages of a R-2R Ladder DAC are as follows −
R-2R Ladder DAC contains only two values of resistor: R
and 2R. So, it is easy to select and design more accurate
resistors.
If more number of bits are present in the digital input,
then we have to include required number of R-2R
sections additionally.
Due to the above advantages, R-2R Ladder DAC is
preferable over binary weighted resistor DAC.

Analog to Digital Converters (A/D):
This type of converter is used to convert analog voltage to its
corresponding digital output. The function of the analog to
digital converter is exactly opposite to that of a DIGITAL TO
ANALOG CONVERTER. Like a D/A converter, an A/D converter
is also specified as 8, 10, 12 or 16 bit.
Successive Approximation Type Analog to Digital Converter:
A successive approximation A/D converter consists of a
comparator, a successive approximation register (SAR), output
latches, and a D/A converter. The circuit diagram is shown
below.

Successive Approximation Type Analog to Digital Converter :
The main part of the circuit is the 8-bit SAR, whose output is given to an 8-bit
D/A converter. The analog output Va of the D/A converter is then compared to
an analog signal Vin by the comparator. The output of the comparator is a serial
data input to the SAR. Till the digital output (8 bits) of the SAR is equivalent to
the analog input Vin, the SAR adjusts itself. The 8-bit latch at the end of
conversation holds onto the resultant digital data output.
Working: At the start of a conversion cycle, the SAR is reset by making the start
signal (S) high. The MSB of the SAR (Q7) is set as soon as the first transition
from LOW to HIGH is introduced. The output is given to the D/A converter
which produces an analog equivalent of the MSB and is compared with the
analog input Vin. If comparator output is LOW, D/A output will be greater than
Vin and the MSB will be cleared by the SAR.
If comparator output is HIGH, D/A output will be less than Vin and the MSB will
be set to the next position (Q7 to Q6) by the SAR.

According to the comparator output, the SAR will either keep
or reset the Q6 bit. This process goes on until all the bits are
tried. After Q0 is tried, the SAR makes the conversion
complete (CC) signal HIGH to show that the parallel output
lines contain valid data. The CC signal in turn enables the
latch, and digital data appear at the output of the latch. As
the SAR determines each bit, digital data is also available
serially. As shown in the figure above, the CC signal is
connected to the start conversion input in order to convert
the cycle continuously. The biggest advantage of such a circuit
is its high speed. It may be more complex than an A/D
converter, but it offers better resolution.

4-Bits SAR ADC using
DAC
15/16 1111
14/16 1110
13/16 1101
12/16 1100
11/16 1011
10/16 1010
9/16 1001
8/16 1000
7/16 0111
6/16 0110
5/16 0101
4/16 0100
3/16 0011
2/16 0010
1/16 0001
0V 0000

Summary
Strengths of the SAR ADC
Low power consumption
Physically Small
Weaknesses of the SAR ADC
Low sampling rates for high resolutions
Limited resolution due to limits of DAC and Comparator
Size increases with number of bits
Applications of the SAR ADC
Ideal for multichannel data acquisition systems with sampling
frequencies under 10 MHz and resolutions between 8-16 bits.

B sc3 unit 4 combi..lckt

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