B045060813
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This document describes the design and verification of an advanced carry select adder. It begins with an abstract that explains carry select adders are one of the fastest adders used in processors to perform fast arithmetic. The authors developed 16, 32, 64, and 128-bit square root carry select adder architectures using a gate-level modification to significantly reduce area and power compared to a regular square root carry select adder. It then discusses the basic structures of regular and modified carry select adders. The modified architecture replaces ripple carry adders with binary to excess-1 converters to reduce area and power. Uniform carry select adders using carry skip adders are also proposed. Implementation results show the modified and uniform
![Guru Dixit Chepuri et al Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 5( Version 6), May 2014, pp.08-13
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evaluationisdone bycountingthe totalnumberof
AOIgatesrequiredforeachlogicblock.Basedon
thisapproach, theblocksof2:1mux,HalfAdder
(HA),andFAareevaluatedandlistedinTableI.
Fig. 1:DelayandArea evaluationofanXORgate.
Fig.2:4-bBEC.
The Booleanexpressionsof the4-bit BECis
listedas(notethefunctionalsymbols~NOT,&AND,
^XOR)
X0= ~B0
X1= B0^B1
X2= B2^(B0&B1)
X3= B3^(B0&B1&B2)
Fig.3:4-bBECwith8:4mux.
Table 1: Delay and Area count of Basic Blocks of
CSA
Thebasic workistouseBinaryto Excess-
1Converter (BEC)insteadofRCAwithCin=1in
theregularCSA toachievelowerareaandpower
consumption. ThemainadvantageofthisBEClogic
comes fromthelessernumber oflogic gatesthanthen-
bit
FullAdder(FA)structure.Asstatedabovethemainidea
ofthisworkistouse BECinsteadoftheRCAwithCin=1
inordertoreducetheareaandpowerconsumptionofthe
regularCSA. Toreplacethen-bitRCA,ann+1-bitBEC
isrequired. Astructure and the function tableofa4-bit
BECareshowninFig.2.
III. BASICSTRUCTUREOF
REGULAR16-BIT CSA
A16-bitcarryselectaddercanbedeveloped
intwodifferentsizesnamely uniformblocksizeand
variableblocksize.Similarlya32,64and128-bit can
alsobe developedintwomodesof different
blocksizes.Ripple-carry addersarethesimplestand
mostcompactfulladders,buttheirperformance is
limitedbyacarrythatmustpropagatefromtheleast-
significantbittothe most-significantbit.Thevarious
16,32,64and128-bitCSAcanalsobedeveloped
byusingripplecarryadders.Thespeedofacarry-
selectaddercanbeimprovedupto 40%to 90%,by
performingthe additionsinparallel,andreducingthe
maximum carrydelay.
Fig. 4showstheRegularstructureof 16-bit
SQRTCSA.Itincludesmanyripplecarryaddersof
variablesizeswhicharedividedinto groups.Group0
contains2-bitRCAwhichcontainsonly oneripple carry
adderwhichaddstheinputbitsandtheinput carry
andresultstosum[1:0]andthecarry out.The carry
outoftheGroup0whichactsastheselection inputto
muxwhichisingroup1, selectstheresult fromthe
correspondingRCA(Cin=0)orRCA (Cin=1).Similarly
the remaininggroupswillbe selected
dependingontheCout fromtheprevious groups.
InRegularCSLA,thereisonly oneRCAto
performtheadditionoftheleastsignificantbits[1:0]. The
remainingbits(otherthanLSBs),the additionis
performedby usingtwoRCAscorrespondingtothe one
assumingacarry-inof0,theotheracarry-inof1](https://image.slidesharecdn.com/b045060813-140713012814-phpapp02/85/B045060813-2-320.jpg)
![Guru Dixit Chepuri et al Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 5( Version 6), May 2014, pp.08-13
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withinagroup.Inagroup,thereare twoRCAs that
receivethesamedata inputsbutdifferentCin. The
actualCinfromthepreceding sector selects one of the
two RCAs. That is, as shown in Fig. 4, if the carry-in is
0, the sum and carry-out of the upper RCA is selected,
and if the carry-in is 1, the sum and carry-out of lower
RCA is selected.
Fig.4:Regular16-bSQRTCSA.
IV. BASIC STRUCTURE OFMODIFIED
16-BIT CSA
This architectureissimilartoregular64-bit
SQRTCSA,theonly changeisthat,wereplace
RCAwithCin=1amongthetwoavailableRCAsin
agroupwithaBEC. ThisBEChas afeaturethatit
canperformthe similaroperationasthatofthe replaced
RCA with Cin=1. Fig 6shows theModified
blockdiagramof 16-bit SQRTCSA. The
numberofbitsrequiredforBEClogicis1bit more than
theRCAbits. The modified block diagramis
alsodividedintovariousgroupsof
variablesizesofbitswith each grouphavingthe
ripplecarry adders, BEC andcorrespondingmux.The
basic BEC is shown in Fig. 3. As showninthe
Fig.5,Group0containoneRCA onlywhichis
havinginputof lowersignificantbit andcarry
inbitandproducesresultofsum [1:0]
andcarryoutwhichisactingasmuxselectionlinefor
thenextgroup, similarlytheprocedurecontinuesfor
highergroupsbuttheyincludesBEClogicinsteadofRCA
withCin=1.Basedontheconsiderationof
delayvalues,thearrivaltimeofselectioninputC1
of8:3muxisearlierthanthesumofRCA andBEC.
Forremaininggroupstheselectioninput arrivalis
laterthantheRCA andBEC.
Thus, thesum1andc1 (output from mux)
dependson mux and results computed byRCAand
BEC respectively. The sum2 depends on c1 and
mux. For theremainingpartsthearrivaltimeof
muxselection
inputisalwaysgreaterthanthearrivaltimeof data
inputsfromtheBEC’s.Thus,thedelay ofthe
remainingMUXdependsonthearrivaltimeofmux
selectioninputand themuxdelay.InthisModified CSA
architecture, the implementation
codeforFullAdderandMultiplexersof6:3,8:4,and10:5u
p to24:11weredesigned.Thedesign codefor
theBECwasdesignedby usingNOT,XORandAND
gates.Then2, 3,4,5upto11-bitripplecarryadder
wasdesigned.
V. BASIC STRUCTURE OF
UNIFORM16-BIT CSA
InthisUCSLA,carryskipadder(CSKA)is
usedforreducing delayand areacomparedwithregular
and modified CSA.Theupperadderhas theCSKA
withCin=0andtheBECcircuitisinthelower
adderinsteadofRCAwithCin=1intheUCSA.The 16
bit UCSA architecture isshowninFig.7.The CSKA
shown in Fig.5isusedtoreducethedelay
comparedwithRCA.Thegroup1has onlyone set
of4bitCSKAwithcarry-in signal.The carry-
outoftheCSKA isusedas controlsignalin
multiplexer.Thegroup2hasonesetof4bitCSKAwithCin
=0
andonesetof5bitBECinsteadof4bitCSKAwithCin=1.](https://image.slidesharecdn.com/b045060813-140713012814-phpapp02/85/B045060813-3-320.jpg)
![Guru Dixit Chepuri et al Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 5( Version 6), May 2014, pp.08-13
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Fig. 8: 16-bit CSA output Waveform
S.No
.
Adders Power (nw) Area
(µm2
)
1. 16–bit
Regular 32803.4 652
Modified 31585.5 562
Uniform 29871.4 528
2. 32–bit
Regular 69970.6 1356
Modified 63658.8 1156
Uniform 63108.8 1128
3. 64–bit
Regular 143885.5 2805
Modified 131386.0 2387
Uniform 125165.7 2327
4. 128–bit
Regular 311320.8 5719
Modified 276443.4 4844
Uniform 257825.0 4724
Table 2: Comparisons of Regular, Modified and
Uniform CSA
VII. CONCLUSION
The synthesis and simulation of Regular
Square Root Carry Select
Adder(SQRTCSLA),ModifiedSquareRootCarry
SelectAdder and Uniform Square Root Carry
Select Adder wasdonein
VerilogHardwareDescriptionLanguageusingXilinxIS
Etool and Synthesis is done using Cadence.Acarry-
selectadder is a particular way to implement anadder
in which a logic element thatcomputesthe
(n+1)bitsumoftwo n -bitnumbers and also replacing
Ripple Carry Adder with Carry Skip Adder.
Theapproachproposedinthisreport is
toreducetheareaandpowerofSQRT
CSLAarchitecture.Thereducednumberofgatesofthisw
orkoffersgreatadvantage
inthereductionofareaandtotalpower. But minimization
of delay was not possible using the proposed
architecture. The compared results show that the area
and power of 128-bit Uniform SQRT CSLA are
significantly reduced by 17.39% and 17.18%
respectively. Similarly, the area and power of 128-bit
Modified SQRT CSLA are significantly reduced by
15.29% and 11.20% respectively which indicates the
success of the method for power and delay. The
power-delay Product and Area-Delay Product of the
proposed design varies for 16-, 32-, 64-, 128-bit sizes
The Uniform SQRT CSLA Architecture is
therefore low power, low area, simple and efficient for
VLSI hardware implementation. It would be interesting
to design a SQRT CSLA Architecture which has reduced
delay. In futurepower utilization, area and also
delay can bereduced greatlybyusing various
adders in Carry Select Adder Architecture.
REFERENCES
[1] B.Ram KumarandHarish M
Kittur”LowPower and Area-
EfficientCarrySelectAdder”IEEETransaction
1063-8210 2011 IEEE
[2] Bedrij, O.J., (1962), “Carry-
selectadder,”IRETrans.Electron. Comput.,
pp.340–344.
[3] Ceiang, T.Y.andHsiao,
M.J.,(Oct1998),“Carry-selectadder using
singleripplecarryadder,”Electron.Lett.,vol.34](https://image.slidesharecdn.com/b045060813-140713012814-phpapp02/85/B045060813-5-320.jpg)
![Guru Dixit Chepuri et al Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 5( Version 6), May 2014, pp.08-13
www.ijera.com 13|P a g e
,no.22,pp.2101–2103
[4] He, Y., Chang, C.H.andGu,
J.,(2005),“AnAreaefficient64-bit square
rootcarry-selectadderforlow power
application,” inProc.IEEE
Int.Symp.CircuitsSyst.vol. 4,pp. 4082–4085.
[5] RamKumar, B.,Kittur,H.M.andKannan, P.
M.,(2010),“ASIC
implementationofmodifiedfastercarry
saveadder, Eur.J.Sci.Res”vol. 42, no.1,
pp.53–58.
[6] Kim, Y.andKim, L.-S., (May2001), “64-
bitcarry-selectadderwith reduced area,
ElectronLett” vol.37, no.10, pp.614–615.
[7] E. Abu-Shama andM. Bayoumi, “A New
cell forlow poweradders,”inProc.Int.Mid-
westSymp.CircuitsandSystems, 1995,
pp.1014–1017
[8] www.xilinx.com.
[9] Verilog HDL-DigitalDesign andSynthesis,
bySamirPalnitkar](https://image.slidesharecdn.com/b045060813-140713012814-phpapp02/85/B045060813-6-320.jpg)
B045060813
- 1. Guru Dixit Chepuri et al Int. Journal of Engineering Research and Applications www.ijera.com ISSN : 2248-9622, Vol. 4, Issue 5( Version 6), May 2014, pp.08-13 www.ijera.com 8|P a g e Design and Verification of Advanced Carry Select Adder Guru Dixit Chepuri, Murali Krishna M, J.Beatrice Seventline Master of Technology, VLSI Design, GITAM University, Visakhapatnam. Assistant Professor, ECE department, GITAM University, Visakhapatnam. Associate Professor, ECE Department, GITAM University, Visakhapatnam Abstract Design ofareaefficient data pathlogicsystems formsthelargestareasofresearch inVLSIsystem design.Indigital adders, thespeed of addition islimitedbythetimerequired totransmit a carrythroughtheadder.CarrySelectAdder (CSA) isoneofthefastestadders usedinmanydata-processingprocessorstoperform fastarithmetic functions. Fromthestructure oftheCSA,itisclear thatthereisscopeforreducing thearea and powerintheCSA. This work usesasimpleandefficient gate-level modification todrasticallyreducetheareaandpower oftheCSA.Basedonthismodification 16,32,64 and128-bitsquare-root CSA(SQRT CSA) architectureshavebeendevelopedandcomparedwith theregularSQRTCSAarchitecture. Theproposed designhasreducedarea and powerascompared withtheregular SQRTCSA.Thisworkestimates theperformanceof theproposed designsintermsofpower,areaand isimplementedusingXilinxISE and synthesized using cadence in 90nm technology. Keywords-CarrySelectAdder,Area, Power, SQRT. I. INTRODUCTION Inrapidly growingmobileindustry,fasterunitsarenottheonly concern butalso smaller areaand lesspowerbecome majorconcernsfordesignofdigitalcircuits.Inmobileelec tronics, reducing areaandpowerconsumptionarekeyfactorsin increasingportability andbatterylife.Eveninserversand desktopcomputers powerdissipationisanimportantdesign constraint.Designof areaandpower-efficienthigh- speeddata pathlogicsystemsare one of themostsubstantialareasof researchinVLSIsystem design.Indigitaladders,thespeedof additionislimitedby thetimerequiredtopropagateacarry through the adder. The sumfor each bit positionin an elementary adder is generated sequentially only after the previous bitpositionhas beensummedanda carry propagated intothe nextposition.Amongvariousadders,theCSA is intermediate regardingspeedandarea. Additionistheheartof computerarithmetic,and thearithmetic unitisoftentheworkhorseofacomputationalcircuit.They are thenecessarycomponentofadatapath,e.g.inmicroproce ssors orasignalprocessor.Therearemany waystodesignanadder. The Ripple Carry Adder(RCA) providesthe mostcompact designbut takeslongercomputingtime. If thereisN-bitRCA, thedelayislinearlyproportionaltoN.Thusforlargevalues of NtheRCAgiveshighestdelayofalladders.TheCarryLoo k- AheadAdder(CLA)givesfastresultsbutconsumeslargea rea. IfthereisN-bitadder,CLAisfastforN <4,butforlargevalues ofN bitsdelay increasesmorethanotheradders.Soforhigher numberof bits,CLAgiveshigherdelaythanotheraddersdueto presence of large numberoffan-inandalarge numberof logic gates.TheCarry SelectAdder(CSA)providesacompromise betweensmallareabutlongerdelay RCAandalargeareawith shorter delayCLA. In this paper the design of Modified CarrySelect-Adder (MCSA) and Uniform carry select adder (UCSA)architectures toreduce area andpowerwithminimum speedpenalty is described .TheMCSA and UCSA isdesignedby usingsingleRCAand Binary to Excess-1 Converter(BEC) and Carry skip adder (CSKA). II. BASICADDERBLOCK TheadderblockusingaRipplecarry adder, BECandMuxisexplainedinthissection. In this we calculate andexplainthedelay &areausingthe theoretical approachand showhowthedelayand areaaffectthe totalimplementation.The AND,OR, andInverter(AOI)implementationofanXORgate isshowninFig.1.Thedelay andareaevaluation methodology considersallgatesto bemadeupof AND,OR,andInverter,eachhavingdelayequalto1 unitandareaequalto 1unit.Wethenaddupthe numberofgatesinthelongestpathof alogicblock thatcontributesto themaximumdelay.Thearea RESEARCH ARTICLE OPEN ACCESS
- 2. Guru Dixit Chepuri et al Int. Journal of Engineering Research and Applications www.ijera.com ISSN : 2248-9622, Vol. 4, Issue 5( Version 6), May 2014, pp.08-13 www.ijera.com 9|P a g e evaluationisdone bycountingthe totalnumberof AOIgatesrequiredforeachlogicblock.Basedon thisapproach, theblocksof2:1mux,HalfAdder (HA),andFAareevaluatedandlistedinTableI. Fig. 1:DelayandArea evaluationofanXORgate. Fig.2:4-bBEC. The Booleanexpressionsof the4-bit BECis listedas(notethefunctionalsymbols~NOT,&AND, ^XOR) X0= ~B0 X1= B0^B1 X2= B2^(B0&B1) X3= B3^(B0&B1&B2) Fig.3:4-bBECwith8:4mux. Table 1: Delay and Area count of Basic Blocks of CSA Thebasic workistouseBinaryto Excess- 1Converter (BEC)insteadofRCAwithCin=1in theregularCSA toachievelowerareaandpower consumption. ThemainadvantageofthisBEClogic comes fromthelessernumber oflogic gatesthanthen- bit FullAdder(FA)structure.Asstatedabovethemainidea ofthisworkistouse BECinsteadoftheRCAwithCin=1 inordertoreducetheareaandpowerconsumptionofthe regularCSA. Toreplacethen-bitRCA,ann+1-bitBEC isrequired. Astructure and the function tableofa4-bit BECareshowninFig.2. III. BASICSTRUCTUREOF REGULAR16-BIT CSA A16-bitcarryselectaddercanbedeveloped intwodifferentsizesnamely uniformblocksizeand variableblocksize.Similarlya32,64and128-bit can alsobe developedintwomodesof different blocksizes.Ripple-carry addersarethesimplestand mostcompactfulladders,buttheirperformance is limitedbyacarrythatmustpropagatefromtheleast- significantbittothe most-significantbit.Thevarious 16,32,64and128-bitCSAcanalsobedeveloped byusingripplecarryadders.Thespeedofacarry- selectaddercanbeimprovedupto 40%to 90%,by performingthe additionsinparallel,andreducingthe maximum carrydelay. Fig. 4showstheRegularstructureof 16-bit SQRTCSA.Itincludesmanyripplecarryaddersof variablesizeswhicharedividedinto groups.Group0 contains2-bitRCAwhichcontainsonly oneripple carry adderwhichaddstheinputbitsandtheinput carry andresultstosum[1:0]andthecarry out.The carry outoftheGroup0whichactsastheselection inputto muxwhichisingroup1, selectstheresult fromthe correspondingRCA(Cin=0)orRCA (Cin=1).Similarly the remaininggroupswillbe selected dependingontheCout fromtheprevious groups. InRegularCSLA,thereisonly oneRCAto performtheadditionoftheleastsignificantbits[1:0]. The remainingbits(otherthanLSBs),the additionis performedby usingtwoRCAscorrespondingtothe one assumingacarry-inof0,theotheracarry-inof1
- 3. Guru Dixit Chepuri et al Int. Journal of Engineering Research and Applications www.ijera.com ISSN : 2248-9622, Vol. 4, Issue 5( Version 6), May 2014, pp.08-13 www.ijera.com 10|P a g e withinagroup.Inagroup,thereare twoRCAs that receivethesamedata inputsbutdifferentCin. The actualCinfromthepreceding sector selects one of the two RCAs. That is, as shown in Fig. 4, if the carry-in is 0, the sum and carry-out of the upper RCA is selected, and if the carry-in is 1, the sum and carry-out of lower RCA is selected. Fig.4:Regular16-bSQRTCSA. IV. BASIC STRUCTURE OFMODIFIED 16-BIT CSA This architectureissimilartoregular64-bit SQRTCSA,theonly changeisthat,wereplace RCAwithCin=1amongthetwoavailableRCAsin agroupwithaBEC. ThisBEChas afeaturethatit canperformthe similaroperationasthatofthe replaced RCA with Cin=1. Fig 6shows theModified blockdiagramof 16-bit SQRTCSA. The numberofbitsrequiredforBEClogicis1bit more than theRCAbits. The modified block diagramis alsodividedintovariousgroupsof variablesizesofbitswith each grouphavingthe ripplecarry adders, BEC andcorrespondingmux.The basic BEC is shown in Fig. 3. As showninthe Fig.5,Group0containoneRCA onlywhichis havinginputof lowersignificantbit andcarry inbitandproducesresultofsum [1:0] andcarryoutwhichisactingasmuxselectionlinefor thenextgroup, similarlytheprocedurecontinuesfor highergroupsbuttheyincludesBEClogicinsteadofRCA withCin=1.Basedontheconsiderationof delayvalues,thearrivaltimeofselectioninputC1 of8:3muxisearlierthanthesumofRCA andBEC. Forremaininggroupstheselectioninput arrivalis laterthantheRCA andBEC. Thus, thesum1andc1 (output from mux) dependson mux and results computed byRCAand BEC respectively. The sum2 depends on c1 and mux. For theremainingpartsthearrivaltimeof muxselection inputisalwaysgreaterthanthearrivaltimeof data inputsfromtheBEC’s.Thus,thedelay ofthe remainingMUXdependsonthearrivaltimeofmux selectioninputand themuxdelay.InthisModified CSA architecture, the implementation codeforFullAdderandMultiplexersof6:3,8:4,and10:5u p to24:11weredesigned.Thedesign codefor theBECwasdesignedby usingNOT,XORandAND gates.Then2, 3,4,5upto11-bitripplecarryadder wasdesigned. V. BASIC STRUCTURE OF UNIFORM16-BIT CSA InthisUCSLA,carryskipadder(CSKA)is usedforreducing delayand areacomparedwithregular and modified CSA.Theupperadderhas theCSKA withCin=0andtheBECcircuitisinthelower adderinsteadofRCAwithCin=1intheUCSA.The 16 bit UCSA architecture isshowninFig.7.The CSKA shown in Fig.5isusedtoreducethedelay comparedwithRCA.Thegroup1has onlyone set of4bitCSKAwithcarry-in signal.The carry- outoftheCSKA isusedas controlsignalin multiplexer.Thegroup2hasonesetof4bitCSKAwithCin =0 andonesetof5bitBECinsteadof4bitCSKAwithCin=1.
- 4. Guru Dixit Chepuri et al Int. Journal of Engineering Research and Applications www.ijera.com ISSN : 2248-9622, Vol. 4, Issue 5( Version 6), May 2014, pp.08-13 www.ijera.com 11|P a g e Fig 5: 4 bit CSKA Architecture VI. IMPLEMENTATION RESULTS Thedesignproposed inthispaperis developedusingVerilog-HDL inXilinx ISEandsynthesizedusing cadence in 90nm technology.Foreachwordsizeoftheadder, theVerilog code is dumped into cadence toperformthepowersimulations. The similardesign flowisfollowed forboththemodified and uniformSQRTCSA.Fig 8 exhibitsthesimulation resultsof16-bitCSA structures and Table 2 distinguish themin termsof Delay and Area. Fig.6: Modified16-bSQRT CSA – TheparallelRCAisreplacedwithBEC Fig.7: Uniform 16-bit SQRT CSA- The parallel RCA is replaced with BEC and CSKA
- 5. Guru Dixit Chepuri et al Int. Journal of Engineering Research and Applications www.ijera.com ISSN : 2248-9622, Vol. 4, Issue 5( Version 6), May 2014, pp.08-13 www.ijera.com 12|P a g e Fig. 8: 16-bit CSA output Waveform S.No . Adders Power (nw) Area (µm2 ) 1. 16–bit Regular 32803.4 652 Modified 31585.5 562 Uniform 29871.4 528 2. 32–bit Regular 69970.6 1356 Modified 63658.8 1156 Uniform 63108.8 1128 3. 64–bit Regular 143885.5 2805 Modified 131386.0 2387 Uniform 125165.7 2327 4. 128–bit Regular 311320.8 5719 Modified 276443.4 4844 Uniform 257825.0 4724 Table 2: Comparisons of Regular, Modified and Uniform CSA VII. CONCLUSION The synthesis and simulation of Regular Square Root Carry Select Adder(SQRTCSLA),ModifiedSquareRootCarry SelectAdder and Uniform Square Root Carry Select Adder wasdonein VerilogHardwareDescriptionLanguageusingXilinxIS Etool and Synthesis is done using Cadence.Acarry- selectadder is a particular way to implement anadder in which a logic element thatcomputesthe (n+1)bitsumoftwo n -bitnumbers and also replacing Ripple Carry Adder with Carry Skip Adder. Theapproachproposedinthisreport is toreducetheareaandpowerofSQRT CSLAarchitecture.Thereducednumberofgatesofthisw orkoffersgreatadvantage inthereductionofareaandtotalpower. But minimization of delay was not possible using the proposed architecture. The compared results show that the area and power of 128-bit Uniform SQRT CSLA are significantly reduced by 17.39% and 17.18% respectively. Similarly, the area and power of 128-bit Modified SQRT CSLA are significantly reduced by 15.29% and 11.20% respectively which indicates the success of the method for power and delay. The power-delay Product and Area-Delay Product of the proposed design varies for 16-, 32-, 64-, 128-bit sizes The Uniform SQRT CSLA Architecture is therefore low power, low area, simple and efficient for VLSI hardware implementation. It would be interesting to design a SQRT CSLA Architecture which has reduced delay. In futurepower utilization, area and also delay can bereduced greatlybyusing various adders in Carry Select Adder Architecture. REFERENCES [1] B.Ram KumarandHarish M Kittur”LowPower and Area- EfficientCarrySelectAdder”IEEETransaction 1063-8210 2011 IEEE [2] Bedrij, O.J., (1962), “Carry- selectadder,”IRETrans.Electron. Comput., pp.340–344. [3] Ceiang, T.Y.andHsiao, M.J.,(Oct1998),“Carry-selectadder using singleripplecarryadder,”Electron.Lett.,vol.34
- 6. Guru Dixit Chepuri et al Int. Journal of Engineering Research and Applications www.ijera.com ISSN : 2248-9622, Vol. 4, Issue 5( Version 6), May 2014, pp.08-13 www.ijera.com 13|P a g e ,no.22,pp.2101–2103 [4] He, Y., Chang, C.H.andGu, J.,(2005),“AnAreaefficient64-bit square rootcarry-selectadderforlow power application,” inProc.IEEE Int.Symp.CircuitsSyst.vol. 4,pp. 4082–4085. [5] RamKumar, B.,Kittur,H.M.andKannan, P. M.,(2010),“ASIC implementationofmodifiedfastercarry saveadder, Eur.J.Sci.Res”vol. 42, no.1, pp.53–58. [6] Kim, Y.andKim, L.-S., (May2001), “64- bitcarry-selectadderwith reduced area, ElectronLett” vol.37, no.10, pp.614–615. [7] E. Abu-Shama andM. Bayoumi, “A New cell forlow poweradders,”inProc.Int.Mid- westSymp.CircuitsandSystems, 1995, pp.1014–1017 [8] www.xilinx.com. [9] Verilog HDL-DigitalDesign andSynthesis, bySamirPalnitkar