Design and Reuse Panel
- 1. Design and Reuse Panel December 2011 Altera © 2010 Altera Corporation—Confidential
- 2. Semiconductor Tipping Point Technology challenges are bigger Performance vs. power trade-off Development complexity rising In a world that is continuously looking for Lower power Lower cost Faster time to market Lower risk and higher productivity © 2010 Altera Corporation—Confidential ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
- 3. What can 28nm Deliver with FPGA Highest Performance Up to 1 Million LEs (Equivalent) Hard IP PCI Express, ARM Processors, Memory Controllers High Performance I/O High Speed transceivers running at 28 Gbps 1067 MHz DDR3 DIMM Up to 53 Mbits of Memory Up to 40% power reductions Lower overall system costs Greater Productivity © 2010 Altera Corporation—Confidential ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. 3
- 4. Objectives To Meet Altera Solutions Strategy Expand protocol IP portfolio Develop IP in-house targeting key BU applications Rollout early for time-to- market Where valued, harden IP to hit cost/power /performance PCIe, HMCs, SOC Provide interoperability & ‘Complete Integrated standards certification for key Solution’ Ensures protocols Time to Market and Customer Success Utilize IP partners to fill-in gaps © 2010 Altera Corporation—Confidential ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. 4
- 5. Investing in Next-Generation Solutions… Wireline/ Industrial Broadcast Military CCSTM Wireless Automotive OTN, New Video Radar/EW, Computing, Video Ethernet IO Intelligence, Acceleration Surveillance, Aggregation, Standards, EO/IR, Imaging/ Analytics, RRU, Edge QAM, Secure Display Motion/Motor Backhaul Codecs Comms Control 40/100GbE, 40/100GbE, 1588, Mobile DDR, PCIe Gen3, DSPB Advanced Blockset 100G Interlaken PCIe Gen3/4, LPDDR2, DisplayPort, DSP IP 1588 & Sync-E, SFI-S, QDRIV, HDMI/DVI, DSP IP H.264/265 SerialLite II+ 100G E/GFEC 100G E/GFEC © 2010 Altera Corporation—Confidential ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. 5
- 6. Reaching the Tipping Point 130nm FPGA 40nm FPGA 40nm ASIC (Stratix) (Stratix IV) (HardCopy IV) 130nm ASIC 130nm ASIC Relative die size estimates based on design of approximately 4M logic gates and 8M bits of RAM © 2010 Altera Corporation—Confidential ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. 6
Editor's Notes
- #3: So what does this mean so far? The technology challenges are bigger. We in the semiconductor industry are having a harder time meeting the need for more performance while managing power consumption. All at the same time, we need to get to market faster, lower risk, and productivity for our customers.
- #6: Recall that this slide was used in the 2011 sales kick-off meeting; this slide was shown by the Business Units to illustrate the key application areas driving the next-generation technologies & requirements. These key application areas also drive the next generation protocol/interface IP requirements!!!Your input, feedback, and close calaboration with the Business Units & Product Planning defines the next generation IP & solutions roadmaps.