Boundary scan for support engineers and technicians
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The document provides a comprehensive overview of boundary scan (BSCAN) testing, emphasizing its application in verifying digital integrated circuits per IEEE standard 1149.1. It outlines the types of BSCAN tests, common failures, and troubleshooting tips, including potential causes and error messages for various failure scenarios. Additionally, it includes guidelines for effective BSCAN test execution and considerations for minimizing noise during tests.
Boundary scan for support engineers and technicians
- 2. Index •What is bscan. •Compile bscan test. •Types of bscan tests. •ECO •Debbug/Common Failures
- 3. What is bscan. • Boundary scan: Test technique of interconnections between IC pins as supported by IEEE Std 1149.1. • JTAG (JETAG): Joint Test Action Group/Joint European Test Action Group Refers to the group that start the standardization of Boundary scan. • IEEE 1149.1: This standard defines a test access port and boundary- scan architecture for digital integrated circuits and for the digital portions of mixed analog/digital integrated circuits.
- 9. What is bscan. TDO U1 Core Logic TAP TDI TDO … Instruction Reg … ID Code Reg. Bypass TMS TCK U2 Core Logic TAP TDI TDO … Instruction Reg … ID Code Reg Bypass U3 Core Logic TAP TDI … Instruction Reg … ID Code Reg. Bypass TDI … U4 Core Logic TAP TDI … Instruction Reg … ID Code Reg Bypass
- 10. BSCAN Test Files
- 11. ITL vs Digital
- 12. PCF ! D = Driver; B = Bidirectional; R = Receiver ! DDDDBBRRRR ! ---------- "000001HHHH" "0111HLLLHL" "00......LL" ! dot means "repeat state from previous line" ! - same as "0011HLLLLL" "1ZZ000HLXX"
- 13. sequential ! Test U1_U4 vector cycle 200n receive delay 100n assign TCK to nodes "TCK" assign TDI to nodes "TDI" assign TDO to nodes "TDO" assign TMS to nodes "TMS" family TTL !! Warning, Defaulted family inputs TCK inputs TMS inputs TDI outputs TDO pcf order default Scan is TCK, TMS, TDI, TDO !Column-to-Node Map, Nodes 1 to 4 ! unit "Scan_Test" ! Vector 1 pcf use pcf order Scan "01ZX" "11ZX" "01ZX" "11ZX" "01ZX" "11ZX" "01ZX" "11ZX" "01ZX" "11ZX"!Test-Logic-Reset "00ZX" "10ZX"!Run-Test/Idle "01ZX" "11ZX"!Select-DR-Scan "01ZX" "11ZX"!Select-IR-Scan "00ZX" "10ZX"!Capture-IR "00ZX" "10ZX"!Shift-IR
- 14. Types of Bscan Test • Integrity • Disable • Connect • Interconnect • Silicon Nails • Cover Extended
- 15. INTEGRITY Posibles Causas Agujas defectuosa. Voltaje no presente. Voltaje no regulado. Pines elevados. Resistencias no pobladas. ICs en la cadena no deshabilitados correctamente. Voltaje Incorrecto message "IEEE Std 1149.1-2001 Integrity Failure" message " Device #%IC120 has failed," message " suspect device or these pins:" message " (tck) 91" message " (tms) 90" message " (tdi) 94" message " (tdo) 95" It verifies that the chain is operable, and that the scan path is intact. This is done by verifying the two least significant bits of the Instruction Register, which are captured during the IR-CAPTURE state.
- 16. ID CODE Posibles Causas BSDL incorrecto Instrucción Erronea IC Incorrecto ECO Resistencias no pobladas. ICs en la cadena no deshabilitados correctamente. message "IEEE Std 1149.1-2001 IDCODE failure" message "in Device #%IC603, expecting:" message " 00001010111001001001000000011101"
- 17. DISABLE (ic603_dis.vcl) Posibles Causas BSDL incorrecto Instrucción Errónea Voltaje Incorrecto Pines elevados. Resistencias no pobladas. ICs en la cadena no deshabilitados correctamente. When a connect test is executed, only one device is tested at a time. If other devices in the chain have bussed pins that need to be disabled in order to test a pin of the selected device, the bussed devices will be issued the HIGHZ instruction, instead of the BYPASS instruction, to allow testing of the bussed pins.
- 18. CONNECT (ic603_connect_a) Posibles Causas HDD mas sensibles Voltaje Incorrecto Disable no colocado correctamente Unidades Programadas Resistencias no pobladas. ICs en la cadena no deshabilitados correctamente.
- 19. INTERCONNECT (ic120_ic603) Posibles Causas HDD mas sensibles Voltaje Incorrecto, Irregular Ground Plane Unidades Programadas Resistencias no pobladas. ICs en la cadena no deshabilitados correctamente.
- 20. SILICON NAILS Posibles Causas HDD mas sensibles Voltaje Incorrecto Unidades Programadas Resistencias no pobladas. ICs en la cadena no deshabilitados correctamente. u6 HAS FAILED SILICON NAIL FAILURE DETECTED FOR TEST Failing Vector #: 522 (message follows) Silicon Nail Test failed nailed output: Vector 3 of pre-serialized test. ----------------------------------------- Opens on Output or Bidir Pins U6.6 ----------------------------------------- A limitation of Silicon Nails testing is the low, real vector application rate to the DUT. For example, running TDI with a rate of 5 MHz through a chain of over 1,000 cells results in less than a 5 kHz real vector application rate. This can be a problem if you are testing dynamic components.
- 22. COVER EXTENDED
- 23. COVER EXTENDED GUIDELINES • Minimizing noise is the goal! • Use Agilent sensor plates (thicker) • Use snap-on ferrite on USB cable • Boundary scan tests must be 100% stable • VTEP tests must be 100% debugged • Use 07.20pd or newer software revision • Remove nailed nodes from the CET test to reduce noise (test nailed nodes w/ VTEP) • “verify all mux cards” to check VTEP, then power up CET mux card and “verify all CET cards” • If board has multiple identical connectors, retain probes for one connector to characterize the VTEP and boundary scan performance • Customize sensor plates for maximum coupling, remove unneeded copper
- 24. DEBUGG
- 25. ECO Cambio Conexión de Nodos Pull up, Pull down Pin queda desconectado Unidades Programadas Resistencias no pobladas. ICs en la cadena no deshabilitados correctamente. DUAL Core
- 26. COMMON FAILURES
- 27. COMMON FAILURES
- 28. COMMON FAILURES
- 29. COMMON FAILURES
- 30. COMMON FAILURES
- 33. PREGUNTAS
- 34. ¡Gracias!