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BRAINWARE UNIVERSITY
• Name:-arendra singh
• Student code:-(BWU/BEC/19/027)
• Department:-b-tech(ECE)
• Semester:-5THh
• Subject:-PCC-EC(502) COMPUTER ARCHITECTURE
• JDK SIR
Topic:-cache Coherence
cache coherence?
In a single cpu system ,two copies of same data (one in cache
and other in main memory) may become inconsistent
Contents of cache and main memory can be altered by more
than one device
Techniques For Cache coherence (single CPU)
for avoiding Cache coherence
1) write through:- when you update cache you have to update in main
memory at same time(it takes lots of acces time due to overhead
2) Write Block:- block of data can updated at time including block of
main memory and cache memory
3) Instruction cache:- in this the property of cache changed means:-
till now data is store but we built in different way they can direcly
store instruction
Cache coherence (in multiprocessor environment)
for avoiding Cache coherence
1)Sharing of writeable data
2) Process migration
3)i/o activity
p1 p2
X
x
p1 p2 p1
x
x
X`
X`
x
x`
p2
x
1) Sharing of writeable data
Processors
cache
Shared memory
Before update Write through Write block
p1 p2
X
x
p1 p2 p1
x
x
X`
X`
x
x`
p2
x
2) Process migration
Processors
cache
Shared memory
Before update Write through Write block
p1 p2
x
p1 p2 p1
x
x
X`
X`
X`
x
p2
x
3) i/o activity
Processors
cache
Shared memory
Before update Write through Write block
x
x
x
i/o processor
Cache coherence ppt
Software solution
#𝑃𝑟𝑜𝑏𝑙𝑒𝑚 𝑖𝑠 𝑀𝑎𝑛𝑎𝑔𝑒𝑑 𝐶𝑜𝑚𝑝𝑙𝑒𝑡𝑒𝑙𝑦 𝑏𝑦 𝐶𝑜𝑚𝑝𝑖𝑙𝑒𝑟 𝑎𝑛𝑑 𝑜𝑠
#𝑁𝑜 𝑎𝑑𝑑𝑖𝑡𝑖𝑜𝑛𝑎𝑙 𝑐𝑖𝑟𝑐𝑢𝑖𝑡
# 𝑖𝑛 𝑇ℎ𝑖𝑠 𝐴𝑝𝑝𝑟𝑜𝑎𝑐ℎ 𝐶𝑜𝑚𝑝𝑖𝑙𝑒𝑟 𝑀𝑎𝑟𝑘 𝑡ℎ𝑒 𝑑𝑎𝑡𝑎 𝑤ℎ𝑖𝑐ℎ 𝑎𝑟𝑒
𝑙𝑖𝑘𝑒𝑙𝑦 𝑡𝑜 𝑏𝑒 𝑐ℎ𝑎𝑛𝑔𝑒𝑑 𝑎𝑛𝑑
os keeps away from cache
#𝑃𝑟𝑒𝑣𝑒𝑛𝑡 𝑐ℎ𝑎𝑛𝑒𝑎𝑏𝑙𝑒 𝐷𝑎𝑡𝑎 𝐹𝑟𝑜𝑚 𝑏𝑒𝑖𝑛𝑔 𝑐𝑎𝑐ℎ𝑒
1 Safe Period
2 Critical Period
Hardware solution
# 𝑅𝑒𝑓𝑒𝑟𝑟𝑒𝑑 𝑔𝑒𝑛𝑒𝑟𝑎𝑙𝑙𝑦 𝑎𝑠 𝑐𝑜ℎ𝑒𝑟𝑒𝑛𝑐𝑒 𝑝𝑟𝑜𝑡𝑜𝑐𝑜𝑙
#𝐷𝑦𝑛𝑎𝑚𝑖𝑐𝑎𝑙𝑙𝑦 ℎ𝑎𝑛𝑑𝑙𝑒𝑑 𝑜𝑛 𝑟𝑢𝑛𝑡𝑖𝑚𝑒
# 𝑀𝑜𝑟𝑒 𝑒𝑓𝑓𝑒𝑐𝑡𝑖𝑣𝑒 𝑈𝑡𝑖𝑙𝑖𝑧𝑎𝑡𝑖𝑜𝑛
1)Snoopy Protocols
2)Directory Protocols
Cache coherence ppt
Snoopy Protocols
# 𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓𝑝𝑟𝑜𝑐𝑠𝑠𝑜𝑟 𝑐𝑜𝑛𝑛𝑒𝑐𝑡𝑒𝑑 𝑡𝑜 𝑎 𝑐𝑜𝑚𝑚𝑜𝑛 𝑏𝑢𝑠 𝑎𝑛𝑑 𝑒𝑎𝑐ℎ ℎ𝑎𝑠
𝑜𝑤𝑛 𝑙𝑜𝑐𝑎𝑙 𝑐𝑎𝑐ℎ𝑒
#𝑃𝑜𝑙𝑖𝑐𝑖𝑒𝑠 𝑈𝑠𝑒𝑑
1 Write-invalidate
2 Write Update policy
Directory Protocols
# 𝑀𝑎𝑖𝑛𝑡𝑎𝑖𝑛𝑠 𝑖𝑛𝑓𝑜 𝑤ℎ𝑒𝑟𝑒 𝑐𝑜𝑝𝑖𝑒𝑠 𝑜𝑓 𝑏𝑙𝑜𝑐𝑘 𝑟𝑒𝑠𝑖𝑑𝑒
# 𝐶𝑎𝑛 𝑏𝑒 𝑐𝑒𝑡𝑟𝑎𝑙𝑖𝑧𝑒𝑑 𝑜𝑟 𝑑𝑖𝑠𝑡𝑟𝑖𝑏𝑢𝑡𝑒𝑑
# 𝑇ℎ𝑒𝑟𝑒 𝑖𝑠 𝑐𝑒𝑛𝑡𝑟𝑎𝑙𝑖𝑧𝑒𝑑 𝑐𝑜𝑛𝑡𝑟𝑜𝑙𝑙𝑒𝑟
# 𝐶𝑒𝑛𝑡𝑟𝑎𝑙 𝑏𝑜𝑡𝑡𝑒𝑙𝑛𝑒𝑐𝑘 𝑠𝑢𝑓𝑓𝑒𝑟𝑒𝑑
# 𝐴𝑑𝑑𝑖𝑡𝑖𝑜𝑛𝑎𝑙 𝑜𝑣𝑒𝑟ℎ𝑒𝑎𝑑 𝑑𝑢𝑒 𝑡𝑜 𝑐𝑜𝑚𝑚𝑢𝑛𝑖𝑐𝑎𝑡𝑖𝑜𝑛
# 𝐸𝑓𝑒𝑐𝑡𝑖𝑣𝑒 𝑖𝑛 𝑙𝑎𝑟𝑔𝑒 𝑠𝑐𝑎𝑙𝑒 𝑆𝑦𝑠𝑡𝑒𝑚
Cache coherence ppt

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Cache coherence ppt

  • 1. BRAINWARE UNIVERSITY • Name:-arendra singh • Student code:-(BWU/BEC/19/027) • Department:-b-tech(ECE) • Semester:-5THh • Subject:-PCC-EC(502) COMPUTER ARCHITECTURE • JDK SIR Topic:-cache Coherence
  • 2. cache coherence? In a single cpu system ,two copies of same data (one in cache and other in main memory) may become inconsistent Contents of cache and main memory can be altered by more than one device
  • 3. Techniques For Cache coherence (single CPU) for avoiding Cache coherence 1) write through:- when you update cache you have to update in main memory at same time(it takes lots of acces time due to overhead 2) Write Block:- block of data can updated at time including block of main memory and cache memory 3) Instruction cache:- in this the property of cache changed means:- till now data is store but we built in different way they can direcly store instruction
  • 4. Cache coherence (in multiprocessor environment) for avoiding Cache coherence 1)Sharing of writeable data 2) Process migration 3)i/o activity
  • 5. p1 p2 X x p1 p2 p1 x x X` X` x x` p2 x 1) Sharing of writeable data Processors cache Shared memory Before update Write through Write block
  • 6. p1 p2 X x p1 p2 p1 x x X` X` x x` p2 x 2) Process migration Processors cache Shared memory Before update Write through Write block
  • 7. p1 p2 x p1 p2 p1 x x X` X` X` x p2 x 3) i/o activity Processors cache Shared memory Before update Write through Write block x x x i/o processor
  • 9. Software solution #𝑃𝑟𝑜𝑏𝑙𝑒𝑚 𝑖𝑠 𝑀𝑎𝑛𝑎𝑔𝑒𝑑 𝐶𝑜𝑚𝑝𝑙𝑒𝑡𝑒𝑙𝑦 𝑏𝑦 𝐶𝑜𝑚𝑝𝑖𝑙𝑒𝑟 𝑎𝑛𝑑 𝑜𝑠 #𝑁𝑜 𝑎𝑑𝑑𝑖𝑡𝑖𝑜𝑛𝑎𝑙 𝑐𝑖𝑟𝑐𝑢𝑖𝑡 # 𝑖𝑛 𝑇ℎ𝑖𝑠 𝐴𝑝𝑝𝑟𝑜𝑎𝑐ℎ 𝐶𝑜𝑚𝑝𝑖𝑙𝑒𝑟 𝑀𝑎𝑟𝑘 𝑡ℎ𝑒 𝑑𝑎𝑡𝑎 𝑤ℎ𝑖𝑐ℎ 𝑎𝑟𝑒 𝑙𝑖𝑘𝑒𝑙𝑦 𝑡𝑜 𝑏𝑒 𝑐ℎ𝑎𝑛𝑔𝑒𝑑 𝑎𝑛𝑑 os keeps away from cache #𝑃𝑟𝑒𝑣𝑒𝑛𝑡 𝑐ℎ𝑎𝑛𝑒𝑎𝑏𝑙𝑒 𝐷𝑎𝑡𝑎 𝐹𝑟𝑜𝑚 𝑏𝑒𝑖𝑛𝑔 𝑐𝑎𝑐ℎ𝑒 1 Safe Period 2 Critical Period
  • 10. Hardware solution # 𝑅𝑒𝑓𝑒𝑟𝑟𝑒𝑑 𝑔𝑒𝑛𝑒𝑟𝑎𝑙𝑙𝑦 𝑎𝑠 𝑐𝑜ℎ𝑒𝑟𝑒𝑛𝑐𝑒 𝑝𝑟𝑜𝑡𝑜𝑐𝑜𝑙 #𝐷𝑦𝑛𝑎𝑚𝑖𝑐𝑎𝑙𝑙𝑦 ℎ𝑎𝑛𝑑𝑙𝑒𝑑 𝑜𝑛 𝑟𝑢𝑛𝑡𝑖𝑚𝑒 # 𝑀𝑜𝑟𝑒 𝑒𝑓𝑓𝑒𝑐𝑡𝑖𝑣𝑒 𝑈𝑡𝑖𝑙𝑖𝑧𝑎𝑡𝑖𝑜𝑛 1)Snoopy Protocols 2)Directory Protocols
  • 12. Snoopy Protocols # 𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓𝑝𝑟𝑜𝑐𝑠𝑠𝑜𝑟 𝑐𝑜𝑛𝑛𝑒𝑐𝑡𝑒𝑑 𝑡𝑜 𝑎 𝑐𝑜𝑚𝑚𝑜𝑛 𝑏𝑢𝑠 𝑎𝑛𝑑 𝑒𝑎𝑐ℎ ℎ𝑎𝑠 𝑜𝑤𝑛 𝑙𝑜𝑐𝑎𝑙 𝑐𝑎𝑐ℎ𝑒 #𝑃𝑜𝑙𝑖𝑐𝑖𝑒𝑠 𝑈𝑠𝑒𝑑 1 Write-invalidate 2 Write Update policy
  • 13. Directory Protocols # 𝑀𝑎𝑖𝑛𝑡𝑎𝑖𝑛𝑠 𝑖𝑛𝑓𝑜 𝑤ℎ𝑒𝑟𝑒 𝑐𝑜𝑝𝑖𝑒𝑠 𝑜𝑓 𝑏𝑙𝑜𝑐𝑘 𝑟𝑒𝑠𝑖𝑑𝑒 # 𝐶𝑎𝑛 𝑏𝑒 𝑐𝑒𝑡𝑟𝑎𝑙𝑖𝑧𝑒𝑑 𝑜𝑟 𝑑𝑖𝑠𝑡𝑟𝑖𝑏𝑢𝑡𝑒𝑑 # 𝑇ℎ𝑒𝑟𝑒 𝑖𝑠 𝑐𝑒𝑛𝑡𝑟𝑎𝑙𝑖𝑧𝑒𝑑 𝑐𝑜𝑛𝑡𝑟𝑜𝑙𝑙𝑒𝑟 # 𝐶𝑒𝑛𝑡𝑟𝑎𝑙 𝑏𝑜𝑡𝑡𝑒𝑙𝑛𝑒𝑐𝑘 𝑠𝑢𝑓𝑓𝑒𝑟𝑒𝑑 # 𝐴𝑑𝑑𝑖𝑡𝑖𝑜𝑛𝑎𝑙 𝑜𝑣𝑒𝑟ℎ𝑒𝑎𝑑 𝑑𝑢𝑒 𝑡𝑜 𝑐𝑜𝑚𝑚𝑢𝑛𝑖𝑐𝑎𝑡𝑖𝑜𝑛 # 𝐸𝑓𝑒𝑐𝑡𝑖𝑣𝑒 𝑖𝑛 𝑙𝑎𝑟𝑔𝑒 𝑠𝑐𝑎𝑙𝑒 𝑆𝑦𝑠𝑡𝑒𝑚