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Cache Memory from Computer Architecture.ppt
- 2. Location • CPU • Internal • External
- 3. Memory Hierarchy • Registers —In CPU • Internal or Main memory —May include one or more levels of cache —“RAM” • External memory —Backing store
- 4. Memory Hierarchy - Diagram
- 5. Performance • Access time —Time between presenting the address and getting the valid data • Memory Cycle time —Time may be required for the memory to “recover” before next access —Cycle time is access + recovery • Transfer Rate —Rate at which data can be moved
- 6. Hierarchy List • Registers • L1 Cache • L2 Cache • Main memory • Disk cache • Disk • Optical • Tape
- 7. Cache • Small amount of fast memory • Sits between normal main memory and CPU • May be located on CPU chip or module
- 8. Cache and Main Memory
- 10. Cache operation – overview • CPU requests contents of memory location • Check cache for this data • If present, get from cache (fast) • If not present, read required block from main memory to cache • Then deliver from cache to CPU • Cache includes tags to identify which block of main memory is in each cache slot
- 11. Cache Read Operation - Flowchart
- 12. Cache Addressing • Where does cache sit? —Between processor and virtual memory management unit —Between MMU and main memory • Logical cache (virtual cache) stores data using virtual addresses —Processor accesses cache directly, not thorough physical cache —Cache access faster, before MMU address translation —Virtual addresses use same address space for different applications – Must flush cache on each context switch • Physical cache stores data using main memory physical addresses
- 13. Mapping Function • Cache of 64kByte • Cache block of 4 bytes —i.e. cache is 16k (214 ) lines of 4 bytes • 16MBytes main memory • 24 bit address —(224 =16M)
- 14. Direct Mapping • Each block of main memory maps to only one cache line —i.e. if a block is in cache, it must be in one specific place • Address is in two parts • Least Significant w bits identify unique word • Most Significant s bits specify one memory block • The MSBs are split into a cache line field r and a tag of s-r (most significant)
- 15. Direct Mapping Address Structure Tag s-r Line or Slot r Word w 8 14 2 • 24 bit address • 2 bit word identifier (4 byte block) • 22 bit block identifier — 8 bit tag (=22-14) — 14 bit slot or line • No two blocks in the same line have the same Tag field • Check contents of cache by finding line and checking Tag
- 16. Direct Mapping from Cache to Main Memory
- 17. Direct Mapping Cache Line Table Cache line Main Memory blocks held 0 0, m, 2m, 3m…2s-m 1 1,m+1, 2m+1…2s-m+1 … m-1 m-1, 2m-1,3m-1…2s-1
- 18. Direct Mapping Cache Organization
- 19. Direct Mapping Summary • Address length = (s + w) bits • Number of addressable units = 2s+w words or bytes • Block size = line size = 2w words or bytes • Number of blocks in main memory = 2s+ w /2w = 2s • Number of lines in cache = m = 2r • Size of tag = (s – r) bits
- 20. Direct Mapping pros & cons • Simple • Inexpensive • Fixed location for given block —If a program accesses 2 blocks that map to the same line repeatedly, cache misses are very high
- 21. Associative Mapping • A main memory block can load into any line of cache • Memory address is interpreted as tag and word • Tag uniquely identifies block of memory • Every line’s tag is examined for a match • Cache searching gets expensive
- 22. Associative Mapping from Cache to Main Memory
- 23. Fully Associative Cache Organization
- 24. Tag 22 bit Word 2 bit Associative Mapping Address Structure • 22 bit tag stored with each 32 bit block of data • Compare tag field with tag entry in cache to check for hit • Least significant 2 bits of address identify which 16 bit word is required from 32 bit data block • e.g. —Address Tag Data Cache line —FFFFFC FFFFFC24682468 3FFF
- 25. Associative Mapping Summary • Address length = (s + w) bits • Number of addressable units = 2s+w words or bytes • Block size = line size = 2w words or bytes • Number of blocks in main memory = 2s+ w /2w = 2s • Number of lines in cache = undetermined • Size of tag = s bits
- 26. Set Associative Mapping • Cache is divided into a number of sets • Each set contains a number of lines • A given block maps to any line in a given set —e.g. Block B can be in any line of set i • e.g. 2 lines per set —2 way associative mapping —A given block can be in one of 2 lines in only one set
- 27. Set Associative Mapping Example • 13 bit set number • Block number in main memory is modulo 213 • 000000, 00A000, 00B000, 00C000 … map to same set
- 28. Mapping From Main Memory to Cache: v Associative
- 29. Mapping From Main Memory to Cache: k-way Associative
- 30. K-Way Set Associative Cache Organization
- 31. Set Associative Mapping Address Structure • Use set field to determine cache set to look in • Compare tag field to see if we have a hit • e.g —Address Tag Data Set number —1FF 7FFC 1FF 12345678 1FFF —001 7FFC 001 11223344 1FFF Tag 9 bit Set 13 bit Word 2 bit
- 32. Set Associative Mapping Summary • Address length = (s + w) bits • Number of addressable units = 2s+w words or bytes • Block size = line size = 2w words or bytes • Number of blocks in main memory = 2d • Number of lines in set = k • Number of sets = v = 2d • Number of lines in cache = kv = k * 2d • Size of tag = (s – d) bits
- 33. Replacement Algorithms (1) Direct mapping • No choice • Each block only maps to one line • Replace that line
- 34. Replacement Algorithms (2) Associative & Set Associative • Hardware implemented algorithm (speed) • Least Recently used (LRU) • e.g. in 2 way set associative —Which of the 2 block is lru? • First in first out (FIFO) —replace block that has been in cache longest • Least frequently used —replace block which has had fewest hits • Random
- 35. Write Policy • Must not overwrite a cache block unless main memory is up to date • Multiple CPUs may have individual caches • I/O may address main memory directly
- 36. Write through • All writes go to main memory as well as cache • Multiple CPUs can monitor main memory traffic to keep local (to CPU) cache up to date • Lots of traffic • Slows down writes • Remember bogus write through caches!
- 37. Write back • Updates initially made in cache only • Update bit for cache slot is set when update occurs • If block is to be replaced, write to main memory only if update bit is set • Other caches get out of sync • I/O must access main memory through cache • N.B. 15% of memory references are writes
- 38. Multilevel Caches • High logic density enables caches on chip —Faster than bus access —Frees bus for other transfers • Common to use both on and off chip cache —L1 on chip, L2 off chip in static RAM —L2 access much faster than DRAM or ROM —L2 often uses separate data path —L2 may now be on chip —Resulting in L3 cache – Bus access or now on chip…
- 39. Unified v Split Caches • One cache for data and instructions or two, one for data and one for instructions • Advantages of unified cache —Higher hit rate – Balances load of instruction and data fetch – Only one cache to design & implement • Advantages of split cache —Eliminates cache contention between instruction fetch/decode unit and execution unit – Important in pipelining