Chap2 comp architecture
- 2. Introduction Central processing unit Communication among various units
- 4. Referred as brain of a computer Converts data(input) to information (output) Complex, exclusive set of electronic circuitry which executes stored program instructions. Performs arithmetic and logical operations Operates only on binary data, composed of 0’s and 1’s Controls the usage of main memory to store data and instructions Controls sequence of the operations.
- 5. CPU consists of three main subsystems ALU CU Registers Arithmetic logic unit It contains electronic circuitry to execute arithmetic and logical operations on the data available to it.
- 6. ALU comprises of two things Arithmetic unit Logic unit Arithmetic unit Performs actual computing carrying out arithmetic calculations. Such as addition, subtraction, multiplication and division Performs them at a very high speed.
- 7. Logic unit Performs logical operations based on the instructions provided to it Logical comparisons between the data items It compares numbers, letters and special characters Takes actions based on the result of comparison. Three conditions: ▪ Equal-to condition ▪ Less than condition ▪ Greater than condition
- 8. ALU compares two values to determine if they are equal Eg: no of tickets sold equals to the number of the seats in the cinema hall, then houseful is declared.
- 9. ALU compares the value to determine if one is less than the other Eg: if a person purchases less than two tickets then no discount rate is given.
- 10. The computer determines if one of the value is greater than the other. If person purchases greater than two tickets, he gets a discount of 5% on ticket.
- 11. Are special purpose , high speed temporary memory units. They hold various types of data and information , instructions , addresses and intermediate results of calculations. They offer extra space for the computer hence speeds up the computer in calculations.
- 12. The registers work under the direction of CU to accept, hold and transfer the instruction or data and perform arithmetic or logical operations at high speed. When one instruction finishes its execution, next execution will be ready in a register called program counter
- 14. Register name Function Program Counter (PC) The PC keeps track of the next instruction to be executed Instruction Register (IR) Holds the instruction to be decoded by the CPU Memory Address Register (MAR) Holds the address of next location in the memory to be accessed. Memory Buffer Register(MBR) Used to store data either coming to CPU or data being transferred by CPU Accumulator(ACC) General purpose register used to store the temporary results and results produced by ALU Data register (DR) The DR is used to store the operands and other data.
- 15. Instructions are normally stored in the consecutive registers and are executed sequentially. CU reads an instruction from the memory by a specific address in the registers and executes it. The next instruction is fetched from a sequence and executed and so on.
- 16. It contains circuitry that uses electrical signals to direct the entire computer system to carry out, or execute , stored program instructions. It does not execute the program instructions, it directs other parts of the system to do so by communicating both ALU and memory. Controls the I/O devices and transfer of data to and from the primary storage. CU itself is controlled by the programs located in main memory. CU decides which action will occur at which time. Following figure illustrates how the CU instructs other parts of CPU.
- 18. A bus is a set of connections between two or more components / devices which are designed for transfer several . All bits of word from the source to destination. A bus contains multiple paths, which are also termed as lines, and each line is capable of transferring one bit at a time. To transfer 8 bit at a time, eight lines are required.
- 19. A bus can be unidirectional or bi-directional. In shared bus, only one source can transmit data at one time, while one or more than one can receive that signal. A bus that connects three components i.e. CPU, memory and I/O devices is called system bus. A system bus contains of 50-100 separate lines They are categorized into three groups. Data lines Address lines Control lines
- 22. Data lines They provide path for moving data between the system modules. Data lines are collectively known as data bus. Consists of 8,16,32 separate lines No. of lines in a data bus is called the width of the data bus. The width of the data bus determines the performance of a computer system.
- 23. Address lines It designates the source of data for a data bus. Memory is divided into a linear array of bytes or words, for reading or writing any information on to memory The CPU needs to specify the address of a particular location. This is supplied by the address bus. Width of address bus specifies the maximum possible memory supported by the system.
- 24. Control lines Used to control the access to data and the address bus Control lines are collectively are called control bus. Used for transmission of commands and timing signals between the system modules. Timing signals indicate whether data and address information is valid Command signals specify which operations are to be performed. Used to reading/writing to I/O devices or the memory.
- 25. Its an integral part of the CPU, it is separately placed on the computer’s mother board Memory stores the data and programs as long as the program requires it for the operations. CPU access the memory in random manner. Two types: Random Access Memory (RAM) Read Only Memory (ROM)
- 26. provides the required information to the processor It is a block of sequential memory locations each of them having a unique memory address and those locations having a data element. It is volatile in nature, data remains as long as power is switched on, it is lost when the power supply is broken.
- 27. Stores the initial start-up instructions and routines in Basic Input / Output System (BIOS) which can be read only the CPU , each time the system is on. Data is not volatile in nature The instructions built in ROM are built into the electronic circuits of the chip called the firmware. Different kinds of ROM are available Programmable Read Only Memory (PROM) Erasable Programmable Read Only Memory (EPROM) Electrically Erasable Programmable Read Only Memory (EEPROM)
- 28. Very high speed , expensive piece of memory, used to speed up the memory retrieval process. Without cache, very request from the CPU to access the data would have been sent to main memory, then the response is sent on the system bus This slows the process in computing terms Cache will store the frequently accessed data and data that are around it, helps in achieving a quicker response time.
- 30. The computer uses the logic to find out which data are frequently accessed and keeps them in cache. Cache is categorized into three levels L1 cache L2 cache L3 cache
- 31. Closest to the processor, hence termed as primary or L1 cache. Each time the processor requests for a data, the cache controller on the chip uses a special circuitry to first check whether the requested data is already present in the cache. Cache ranges in size from 8 to 64 KB, with larger amounts on a new processors It is fast because it is integrated into the processor. Two different ways that a processor can organize its primary cache Unified cache- a single cache for both command instructions and program data Spilt cache- separate cache for instruction and data.
- 32. This cache is larger but slower than L1 cache. Used to see the recent accesses that is not picked by the L1 cache Usually 64 to 2MB in size. L1 and L2 can be used together, missing data can be retrieved from L2 cache.
- 33. Presented on the motherboard of the computer Present in between the main memory and the processor. Reduces the time gap between the request and retrieval of the data and instructions Hence accesses the data faster than main memory. Ranges more than 3MB
- 34. All units of the computer system, work conjunction with each other to formulate a function computer system. To have a proper coordination among these units , a reliable and robust means of communication is required. Processor to memory communication Processor-I/O devices communication
- 36. The entire process between processor and a memory can be divided into two steps. Information transfer from the memory to the processor Writing information in the memory Information transfer Steps The processor places the address in the MAR through the address bus The process issues a READ command through the control bus. The memory places required data on the data bus, which are then transferred to the processor.
- 37. Information written into the memory The processor places the address into the MAR through address bus The processor places the data to be written in the memory on the data bus. The processor issues a WRITE command to the memory on the data bus The data are written In the memory at the address specified in the MAR
- 38. The main concern in the processor –memory communication is the speed mismatch between the memory and the processor. The memory speed is slower than the CPU’s speed CPU is forced to wait for the data. This reduced by using a small fast memory called the cache between processor and memory.
- 39. All the I/O devices are connected via system bus Each device in a computer system is first met with the controller called the Direct Memory Access (DMA) controller, which controls the operation of that device. DMA is capable of taking over the system bus from the CPU DMA can access the memory directly and used to transfer data to and from the one memory location to another.
- 41. DMA can use the system bus only when the CPU does not require it or it should suspend the operations currently being processed by the CPU. With a DMA controller, a dedicated data transfer device reads the incoming data from a device and stores that data in a system memory buffer for later retrieval by the CPU. The DMA controller allows the peripheral devices to access the memory for both read and write operations without affecting the current state of computer’s central processor.
- 42. When a large amount of data is to be transferred from the CPU, the DMA controller to be used. The DMA controller allows the I/O unit of exchange data directly with the memory without going through CPU except at the beginning (to issue the command) and at the end (to clean up the command) While I/O operation is being performed by the DMA controller, the CPU can start the execution of the some other part of the same program or can start executing some other program. Thus, DMA speeds up the speed of the I/O operations by taking over the buses and eliminating CPU interventions