「づや会 vol3 ~AWSの話~」登壇時の資料です。EC2で自宅サーバと同じスペックでサーバを立てたらどれくらいの運用費用がかかるか、EC2の料金体系をひも解きながら考えてみました。
※イメージ写真としてCC表示3.0ライセンスのFile:A view of the server room at The National Archives.jpg - Wikimedia Commonsを使用しています。
ブログで更に詳しい情報を掲載しています:
http://media-massage.net/works/docs/aws_as_a_home_server/
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CreativeCommons Attribution-NonCommercial 4.0 International
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Rosserial無線化への招待 〜Invitation to wirelessization by rosserial〜Tatsuya Fukuta
ESP32(Arduino互換機)を使ってrosserialの無線化に挑戦した。TCP/IPを使ったシリアルプロトコルであるため仮想化技術(DockerやVirtual Machine)との相性が非常に良い。
I tried wirelessization of rosserial using ESP 32 (Arduino compatible machine). Since it is a serial protocol using TCP / IP, it is very compatible with virtualization technology (Docker and Virtual Machine).
Rosserial無線化への招待 〜Invitation to wirelessization by rosserial〜Tatsuya Fukuta
ESP32(Arduino互換機)を使ってrosserialの無線化に挑戦した。TCP/IPを使ったシリアルプロトコルであるため仮想化技術(DockerやVirtual Machine)との相性が非常に良い。
I tried wirelessization of rosserial using ESP 32 (Arduino compatible machine). Since it is a serial protocol using TCP / IP, it is very compatible with virtualization technology (Docker and Virtual Machine).
The document discusses Twitter and GitHub accounts, an IPSJ conference, and hardware including an Intel Core i7, FPGA boards from Digilent and ScalableCore, and code snippets for C programs and hardware designs including for a convolutional neural network layer.
Pythonによるカスタム可能な高位設計技術 (Design Solution Forum 2016@新横浜)Shinya Takamaeda-Y
Veriloggen is a Python library that allows users to generate Verilog HDL code from Python. It provides objects and methods to define RTL modules in Python, including module inputs/outputs, registers, assignments, always blocks, etc. When the Veriloggen object is passed to the to_verilog() method, it traverses the object and generates equivalent Verilog HDL code. This allows rapid prototyping of RTL designs in Python without having to write low-level Verilog code directly.
A Random Forest using a Multi-valued Decision Diagram on an FPGaHiroki Nakahara
The ISMVL (Int'l Symp. on Multiple-Valued Logic) presentation slide on May, 22nd, 2017 at Novi Sad, Serbia. It is a kind of machine learning to realize a high-performance and low power.