CSN221_Lec_4.pdf Computer Organization & Architecture

Jun 25, 20240 likes10 views

ssuser034ce1

Computer Organization, CPU Structure and Functions (Lecture - 4

Course Website: http://faculty.iitr.ac.in/~sudiproy.fcs/csn221_2015.html
Piazza Site: https://piazza.com/iitr.ac.in/fall2015/csn221
Dr. Sudip Roy
CSN‐221: COMPUTER ARCHITECTURE
AND MICROPROCESSORS
Computer Organization, CPU Structure and Functions
(Lecture - 4)

What does a processor work?
• The CPU must be designed to accommodate the instructions and data to be
processed
Dr. Sudip Roy 2
System Bus
System Bus
Control
Bus
Data
Bus
Address
Bus
I/O 1
CPU RAM
I/O 2
ALU
CU
Regs
PC
PSW
IR
Internal
CPU Bus
I/O n
Main
Memory
(RAM)

CPU Structure and Functions:
• What CPU does?
1. Fetch instructions
2. Interpret (decode) instructions
3. Fetch data
4. Process data
5. Write data
Dr. Sudip Roy 3

CPU Internal Structure (Processor Organization):
Dr. Sudip Roy 4

Internal Registers:
• Working space (temporary storage) of processor
• Called registers
• Number and function vary between processor designs
• One of the major design decisions
• Top level of memory hierarchy
• The registers in the CPU perform two roles:
 User‐visible registers: assembly‐language programmer can minimize the
main memory referencing by optimizing the use of registers
 Control and status registers: Used by the control unit to control the operation
of the CPU
Dr. Sudip Roy 5

Internal Registers:
• User‐visible registers:
1. General Purpose registers: (between 8 – 32 in number) FP register, stack
operation register
2. Data registers: Only to hold data, Often possible to combine two data registers
(e.g., double int a; long int a;)
3. Address registers: To hold address, like Segment Register, Stack Pointer
4. Condition Codes: Holds flag values of the result, like +ve, ‐ve, zero or overflow
Dr. Sudip Roy 6

Internal Registers:
• Control and Status registers:
1. Program Counter (PC): Contains address of an instruction to be fetched
2. Instruction Register (IR): Contains the instruction most recently fetched
3. Memory Address Register (MAR): Contains the address of a location in memory
4. Memory Buffer Register (MBR): Contains the data to be written to the memory or data
most recently read
• Program Status Word (PSW): A set of bits, Includes Condition Codes, Common fields are:
• Sign: A sign bit of the last arithmetic operation
• Zero: A bit set when the result is zero
• Carry: Set if an operation resulted in a carry (addition) or a borrow (subtraction) out of a high‐
order bit
• Equal: Set if a logical compare result is equality
• Overflow: To indicate arithmetic overflow
• Interrupt enable/disable: To enable/disable interrupt
• Supervisor: To indicate whether the CPU is executing in supervisor or user mode
Dr. Sudip Roy 7

Datapath and Control:
• Datapath:
• Memory, registers, adders, ALU, and communication buses
• Each step (fetch, decode, execute, save result) requires communication (data
transfer) paths between memory, registers and ALU
• Control:
• Datapath for each step is set up by control signals that set up dataflow
directions on communication buses and select ALU and memory functions
• Control signals are generated by a control unit consisting of one or more
finite‐state machines
Dr. Sudip Roy 8

The document provides an overview of the basic components and operation of a computer system. It describes the processor, main memory, I/O modules, and system bus. It explains how the processor fetches and executes instructions, and how interrupts allow other modules to interrupt normal program flow to improve processor utilization for I/O-bound operations. The memory hierarchy is discussed, with faster but smaller and more expensive memory levels closer to the processor.

coa Chapter 2 final edited*Minimum 40 characters required.pptfathibanki

HHCJ AMUMARA:COMPUTER STUDIES LECTURE NOTE FOR SS1:002SOLOMONCHINAEMEUCHEA

Registers are temporary storage areas within the CPU that can hold instructions and data during processing. They allow for faster access and transfer of information compared to main memory. An address identifies the location of data in memory. A bus is a communication pathway that allows different computer components to transfer data by carrying all communications over a single channel. There are internal and expansion buses. Registers include the memory data register, current instruction register, and program counter. They are faster than main memory and are used to store addresses, instructions, and data during processing. The speed of data transfer depends on factors like RAM size, CPU speed, register size, bus width and speed, and cache memory.

HHCJ AMUMARA:COMPUTER STUDIES LECTURE NOTE FOR SS3:005SOLOMONCHINAEMEUCHEA

Registers are temporary storage areas within the CPU that can hold instructions and data during processing. They allow for faster access and transfer of information compared to main memory. There are different types of registers that serve specific purposes, such as the program counter, accumulator, and memory address register. Buses are communication pathways that connect the CPU to other computer components like memory and expansion cards. The internal bus connects the CPU to RAM while the expansion bus allows additional devices to connect. Factors that influence data transfer speeds include RAM size, CPU speed and generation, register size, bus width and speed, and cache memory amount.

3. IICT_Lecture 03_Computer Org PersonalNational College of Business Administration and Economics

Chapter 8Er. Nawaraj Bhandari

This document discusses the structure and function of a CPU. It describes the basic components of a processor including the ALU, control unit, and registers. It explains the roles of different types of registers like general purpose, data, address, and control/status registers. The document then outlines the basic instruction cycle including fetch, execute, and interrupt cycles. It provides diagrams to illustrate the data flow during these cycles. Finally, it introduces the concept of pipelining which allows overlapping the stages of instruction processing to improve processor throughput.

Computer Organization: Introduction to Microprocessor and MicrocontrollerAmrutaMehata

This document provides information on microprocessors and microcontrollers. It discusses the key differences between microprocessors and microcontrollers, including that microcontrollers contain a processor core, memory and I/O pins on a single chip while microprocessors only contain a CPU. Examples of common microcontrollers and microprocessors are provided. The document also describes the functions, advantages, applications and architecture of microprocessors such as the Pentium. It provides details on the 8051 microcontroller including its 8-bit ALU.

Processor Organization and ArchitectureVinit Raut

The document discusses processor organization and architecture. It covers the Von Neumann model, which stores both program instructions and data in the same memory. The Institute for Advanced Study (IAS) computer is described as the first stored-program computer, designed by John von Neumann to overcome limitations of previous computers like the ENIAC. The document also covers the Harvard architecture, instruction formats, register organization including general purpose, address, and status registers, and issues in instruction format design like instruction length and allocation of bits.

introduction COA(M1).pptxBhavanaMinchu

The document provides an introduction to the course on computer organization and architecture. It discusses key concepts like: - Where data is stored, processed, and displayed in a computer. - Computer architecture deals with the functional behavior and design implementation of computer systems. Computer organization deals with the structural relationships and utilization within a computer system. - The document outlines the syllabus which will cover topics like basic computer structure, memory systems, arithmetic and logical operations, and parallel processing techniques like pipelining and vector processing. - Performance is a key measure of computers and depends on factors like hardware design, instruction set, and compiler optimizations. Processor clock rate and the basic performance equation are discussed as measures of a computer's

Ch 2 inside systems unitSajid Mewati

This document provides an overview of the components inside a computer system. It discusses how computers represent data using binary numbers and bytes. It then describes the major internal components of a computer system unit including the motherboard, CPU, memory, expansion cards, and connections on the outside of the system unit. The document explains the role of the motherboard and lists the common components found on it such as the CPU, memory, chipset, and cache. It also discusses how CPUs process data and factors that determine processor performance.

computer organisation and architecture Module 2.pptxAkashML4

Computer organizationishapadhy

The document discusses computer organization and architecture. It defines a computer as a general-purpose programmable machine that can execute a list of instructions. The Von Neumann architecture is described as having a CPU, memory, control unit, and input/output unit. Register transfer language (RTL) represents the transfer of data between registers using symbols. Key components like the ALU, registers, and buses are explained in terms of their role in processing and transferring data and instructions.

HHCJ AMUMARA: COMPUTER STUDIES LECTURE NOTE FOR SS2-001SOLOMONCHINAEMEUCHEA

Registers are temporary storage areas within the CPU that can hold instructions and data during processing. They are faster than main memory. An address identifies the location of data in memory. A bus is a communication pathway that allows different computer components to transfer data. There are internal and expansion buses. Registers include the memory data register, current instruction register, and program counter. Booting loads an operating system from secondary storage into RAM to start a computer, while shutting down closes programs to turn off power in an orderly fashion.

CS3451-OPERATING-SYSTEM NOTES ALL123.pdfPonniS7

ch 2_Component and function of computer .pptxToyba2

UNIT -1 COMPUTER ORGANIZATION (1).pptxxcbhaskarsai499

Basic Computer ArchitectureYong Heui Cho

This document provides an overview of basic computer architecture. It discusses the history of computers, components like the CPU, motherboard, and connections between parts. The document outlines CPU architecture including the fetch-decode-execute cycle and components like the ALU, control unit, and registers. It also describes memory, addressing, cache, and different memory types like RAM, ROM, and CMOS.

Ch 01 os8eSyed Faisal

This document provides an overview of basic computer system components and their functions. It discusses the main components including the processor, main memory, I/O modules, and system bus. It also describes how instructions are executed in a fetch-execute cycle and how interrupts can alter the normal sequencing. The memory hierarchy is introduced, including caches and different levels of memory. Common I/O techniques like programmed I/O, interrupt-driven I/O, and direct memory access are summarized. Finally, symmetric multiprocessors and multicore computers are defined.

Unit 1 processormemoryorganisationKarunamoorthy B

This document provides an overview of processor and memory organization for embedded systems. It describes the main structural units in a processor like the control unit, arithmetic logic unit, registers, and caches. It also discusses different types of memory devices like ROM, RAM, and their selection for embedded applications. The document outlines how memory is allocated to program segments, blocks and memory mapping. It introduces direct memory access and interfacing of processors, memory and I/O devices.

Unit 2 processor&memory-organisationPavithra S

This document discusses processor and memory organization for embedded systems. It describes the structural units of a processor like the MAR, MDR, buses, BIU, IR, ID, CU, ALU, PC, and caches. It covers memory devices like ROM, RAM, SRAM, DRAM, and flash memory. It provides case studies on selecting a processor based on features like clock speed, performance needs, and power efficiency. The document aims to help with selecting appropriate processors and memory for different types of embedded systems.

Chap 3 CA.pptxSahalAhmed4

The document discusses the components inside a CPU. It describes the motherboard, power supply, cooling fan, and drive bays that are inside the computer case. On the motherboard are the system clock, microprocessor, memory, chipset, and input/output buses. The CPU is made up of a control unit, instruction unit with ALU and FPU, registers, caches, and buses that connect the components. Common CPU components like the clock, control unit, and cache are also explained in detail.

hardware.pptx on hardwaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaarekuzivakwshemukwakwam

Chapter1 Computer System Overview Part-1.pptShikhaManrai1

Operating System Basic Elements Processor Top-Level Components Processor Registers User-Visible Registers Control and Status Registers Instruction Execution Instruction Cycle Instruction Fetch and Execute Instruction Register Characteristics of a Hypothetical Machine Direct Memory Access (DMA) Interrupts Program Flow of Control Without Interrupts Interrupt Handler Interrupt Cycle Timing Diagram Based on Short I/O Wait Multiple Interrupts Memory Hierarchy Disk Cache Cache Memory Programmed I/O Interrupt-Driven I/O

computer devices and memory unit 2 notes.pdfshubhangisonawane6

This document provides an overview of various computer devices and components. It discusses the central processing unit (CPU) which includes the arithmetic logic unit (ALU) and control unit (CU). It also describes different types of computer memory including primary memory like random access memory (RAM) and read-only memory (ROM), as well as secondary storage devices. Finally, it lists several common input/output and network devices.

Computer Architecture and Organization pptJayasimhaThummala1

Chapter1 Computer System Overview.pptShikhaManrai1

This document provides an overview of basic computer system components and their functions. It discusses the operating system, main hardware components like the processor and memory, and how they interact. It also covers concepts like interrupts, memory hierarchy, caches, and different I/O techniques like programmed I/O, interrupt-driven I/O, and direct memory access. The document is intended as an introductory overview of computer systems.

Computer_Organization_and_Architecture.pptxManimegalaM3

CSN221_Lec_27 Computer Architecture and Microprocessorssuser034ce1

CSN221_Lec_26 Computer Architecture and Microprocessorssuser034ce1

More Related Content

Similar to CSN221_Lec_4.pdf Computer Organization & Architecture (20)

Processor Organization and ArchitectureVinit Raut

introduction COA(M1).pptxBhavanaMinchu

Ch 2 inside systems unitSajid Mewati

computer organisation and architecture Module 2.pptxAkashML4

Computer organizationishapadhy

HHCJ AMUMARA: COMPUTER STUDIES LECTURE NOTE FOR SS2-001SOLOMONCHINAEMEUCHEA

CS3451-OPERATING-SYSTEM NOTES ALL123.pdfPonniS7

ch 2_Component and function of computer .pptxToyba2

UNIT -1 COMPUTER ORGANIZATION (1).pptxxcbhaskarsai499

Basic Computer ArchitectureYong Heui Cho

Ch 01 os8eSyed Faisal

Unit 1 processormemoryorganisationKarunamoorthy B

Unit 2 processor&memory-organisationPavithra S

Chap 3 CA.pptxSahalAhmed4

hardware.pptx on hardwaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaarekuzivakwshemukwakwam

Chapter1 Computer System Overview Part-1.pptShikhaManrai1

computer devices and memory unit 2 notes.pdfshubhangisonawane6

Computer Architecture and Organization pptJayasimhaThummala1

Chapter1 Computer System Overview.pptShikhaManrai1

Computer_Organization_and_Architecture.pptxManimegalaM3

Processor Organization and ArchitectureVinit Raut

introduction COA(M1).pptxBhavanaMinchu

Ch 2 inside systems unitSajid Mewati

computer organisation and architecture Module 2.pptxAkashML4

Computer organizationishapadhy

HHCJ AMUMARA: COMPUTER STUDIES LECTURE NOTE FOR SS2-001SOLOMONCHINAEMEUCHEA

CS3451-OPERATING-SYSTEM NOTES ALL123.pdfPonniS7

ch 2_Component and function of computer .pptxToyba2

UNIT -1 COMPUTER ORGANIZATION (1).pptxxcbhaskarsai499

Basic Computer ArchitectureYong Heui Cho

Ch 01 os8eSyed Faisal

Unit 1 processormemoryorganisationKarunamoorthy B

Unit 2 processor&memory-organisationPavithra S

Chap 3 CA.pptxSahalAhmed4

hardware.pptx on hardwaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaarekuzivakwshemukwakwam

Chapter1 Computer System Overview Part-1.pptShikhaManrai1

computer devices and memory unit 2 notes.pdfshubhangisonawane6

Computer Architecture and Organization pptJayasimhaThummala1

Chapter1 Computer System Overview.pptShikhaManrai1

Computer_Organization_and_Architecture.pptxManimegalaM3

More from ssuser034ce1 (20)

CSN221_Lec_27 Computer Architecture and Microprocessorssuser034ce1

CSN221_Lec_26 Computer Architecture and Microprocessorssuser034ce1

CSN221_Lec_25 Computer Architecture and Microprocessorssuser034ce1

CSN221_Lec_36 Computer Architecture and Microprocessorssuser034ce1

CSN221_Lec_35 Computer Architecture and Microprocessorssuser034ce1

CSN221_Lec_34 Computer Architecture and Microprocessorssuser034ce1

CSN221_Lec_22.pdf Computer Architecture and Microprocessorssuser034ce1

CSN221_Lec_17.pdf Multi Cycle Datapath Designssuser034ce1

CSN221_Lec_16.pdf MIPS ISA and Datapath designssuser034ce1

CSN221_Lec_15.pdf MIPS ISA and Datapath designssuser034ce1

Computer Architecture CSN221_Lec_37_SpecialTopics.pdfssuser034ce1

CSN221_Lec_5.pdf Computer Organization, CPU Structure and Functionsssuser034ce1

CS-102 Data Structures huffman coding.pdfssuser034ce1

Huffman coding is a lossless data compression algorithm that uses variable-length codewords to encode symbols based on their frequency of occurrence in a file. It builds a binary tree from the frequency of symbols, with more common symbols nearer the root, to assign shorter codewords to more frequent symbols. The document describes the basic Huffman coding algorithm which involves building the Huffman tree from a priority queue of symbol frequencies, traversing the tree to determine codewords, and encoding a sample text file using the new codewords to achieve compression. Real-world applications of Huffman coding include data compression in GNU gzip and internet standards.

CS-102 Data Structures HashFunction CS102.pdfssuser034ce1

Hashing is a technique for implementing dictionaries that provides constant time per operation on average. It works by using a hash function to map keys to positions in a hash table. Ideally, an element with key k would be stored at position h(k). However, collisions can occur if multiple keys map to the same position. When a collision occurs, the element is stored in the next available empty position. Searching for an element involves computing its hash value to locate its position, and searching linearly if a collision is encountered. Deletion requires marking deleted positions as empty rather than truly empty to avoid interfering with searches.

CS-102 Data Structure lectures on Graphsssuser034ce1

The document defines and explains various graph concepts: - It describes graph representations like adjacency matrices and lists, and types of graphs like undirected, directed, and weighted. - Key graph terminology is introduced such as vertices, edges, paths, cycles, connectedness, subgraphs, and degrees of vertices. - Examples are provided to illustrate concepts like complete graphs, trees, and bipartite graphs. - Graph representations like adjacency matrices and linked/packed adjacency lists are also summarized.

CS-102 DS-class04a Lectures DS Class.pdfssuser034ce1

This document discusses different components of space complexity, including instruction space for storing compiled program code, data space for storing variables and constants, and environment stack space for saving function call information. It provides examples of calculating space complexity for programs using arrays, recursion, and dynamic memory allocation, noting space complexities of O(1), O(n), O(n^2), and O(log n).

CS-102 DS-class03 Class DS Lectures .pdfssuser034ce1

The document discusses big O notation and how it is used to analyze the time complexity of algorithms. It provides examples of calculating time complexity for different code snippets. The time complexity classifications range from O(1) being utopian to O(dn) where d>1 being a disaster. It also discusses how to determine the time required to run a problem of larger size based on the time taken for a smaller size.

CS-102 DS-class_01_02 Lectures Data .pdfssuser034ce1

This document provides information about the Data Structures course CS 102 taught by Dr. Balasubramanian Raman at Indian Institute of Technology Roorkee. It outlines the course syllabus, importance of algorithms and data structures, and how to analyze time and space complexity of algorithms. Key concepts covered include asymptotic notation such as Big-O, Big-Omega, and Big-Theta which are used to describe how fast algorithms grow relative to input size. Examples are provided to illustrate these asymptotic notations.

CS-102 BT_24_3_14 Binary Tree Lectures.pdfssuser034ce1

The document discusses operations on heaps and leftist trees. Key points include: - Heaps can be used to implement priority queues, with operations like MAX-HEAPIFY, BUILD-MAX-HEAP, and HEAPSORT taking O(log n) time on average. - Leftist trees are a type of self-balancing binary search tree that supports priority queue operations like insertion and deletion in O(log n) time. - Leftist trees have properties like shortest root-to-leaf paths being O(log n) that allow them to efficiently support priority queue operations through melding of subtrees.

CS-102 Course_ Binary Tree Lectures .pdfssuser034ce1

Heap sort uses a max heap to sort an array in O(n log n) time. It works by building a max heap from the array and then repeatedly removing the maximum element and placing it in the correct position. It first constructs a max heap from the input array. It then iterates from the end of the array to the beginning, removing each element from the heap and placing it in the current position. This places the largest elements at the end of the array and the smallest at the beginning.

CSN221_Lec_27 Computer Architecture and Microprocessorssuser034ce1

CSN221_Lec_26 Computer Architecture and Microprocessorssuser034ce1

CSN221_Lec_25 Computer Architecture and Microprocessorssuser034ce1

CSN221_Lec_36 Computer Architecture and Microprocessorssuser034ce1

CSN221_Lec_35 Computer Architecture and Microprocessorssuser034ce1

CSN221_Lec_34 Computer Architecture and Microprocessorssuser034ce1

CSN221_Lec_22.pdf Computer Architecture and Microprocessorssuser034ce1

CSN221_Lec_17.pdf Multi Cycle Datapath Designssuser034ce1

CSN221_Lec_16.pdf MIPS ISA and Datapath designssuser034ce1

CSN221_Lec_15.pdf MIPS ISA and Datapath designssuser034ce1

Computer Architecture CSN221_Lec_37_SpecialTopics.pdfssuser034ce1

CSN221_Lec_5.pdf Computer Organization, CPU Structure and Functionsssuser034ce1

CS-102 Data Structures huffman coding.pdfssuser034ce1

CS-102 Data Structures HashFunction CS102.pdfssuser034ce1

CS-102 Data Structure lectures on Graphsssuser034ce1

CS-102 DS-class04a Lectures DS Class.pdfssuser034ce1

CS-102 DS-class03 Class DS Lectures .pdfssuser034ce1

CS-102 DS-class_01_02 Lectures Data .pdfssuser034ce1

CS-102 BT_24_3_14 Binary Tree Lectures.pdfssuser034ce1

CS-102 Course_ Binary Tree Lectures .pdfssuser034ce1

Recently uploaded (20)

MAQUINARIA MINAS CEMA 6th Edition (1).pdfssuser562df4

Lidar for Autonomous Driving, LiDAR Mapping for Driverless Cars.pptxRishavKumar530754

railway wheels, descaling after reheating and before forgingJavad Kadkhodapour

Development of MLR, ANN and ANFIS Models for Estimation of PCUs at Different ...Journal of Soft Computing in Civil Engineering

Passenger car unit (PCU) of a vehicle type depends on vehicular characteristics, stream characteristics, roadway characteristics, environmental factors, climate conditions and control conditions. Keeping in view various factors affecting PCU, a model was developed taking a volume to capacity ratio and percentage share of particular vehicle type as independent parameters. A microscopic traffic simulation model VISSIM has been used in present study for generating traffic flow data which some time very difficult to obtain from field survey. A comparison study was carried out with the purpose of verifying when the adaptive neuro-fuzzy inference system (ANFIS), artificial neural network (ANN) and multiple linear regression (MLR) models are appropriate for prediction of PCUs of different vehicle types. From the results observed that ANFIS model estimates were closer to the corresponding simulated PCU values compared to MLR and ANN models. It is concluded that the ANFIS model showed greater potential in predicting PCUs from v/c ratio and proportional share for all type of vehicles whereas MLR and ANN models did not perform well.

15th International Conference on Computer Science, Engineering and Applicatio...IJCSES Journal

Degree_of_Automation.pdf for Instrumentation and industrial specialistshreyabhosale19

Explainable-Artificial-Intelligence-XAI-A-Deep-Dive (1).pptxMahaveerVPandit

Structural Response of Reinforced Self-Compacting Concrete Deep Beam Using Fi...Journal of Soft Computing in Civil Engineering

Analysis of reinforced concrete deep beam is based on simplified approximate method due to the complexity of the exact analysis. The complexity is due to a number of parameters affecting its response. To evaluate some of this parameters, finite element study of the structural behavior of the reinforced self-compacting concrete deep beam was carried out using Abaqus finite element modeling tool. The model was validated against experimental data from the literature. The parametric effects of varied concrete compressive strength, vertical web reinforcement ratio and horizontal web reinforcement ratio on the beam were tested on eight (8) different specimens under four points loads. The results of the validation work showed good agreement with the experimental studies. The parametric study revealed that the concrete compressive strength most significantly influenced the specimens’ response with the average of 41.1% and 49 % increment in the diagonal cracking and ultimate load respectively due to doubling of concrete compressive strength. Although the increase in horizontal web reinforcement ratio from 0.31 % to 0.63 % lead to average of 6.24 % increment on the diagonal cracking load, it does not influence the ultimate strength and the load-deflection response of the beams. Similar variation in vertical web reinforcement ratio leads to an average of 2.4 % and 15 % increment in cracking and ultimate load respectively with no appreciable effect on the load-deflection response.

Introduction to Zoomlion Earthmoving.pptxAS1920

some basics electrical and electronics knowledgenguyentrungdo88

QA/QC Manager (Quality management Expert)rccbatchplant

"Feed Water Heaters in Thermal Power Plants: Types, Working, and Efficiency G...Infopitaara

A feed water heater is a device used in power plants to preheat water before it enters the boiler. It plays a critical role in improving the overall efficiency of the power generation process, especially in thermal power plants. 🔧 Function of a Feed Water Heater: It uses steam extracted from the turbine to preheat the feed water. This reduces the fuel required to convert water into steam in the boiler. It supports Regenerative Rankine Cycle, increasing plant efficiency. 🔍 Types of Feed Water Heaters: Open Feed Water Heater (Direct Contact) Steam and water come into direct contact. Mixing occurs, and heat is transferred directly. Common in low-pressure stages. Closed Feed Water Heater (Surface Type) Steam and water are separated by tubes. Heat is transferred through tube walls. Common in high-pressure systems. ⚙️ Advantages: Improves thermal efficiency. Reduces fuel consumption. Lowers thermal stress on boiler components. Minimizes corrosion by removing dissolved gases.

DATA-DRIVEN SHOULDER INVERSE KINEMATICS YoungBeom Kim1 , Byung-Ha Park1 , Kwa...charlesdick1345

theory-slides-for react for beginners.pptxsanchezvanessa7896

Data Structures_Searching and Sorting.pptxRushaliDeshmukh2

ELectronics Boards & Product Testing_Shiju.pdfShiju Jacob

Reagent dosing (Bredel) presentation.pptxAlejandroOdio

Mathematical foundation machine learning.pdfTalhaShahid49

Smart_Storage_Systems_Production_Engineering.pptxrushikeshnavghare94

IntroSlides-April-BuildWithAI-VertexAI.pdfLuiz Carneiro

MAQUINARIA MINAS CEMA 6th Edition (1).pdfssuser562df4

Lidar for Autonomous Driving, LiDAR Mapping for Driverless Cars.pptxRishavKumar530754

railway wheels, descaling after reheating and before forgingJavad Kadkhodapour

Development of MLR, ANN and ANFIS Models for Estimation of PCUs at Different ...Journal of Soft Computing in Civil Engineering

15th International Conference on Computer Science, Engineering and Applicatio...IJCSES Journal

Degree_of_Automation.pdf for Instrumentation and industrial specialistshreyabhosale19

Explainable-Artificial-Intelligence-XAI-A-Deep-Dive (1).pptxMahaveerVPandit

Structural Response of Reinforced Self-Compacting Concrete Deep Beam Using Fi...Journal of Soft Computing in Civil Engineering

Introduction to Zoomlion Earthmoving.pptxAS1920

some basics electrical and electronics knowledgenguyentrungdo88

QA/QC Manager (Quality management Expert)rccbatchplant

"Feed Water Heaters in Thermal Power Plants: Types, Working, and Efficiency G...Infopitaara

DATA-DRIVEN SHOULDER INVERSE KINEMATICS YoungBeom Kim1 , Byung-Ha Park1 , Kwa...charlesdick1345

theory-slides-for react for beginners.pptxsanchezvanessa7896

Data Structures_Searching and Sorting.pptxRushaliDeshmukh2

ELectronics Boards & Product Testing_Shiju.pdfShiju Jacob

Reagent dosing (Bredel) presentation.pptxAlejandroOdio

Mathematical foundation machine learning.pdfTalhaShahid49

Smart_Storage_Systems_Production_Engineering.pptxrushikeshnavghare94

IntroSlides-April-BuildWithAI-VertexAI.pdfLuiz Carneiro

CSN221_Lec_4.pdf Computer Organization & Architecture

1. Course Website: http://faculty.iitr.ac.in/~sudiproy.fcs/csn221_2015.html Piazza Site: https://piazza.com/iitr.ac.in/fall2015/csn221 Dr. Sudip Roy CSN‐221: COMPUTER ARCHITECTURE AND MICROPROCESSORS Computer Organization, CPU Structure and Functions (Lecture - 4)

2. What does a processor work? • The CPU must be designed to accommodate the instructions and data to be processed Dr. Sudip Roy 2 System Bus System Bus Control Bus Data Bus Address Bus I/O 1 CPU RAM I/O 2 ALU CU Regs PC PSW IR Internal CPU Bus I/O n Main Memory (RAM)

3. CPU Structure and Functions: • What CPU does? 1. Fetch instructions 2. Interpret (decode) instructions 3. Fetch data 4. Process data 5. Write data Dr. Sudip Roy 3

4. CPU Internal Structure (Processor Organization): Dr. Sudip Roy 4

5. Internal Registers: • Working space (temporary storage) of processor • Called registers • Number and function vary between processor designs • One of the major design decisions • Top level of memory hierarchy • The registers in the CPU perform two roles:  User‐visible registers: assembly‐language programmer can minimize the main memory referencing by optimizing the use of registers  Control and status registers: Used by the control unit to control the operation of the CPU Dr. Sudip Roy 5

6. Internal Registers: • User‐visible registers: 1. General Purpose registers: (between 8 – 32 in number) FP register, stack operation register 2. Data registers: Only to hold data, Often possible to combine two data registers (e.g., double int a; long int a;) 3. Address registers: To hold address, like Segment Register, Stack Pointer 4. Condition Codes: Holds flag values of the result, like +ve, ‐ve, zero or overflow Dr. Sudip Roy 6

7. Internal Registers: • Control and Status registers: 1. Program Counter (PC): Contains address of an instruction to be fetched 2. Instruction Register (IR): Contains the instruction most recently fetched 3. Memory Address Register (MAR): Contains the address of a location in memory 4. Memory Buffer Register (MBR): Contains the data to be written to the memory or data most recently read • Program Status Word (PSW): A set of bits, Includes Condition Codes, Common fields are: • Sign: A sign bit of the last arithmetic operation • Zero: A bit set when the result is zero • Carry: Set if an operation resulted in a carry (addition) or a borrow (subtraction) out of a high‐ order bit • Equal: Set if a logical compare result is equality • Overflow: To indicate arithmetic overflow • Interrupt enable/disable: To enable/disable interrupt • Supervisor: To indicate whether the CPU is executing in supervisor or user mode Dr. Sudip Roy 7

8. Datapath and Control: • Datapath: • Memory, registers, adders, ALU, and communication buses • Each step (fetch, decode, execute, save result) requires communication (data transfer) paths between memory, registers and ALU • Control: • Datapath for each step is set up by control signals that set up dataflow directions on communication buses and select ALU and memory functions • Control signals are generated by a control unit consisting of one or more finite‐state machines Dr. Sudip Roy 8

CSN221_Lec_4.pdf Computer Organization & Architecture

Recommended

More Related Content

Similar to CSN221_Lec_4.pdf Computer Organization & Architecture (20)

More from ssuser034ce1 (20)

Recently uploaded (20)

CSN221_Lec_4.pdf Computer Organization & Architecture