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CTS EXCEPTIONSPrediction of Aluminium wire rod physical properties through AI, ML or any modern technique for better productivity and quality control.
- 1. TECHNICAL PRESENTATION ON CTS EXCEPTIONS BY SARATHI T PD - 07
- 2. Agenda ➢ What is CTS? ➢ Goals of CTS ➢ Input files ➢ CTS Exceptions ➢ Output files ➢ Conclusion
- 3. What is CTS? ❖ Clock Tree Synthesis (CTS) is a technique in VLSI design that distributes the clock signal evenly across the chips sequential devices by inserting buffers or inverters along the clock path to balance the clock delay.
- 4. Goals of CTS • minimum skew • minimum insertion delay • DRV constraints • Timing • Crosstalk • Electromigration
- 5. Input files Technology files Netlists (gate-level) MCMM Library files NDR Clock files (CTS cells)
- 6. CTS Exceptions 1. Ignore pin 2. Stop pin 3. Exclude pin 4. Through pin 5. Don’t buffer net 6. Don’t size cells
- 7. ➢ IGNORE PINS • All non-clock pins of sequential devices such as data pins , reset pin , output pins , enables are called as ignore pins (float pins). • No DRV and no balancing is allowed. ➢ STOP PINS • Stop pin is a pin on a sequential or a combinational device where the clock signal terminates or is not intended to propagate further during CTS. • The tool stops to inserting buffers/inverters or performing clock balancing beyond this point. ➢ EXCLUDE PINS • These are the pins on the cell where the clock signal is not consider for optimization during CTS . • These pins are excluded from clock tree building and balancing to simplify the design and avoid unnecessary clock buffering but DRV fixing is allowed.
- 8. ➢ THROUGH PIN • These pins allows the clock signals to continue propagating through the pin. • DRV fixing and clock balancing are allowed. ➢ DON’T BUFFER NETS • It specifies certain nets should not have any buffer/inverters insertion during CTS. ➢ DON’T SIZE CELLS • It prevents the resizing of a specific standard cells during CTS.
- 9. ➢ DON’T TOUCH CELLS • Don’t touch cells are different from normal standard cells because normal standard cells has vary input transition time and output transition time .but in don’t touch cells ,the input transition time and output transition time are equal. ➢ DON’T TOUCH SUBTREE • It is a design constraint that prevents any modification to an entire subtree of the clock tree during CTS optimization . • This includes removal , resizing or buffering of cells within the clock subtree.
- 11. CLOCK BUFFERS NORMAL BUFFERS Equal rise time and fall time Unequal rise time and fall time Less delay More delay More area Less area Less delay variation with PVT and OCV More delay variation with PVT and OCV
- 13. OUTPUT FILES • Design Exchange Format (DEF) files • Standard Parasitic Extracted Format (SPEF) files • Library files • Timing report files • Power report files
- 14. CONCLUSION After CTS optimization, it ensures the timing closure , skew reduction , power efficiency , signal integrity. It also significantly affect the overall quality of the chips and ensuring the design operates with minimum issue during manufacturing.
- 15. Thank you!…