Design and Verification of Area Efficient Carry Select Adder
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The document discusses the design and verification of an area-efficient carry select adder (CSLA) aimed at improving power consumption and area efficiency in digital adders. By utilizing a binary to excess-1 converter in place of certain ripple carry adders, the proposed architecture minimizes area usage while achieving a marginal increase in delay. Simulation results indicate enhanced performance of the modified CSLA compared to conventional designs in terms of area and power efficiency.
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![IJSRD - International Journal for Scientific Research & Development| Vol. 2, Issue 08, 2014 | ISSN (online): 2321-0613
All rights reserved by www.ijsrd.com 78
Design and Verification of Area Efficient Carry Select Adder
V D L Sivasankar1
Ch. Swathi2
B. Shirisha3
1
M. Tech Student 2
Assistant Professor 3
Assistant Professor (HOD)
1,2,3
Department of Electronics and Communication Engineering
1,2,3
Vathsalya Institute of science and technology, R.R Dist, T.S, India
Abstract— Carry Select Adder (CSLA) is one of the fastest
adders used in many data-processing processors to perform
fast arithmetic functions. From the structure of the CSLA, it
is clear that there is scope for reducing the area and power
consumption in the CSLA. This work uses a simple and
efficient gate-level modification to significantly reduce the
area and power of the CSLA. Based on this modification 16,
32 square - root CSLA (SQRT CSLA) architecture have
been developed and compared with the regular SQRT CSLA
architecture. The proposed design has reduced area and
power as compared with the regular SQRT CSLA with only
a slight increase in the delay. This work evaluates the
performance of the proposed designs in terms of delay, area.
Key words: RISC, Lopower, BEC, Carry select adder.
I. INTRODUCTION
In digital adders, the speed of addition is limited by the time
required to propagate a carry through the adder. The sum for
each bit position in an elementary adder is generated
sequentially only after the previous bit position has been
summed and a carry propagated into the next position.
The CSLA is used in many computational systems
to alleviate the problem of carry propagation delay by
independently generating multiple carries and then select a
carry to generate the sum [1]. However, the CSLA is not
area efficient because it uses multiple pairs of Ripple Carry
Adders (RCA) to generate partial sum and carry by
considering carry input and , then the final sum and carry
are selected by the multiplexers (mux).
The basic idea of this work is to use Binary to
Excess-1 Converter (BEC) instead of RCA with in the
regular CSLA to achieve lower area and power consumption
[2]–[4]. The main advantage of this BEC logic comes from
the lesser number of logic gates than the -bit Full Adder
(FA) structure. The details of the BEC logic are discussed in
Section III.
This brief is structured as follows. Section II deals
with the delay and area evaluation methodology of the basic
adder blocks. Section III presents the detailed structure and
the function of the BEC logic.
4 Bit BEC
II. ADDER BLOCKS
A. Ripple carry adder:
It is possible to create a logical circuit using multiple full
adders to add N-bit numbers. Each full adder inputs a Cin,
which is the Cout of the previous adder. This kind of adder is
a ripple carry adder, since each carry bit "ripples" to the next
full adder. Note that the first (and only the first) full adder
may be replaced by a half adder.
In a 32-bit [ripple carry] adder, there are 32 full
adders, so the critical path (worst case) delay is 3 (from
input to carry in first adder) + 31 * 2 (for carry propagation
in later adders) = 65 gate delays.
B. Carry Select Adder:
In electronics, a carry-select adder is a particular way to
implement an adder, which is a logic element that computes
the n+1-bit sum of two -bit numbers. The carry-select
adder is simple but rather fast, having a gate level depth of
O(root(n)).
The carry-select adder generally consists of two
ripple carry adders and a multiplexer. Adding two n-bit
numbers with a carry-select adder is done with two adders
(therefore two ripple carry adders) in order to perform the
calculation twice, one time with the assumption of the carry
being zero and the other assuming one. After the two results
are calculated, the correct sum, as well as the correct carry,
is then selected with the multiplexer once the correct carry is
known.
C. Uniform-sized adder:
A 16-bit carry-select adder with a uniform block size of 4
can be created with three of these blocks and a 4-bit ripple
carry adder. Since carry-in is known at the beginning of
computation, a carry select block is not needed for the first
four bits. The delay of this adder will be four full adder
delays, plus three MUX delays.
Uniform sized adder
D. Variable-sized adder:
A 16-bit carry-select adder with variable size can be
similarly created. Here we show an adder with block sizes of
2-2-3-4-5. This break-up is ideal when the full-adder delay
is equal to the MUX delay, which is unlikely. The total
delay is two full adder delays, and four mux delays.](https://image.slidesharecdn.com/ijsrdv2i8074-150923083728-lva1-app6891/85/Design-and-Verification-of-Area-Efficient-Carry-Select-Adder-1-320.jpg)
![Design and Verification of Area Efficient Carry Select Adder
(IJSRD/Vol. 2/Issue 08/2014/020)
All rights reserved by www.ijsrd.com 79
Variable sized Adder
E. Regular CSA:
The structure of the 16-b regular SQRT CSLA is shown in
Fig. 4. It has five groups of different size RCA. The delay
and area evaluation of each group are shown in Fig. 5, in
which the numerals within specify the delay values, e.g.,
sum2 requires 10 gate delays. The steps leading to the
evaluation are as follows.
Regular CSA
The group2 [see Fig.] has two sets of 2-b RCA.
Based on the consideration of delay values of Table I, the
arrival time of selection input c1(time(t)=7) of 6:3 mux is
earlier than s3[t=8] and later thans2[t=6]. Thus, sum3 [t=11]
is summation of s3 and mux [t=3] and sum2 [t=10] is
summation of c1 and mux
Except for group2, the arrival time of mux
selection input is always greater than the arrival time of data
outputs from the RCA’s. Thus, the delay of group3 to
group5 is determined, respectively as follows:
The one set of 2-b RCA in group2 has 2 FA for
cin=0 and the other set has 1 FA and 1 HA forcing=1. Based
on the area count of Table I, the total number of gate counts
in group2 is determined as follows:
III. LOW POWER AREA EFFICIENT CARRY SELECT ADDER
CIRCUIT
CSA adder, like ripple-carry adders, is the carry has to to
travel through every full adder block. There is a way to
improve the speed by duplicating the hardware due to the
fact that the carry can only be either 0 or 1. The method is
based on the conditional sum adder and extended to a carry-
select adder. With one RCA.each computing the case of the
one polarity of the carry-in, the sum can be obtained with a
2x1 multiplexer with the carry-in as the select signal.
The basic idea of this work is to use Binary to
Excess-1 Converter (BEC) instead of RCA with in the
regular CSLA to achieve lower area and power
consumption. The main advantage of this BEC logic comes
from the lesser number of logic gates than the n-bit Full
Adder (FA) structure. This work is to use BEC instead of
the RCA with cin=1 in order to reduce power consumption
of the regular CSA. To replace the n-bit RCA, an n+1bit
BEC is required [5].
Modified CSA
Group 2 of Modified BEC](https://image.slidesharecdn.com/ijsrdv2i8074-150923083728-lva1-app6891/85/Design-and-Verification-of-Area-Efficient-Carry-Select-Adder-2-320.jpg)
![Design and Verification of Area Efficient Carry Select Adder
(IJSRD/Vol. 2/Issue 08/2014/020)
All rights reserved by www.ijsrd.com 80
The group2 [see Fig] has one 2-b RCA which has 1
FA and 1 HA for Cin=0. Instead of another 2-b RCA with
Cin=1 a 3-b BEC is used which adds one to the output from
2-b RCA
Group 4 of Modified BEC
Similarly, the estimated maximum delay and area
of the other groups of the modified SQRT CSLA are
evaluated.
IV. RESULT
Simulation Result
Synthesis RTL
V. CONCLUSION
Carry Select Adder (CSLA) is one of the fastest adders used
in many data-processing processors to perform fast
arithmetic functions. From the structure of the CSLA, it is
clear that there is scope for reducing the area consumption
in the CSLA. This work uses a simple and efficient gate-
level modification to significantly reduce the area and power
of the CSLA. Based on this modification 16- CSLA
architecture have been developed and compared with the
regular CSLA architecture. Carry Select Adder is realized
by using verilog HDL. Simulation and synthesis by using
Xilinx Palanahead. The delay of CSA is small high compare
to Regular Carry select adder if u improve that one by no
degration of area and power.
REFERENCES
[1] Verilog HDL- Digital Design and Synthesis, by
Samir Palnitkar
[2] O. J. Bedrij, “Carry-select adder,” IRE Trans.
Electron. Compute. pp. 340–344, 1962.
[3] B. Ramkumar, H.M. Kittur, and P. M. Kannan,
“ASIC implementation of modified faster carry save
adder,” Eur. J. Sci. Res., vol. 42, no. 1, pp. 53–58,
2010
[4] T. Y. Ceiang and M. J. Hsiao, “Carry-select adder
using single ripple carry adder,” Electron. Lett. vol.
34, no. 22, pp. 2101–2103, Oct. 1998.
[5] J. M. Rabaey, Digital Integrated Circuits—A Design
Perspective. Upper Saddle River, NJ: Prentice-Hall,
2001.
[6] Y. He, C. H. Chang, and J. Gu, “An area efficient
64-bit square root carry-select adder for low power
applications,” in Proc. IEEE Int. Symp. Circuits
Syst., 2005, vol. 4, pp. 4082–4085.](https://image.slidesharecdn.com/ijsrdv2i8074-150923083728-lva1-app6891/85/Design-and-Verification-of-Area-Efficient-Carry-Select-Adder-3-320.jpg)
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Csla 130319073823-phpapp01-140821210430-phpapp02
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implementation and design of 32-bit adder
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Design of Low Power Energy Efficient Carry Select Adder Using CMOS Technology
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128-Bit Area Efficient Reconfigurable Carry Select Adder ijcisjournal This document presents a novel design for a 128-bit area-efficient carry select adder (CSLA) that significantly reduces gate count from 3320 to 1664 by optimizing logic sharing methods. The proposed architecture decreases both area and total power consumption while maintaining competitive speed in comparison to conventional CSLA designs. Implemented on Artix-7 FPGA, the new design demonstrates a marked improvement in resource efficiency, making it suitable for VLSI hardware applications.
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Cq25550554IJERA Editor The document discusses the design of an efficient 64-bit carry select adder (CSLA) aimed at reducing delay and area while improving addition speed for VLSI systems. It introduces a modified CSLA architecture that replaces traditional ripple carry adders with binary to excess-1 converters to optimize performance. Simulation results demonstrate the proposed design yields lower delay and comparable area for various bit sizes, suggesting it as a viable choice for high-performance processors.
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International Journal of Engineering Research and Development (IJERD)IJERD Editor This paper presents a low power, area, and delay efficient carry select adder (CSLA) using a binary to excess-1 converter (BEC) to optimize performance compared to a regular CSLA architecture. The proposed design reduces area, power consumption, and delay by replacing ripple carry adders with the BEC, which utilizes fewer logic gates. Performance evaluations demonstrate that the modified CSLA exhibits significant improvements in efficiency over traditional methods.
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Paper id 37201520IJRAT This document describes a novel design for a 32-bit unsigned multiplier using a modified carry select adder (MCSLA). It begins with background on adders and multipliers in VLSI design. It then describes the conventional carry select adder (CSLA) and proposes a modified CSLA (MCSLA) that uses common boolean logic to reduce area and power. The document presents the design and VHDL simulation results of a 32-bit unsigned multiplier using both CSLA and the proposed MCSLA. The results show the MCSLA based multiplier achieves a 45% reduction in power-area-delay product compared to the CSLA based multiplier.
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M367578IJERA Editor This research article presents a high-speed, low power, and area-efficient implementation of the carry select adder (CSLA) utilizing a mux-add and binary to excess-1 converter (BEC). The proposed design improves upon traditional adder architectures by significantly reducing power consumption and propagation delay while optimizing area usage, making it suitable for modern processing applications. Simulation results demonstrate a 48.3% improvement in power-delay product and a 34.63% reduction in delay compared to modified CSLA, confirming the design's efficiency.
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LDMMIA Shop & Student News Summer Solstice 25
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Shop, Upcoming: Final Notes to Review as we Close Level One. Make sure to review the orientation and videos as well. There’s more to come and material to cover in Levels 2-3. The content will be a combination of Reiki and Yoga. Also energy topics of our spiritual collective.
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Design and Verification of Area Efficient Carry Select Adder
- 1. IJSRD - International Journal for Scientific Research & Development| Vol. 2, Issue 08, 2014 | ISSN (online): 2321-0613 All rights reserved by www.ijsrd.com 78 Design and Verification of Area Efficient Carry Select Adder V D L Sivasankar1 Ch. Swathi2 B. Shirisha3 1 M. Tech Student 2 Assistant Professor 3 Assistant Professor (HOD) 1,2,3 Department of Electronics and Communication Engineering 1,2,3 Vathsalya Institute of science and technology, R.R Dist, T.S, India Abstract— Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 16, 32 square - root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area. Key words: RISC, Lopower, BEC, Carry select adder. I. INTRODUCTION In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position. The CSLA is used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum [1]. However, the CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input and , then the final sum and carry are selected by the multiplexers (mux). The basic idea of this work is to use Binary to Excess-1 Converter (BEC) instead of RCA with in the regular CSLA to achieve lower area and power consumption [2]–[4]. The main advantage of this BEC logic comes from the lesser number of logic gates than the -bit Full Adder (FA) structure. The details of the BEC logic are discussed in Section III. This brief is structured as follows. Section II deals with the delay and area evaluation methodology of the basic adder blocks. Section III presents the detailed structure and the function of the BEC logic. 4 Bit BEC II. ADDER BLOCKS A. Ripple carry adder: It is possible to create a logical circuit using multiple full adders to add N-bit numbers. Each full adder inputs a Cin, which is the Cout of the previous adder. This kind of adder is a ripple carry adder, since each carry bit "ripples" to the next full adder. Note that the first (and only the first) full adder may be replaced by a half adder. In a 32-bit [ripple carry] adder, there are 32 full adders, so the critical path (worst case) delay is 3 (from input to carry in first adder) + 31 * 2 (for carry propagation in later adders) = 65 gate delays. B. Carry Select Adder: In electronics, a carry-select adder is a particular way to implement an adder, which is a logic element that computes the n+1-bit sum of two -bit numbers. The carry-select adder is simple but rather fast, having a gate level depth of O(root(n)). The carry-select adder generally consists of two ripple carry adders and a multiplexer. Adding two n-bit numbers with a carry-select adder is done with two adders (therefore two ripple carry adders) in order to perform the calculation twice, one time with the assumption of the carry being zero and the other assuming one. After the two results are calculated, the correct sum, as well as the correct carry, is then selected with the multiplexer once the correct carry is known. C. Uniform-sized adder: A 16-bit carry-select adder with a uniform block size of 4 can be created with three of these blocks and a 4-bit ripple carry adder. Since carry-in is known at the beginning of computation, a carry select block is not needed for the first four bits. The delay of this adder will be four full adder delays, plus three MUX delays. Uniform sized adder D. Variable-sized adder: A 16-bit carry-select adder with variable size can be similarly created. Here we show an adder with block sizes of 2-2-3-4-5. This break-up is ideal when the full-adder delay is equal to the MUX delay, which is unlikely. The total delay is two full adder delays, and four mux delays.
- 2. Design and Verification of Area Efficient Carry Select Adder (IJSRD/Vol. 2/Issue 08/2014/020) All rights reserved by www.ijsrd.com 79 Variable sized Adder E. Regular CSA: The structure of the 16-b regular SQRT CSLA is shown in Fig. 4. It has five groups of different size RCA. The delay and area evaluation of each group are shown in Fig. 5, in which the numerals within specify the delay values, e.g., sum2 requires 10 gate delays. The steps leading to the evaluation are as follows. Regular CSA The group2 [see Fig.] has two sets of 2-b RCA. Based on the consideration of delay values of Table I, the arrival time of selection input c1(time(t)=7) of 6:3 mux is earlier than s3[t=8] and later thans2[t=6]. Thus, sum3 [t=11] is summation of s3 and mux [t=3] and sum2 [t=10] is summation of c1 and mux Except for group2, the arrival time of mux selection input is always greater than the arrival time of data outputs from the RCA’s. Thus, the delay of group3 to group5 is determined, respectively as follows: The one set of 2-b RCA in group2 has 2 FA for cin=0 and the other set has 1 FA and 1 HA forcing=1. Based on the area count of Table I, the total number of gate counts in group2 is determined as follows: III. LOW POWER AREA EFFICIENT CARRY SELECT ADDER CIRCUIT CSA adder, like ripple-carry adders, is the carry has to to travel through every full adder block. There is a way to improve the speed by duplicating the hardware due to the fact that the carry can only be either 0 or 1. The method is based on the conditional sum adder and extended to a carry- select adder. With one RCA.each computing the case of the one polarity of the carry-in, the sum can be obtained with a 2x1 multiplexer with the carry-in as the select signal. The basic idea of this work is to use Binary to Excess-1 Converter (BEC) instead of RCA with in the regular CSLA to achieve lower area and power consumption. The main advantage of this BEC logic comes from the lesser number of logic gates than the n-bit Full Adder (FA) structure. This work is to use BEC instead of the RCA with cin=1 in order to reduce power consumption of the regular CSA. To replace the n-bit RCA, an n+1bit BEC is required [5]. Modified CSA Group 2 of Modified BEC
- 3. Design and Verification of Area Efficient Carry Select Adder (IJSRD/Vol. 2/Issue 08/2014/020) All rights reserved by www.ijsrd.com 80 The group2 [see Fig] has one 2-b RCA which has 1 FA and 1 HA for Cin=0. Instead of another 2-b RCA with Cin=1 a 3-b BEC is used which adds one to the output from 2-b RCA Group 4 of Modified BEC Similarly, the estimated maximum delay and area of the other groups of the modified SQRT CSLA are evaluated. IV. RESULT Simulation Result Synthesis RTL V. CONCLUSION Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area consumption in the CSLA. This work uses a simple and efficient gate- level modification to significantly reduce the area and power of the CSLA. Based on this modification 16- CSLA architecture have been developed and compared with the regular CSLA architecture. Carry Select Adder is realized by using verilog HDL. Simulation and synthesis by using Xilinx Palanahead. The delay of CSA is small high compare to Regular Carry select adder if u improve that one by no degration of area and power. REFERENCES [1] Verilog HDL- Digital Design and Synthesis, by Samir Palnitkar [2] O. J. Bedrij, “Carry-select adder,” IRE Trans. Electron. Compute. pp. 340–344, 1962. [3] B. Ramkumar, H.M. Kittur, and P. M. Kannan, “ASIC implementation of modified faster carry save adder,” Eur. J. Sci. Res., vol. 42, no. 1, pp. 53–58, 2010 [4] T. Y. Ceiang and M. J. Hsiao, “Carry-select adder using single ripple carry adder,” Electron. Lett. vol. 34, no. 22, pp. 2101–2103, Oct. 1998. [5] J. M. Rabaey, Digital Integrated Circuits—A Design Perspective. Upper Saddle River, NJ: Prentice-Hall, 2001. [6] Y. He, C. H. Chang, and J. Gu, “An area efficient 64-bit square root carry-select adder for low power applications,” in Proc. IEEE Int. Symp. Circuits Syst., 2005, vol. 4, pp. 4082–4085.