4. Structural Testing
Consider a circuit that implements a Boolean function with 𝑁 inputs.
How to test the fabricated circuit?
Functional Testing:
Apply all possible 2𝑁
input combinations and check output
Becomes infeasible for large 𝑁 (say 50 or 100)
Structural Testing:
Test the components that implements a logic function rather than testing the input–output
functionality
The paradigm of structural testing is widely employed
It reduces the number of test patterns required for good test quality
5. Functional Testing vs. Structural Testing
Structural Testing
Test individual components of the circuit ( G1, G2, G3, G4, and G5)
Each gate will require 24
= 16 input combinations (total 80)
Functional Testing
Will require 2^N, i.e., 216
= 65536 input combinations
Assumptions
Can observe the output pins for all the components
Can write any value at the input pins of all the components
There could be a problem in the integration of components (need to tackle
that also).
DFT techniques tries to make structural testing more effective
by ensuring the above assumptions.
6. Fault Models
Fault Model
Represents a defect using a logical or electrical
model
Why do we use a Fault Model?
Allows us to analyze the impact of a defect using
logic or circuit analysis techniques
Allows deriving test patterns algorithmically for
detecting a given fault
Quantitative assessment of testing
effectiveness using fault coverage
Transforms the problem of defect
detection to the
problem of fault detection
7. Stuck-at Fault Models
Stuck-at Fault Model
Assumes that defects cause the signal to be
permanently stuck at a constant logic
Transforms defects to a logical fault model
Two types:
Stuck at logic “0”: stuck-at-0 or SA0 fault
Stuck at logic “1”: stuck-at-1 or SA1 fault
Single Stuck-at Fault Model
Assumes that there is only one fault active at a
time
Reduces the complexity of test pattern generation
significantly
8. Stuck-at Faults: Fault Site
Fault-site:
The point where a fault exists or we assume it to exist
Emulate a stuck-at fault by first disconnecting the corresponding signal source.
Tie it to the constant logic (either 0 or 1 depending on the fault type)
Multi-fanout net (N>1):
(N+1) fault sites
9. Possible Stuck-at Faults: Illustration
Consider the circuit alongside
How many single stuck-at (0/1)
faults are possible in this circuit?
10. Detecting a Fault: Test Vectors
Test Vectors
Any input pattern, or sequence of input patterns, that produces a different output response
for a faulty circuit and a fault-free circuit
Exhaustive Testing for functionality
Exponential number of test vectors required (2𝑁
)
to test the functionality
Single stuck-at fault model makes the number of fault linear in the number of circuit elements
12. Combinational Circuit: Controllability and Observability
If the NAND gate was lying too deep in a circuit, it is
difficult to apply the required test vectors at the
inputs
Controllability: ability to set any desired value (0 or 1)
on the internal signals of a circuit by applying an
appropriate test-vector to the primary inputs
Similarly the output of NAND gate will be difficult to
observe at any primary output if the NAND gate is
lying too deep in circuit
Observability: ability to examine any internal signal by
propagating its value to a primary output by applying
appropriate test vector to the primary inputs.
13. Sequential Circuit: Controllability and Observability
Problem of controllability
Setting a particular value at any pin in a sequential circuit is more
difficult
Several cycles may be required to write a particular
value
State traversal required
Finding such a test sequence is time consuming by
sequential ATPG tool
Problem of observability
Similar difficulty in examining the value at a particular pin in the
sequential circuit (requires state traversal)
15. Design Modifications in SCAN Design Flow
Normal Flip Flop Vs SCAN Flip Flop
Extra primary ports added
TM (Test Mode)
SE (Scan Enable)
SI (Scan In)
SO (Scan Out)
D flip-flops replaced with
another memory elements
(scan cells)
Scan cells are reconnected to
form shift register (scan
chain)
Outcome:
Dramatically improve controllability and observability of memory elements (flip-flop) in a
sequential circuit
16. Scan Design Flow: Different Modes
Design works in three modes:
1. Normal Mode: functional mode in which chip
works
2. Shift Mode:
Memory elements (i.e. scan cells) work as
shift registers
Test vectors are shifted-in and responses
are shifted-out
3. Capture Mode: response of the fabricated
circuit is captured during testing
Test Mode Scan Enable
Normal Mode 0 0
Shift Mode 1 1
Capture Mode 1 0
17. Scan Cells:
Different kinds of scan cell can be
used
Most popular is MUXED-D Scan Cell
D, CLK, Q similar to D flip-flop
SI ≡ scan input
SE ≡ scan enable
Q also works as SO≡ scan out
The multiplexer selects data between D and SI
using the value at SE pin
In the normal/capture mode: SE=0
Value at D is latched
In the shift mode, SE=1
Value at SI is latched
Output pin produces the content of D flip-flop
Next State could be of D-pin or SI-pin
18. Scan Chain Formation
Normal D Flip Flops formation
Scan Flip Flops Formation
The SI pin of the first scan cell is
connected to the SI port
Q/SO pin of one cell is connected to
SI pin of the next cell to form a chain
Q/SO pin of the last scan cell is
connected to the SO port
All SE pins of scan cells are connected
to the SE port
Form a scan chain consisting of 𝑁 scan
cells
Any test vector can be shifted-in from SI
port in 𝑁 clock cycles
Any test response can be shifted-out
to SO port in 𝑁 clock cycles
Without scan chain, it could take
exponential number of cycles
No changes made to the
previous connections of D, Q and
CLK pins
19. Scan Design: Sequential to Combinational
Circuit Testing
Pins of a flip-flop becomes
controllable/observable from
primary input/output
Q-pin can be treated as
pseudo-primary input (PPI)
D-pin can be treated as
pseudo-primary output (PPO)
Scan design eases of testing:
Effectively transforms the problem of sequential circuit testing to combinational
circuit testing
Automatic test pattern generation (ATPG) problem effectively changes from sequential to
combinational
20. Scan Design Flow: Mechanism
Shift Mode: set SE=1.
Shift in the desired test vector using
port SI to the scan cells F1, F2, F3.
Apply the required test vector at
input
port also.
Capture Mode: set SE=0 for 1 clock cycle.
If there was a fault for which test vector was applied, scan cells will capture the result of
fault and receive “fault” output
Shift Mode: switch back to shift mode (SE=1)
Shift out the captured result to the port SO.
The result is compared with the expected response
Simultaneously, apply next test vector at port SI and allow it to scan-in through the scan
chain.
21. Scan Design Flow: Tasks
Design Preparation: Design becomes testable
Guidelines that must be followed during designing such that scan design flow can be used effectively
Scan Synthesis: Design becomes Scan Design
Scan Configuration: Design becomes Scan Design
Decide number of scan chains, scan cells to be used, exclude certain elements from being converted to
scan cells
Scan Replacement (During Synthesis)
Replace Flip-Flops with Scan Cells
Scan Reordering and Stitching (During Physical Design)
Reorder scan cells based on physical location so that routing becomes easier
Test Vector Generation
Scan Verification
Scan Shift/Capture Operation using logic simulator
Verify Timing (STA): Hold Violations
24. Built in Self Test (BIST):
•Drawbacks of ATE-based testing:
Cost of testing high
ATE cost
Voluminous test data: increase test
time
Can be done only in production test
• environment
Lacks capability of field testing
At-speed test difficult
Probe’s inductance/capacitance
bottleneck
•BIST as a solution:
Test-oriented additional hardware and
• software features inside a given IC
Allows IC to test their own operation
Reducing dependence on an external
ATE for testing
Repair in the field possible
25. BIST: Distinguishing Features
1. Contains Pseudo-random pattern generator inside the chip
Provides Test Vectors Dynamically
Avoids storing voluminous test vectors
2.Performs signature analysis for detecting failures
Does not perform comparison of exact response
Avoids storing voluminous expected response inside the chip
26. Testability: Fault Coverage vs. Random Test Pattern Count
Stuck-At Fault coverage rises to 100%
logarithmically
Reaching 90% coverage is easy using random
patterns
27. BIST: Architecture
Test Pattern Generator (TPG)
Generates pattern for testing
Can contain ROM
Test Response Analyzer (TRA)
Generates signature for the test
response and compare
ROM stores golden signature
Compares test signature with the golden
signature
Test Controller
Controls all the operations of BIST
Strategy for overall test control is
most difficult part of BIST
28. BIST: Test Pattern Generator
Pseudo-Random Pattern Generator
Linear Feedback Shift Register
(LFSR)
Repeatable
Small hardware can produce large
number of “random” test patterns
We can tap the output of any flip-flop
to provide feedback.
If we tap the output 𝑎𝑖 of the i-th
flip- flop, then ℎ𝑖 is taken as 1, else
it is taken as 0.
𝑎𝑘+1 = 𝑎𝑘
0 1
𝑎𝑘+1 = 𝑎𝑘
1 2
….
𝑎𝑘+1 = 𝑎𝑘
−
𝑛 2 −
𝑛 1
𝑎𝑘+1
= 𝑎𝑘
⊕ ℎ1𝑎𝑘
⊕ ℎ2𝑎𝑘
…
⊕ ⊕ ℎ −1
𝑛 𝑎𝑘
−
𝑛 1 0 1 2 −
𝑛 1
30. Pattern Generator: Considerations
LFSR
Test patterns generated by an LFSR have most of the properties of random numbers
Desirable to have long sequence so that good fault coverage is achieved
Some faults may be not covered by random pattern generator
Use ATPG to get deterministic test-vector and put those test-vectors in ROM
Helps achieve high fault coverage with small number of test vectors
31. BIST: Test Response Analyzer
No. of test patterns can be large (e.g. 1 million) and there can be many outputs (e.g. 100)
Too voluminous data to store in ROM (100 million bits)
Compaction: method of reducing the number of bits in the circuit response
Signature: a statistical property of a circuit, usually a number computed for a circuit from its
responses
Signature Analysis: signature of a good circuit (“golden signature” ) compared with the
signature of a “potentially” faulty circuit (“test signature”)
If “golden signature” matches “test signature” then the circuit is assumed to be
good,
else faulty
Desirable: signature of a good circuit and faulty circuits are different
Aliasing: During testing, it is possible that the signature of “good” circuit and “faulty” circuit
match
Due to information loss during compaction
32. BIST: Test Response Analyzer
Techniques to compute
Signature
Ones Counting: count number
of ones across all circuit
responses
Different permutations can
yield same signature
Modular LFSR: Extra XOR
gate at the input
Single Input Signature
Register (SISR)
Need to start with a
seed value
33. Built-In Self Test (BIST) Summary:
•Advantages
Lower cost of test, since the need for
external electrical testing using an ATE
will be reduced
No need to store test patterns
At-speed test can be done
Capability to perform tests outside the
production electrical testing
environment
•Disadvantages
Additional silicon area
Yield and Reliability decrease
Performance loss
Extra delays
Additional pin (and possibly
bigger package size)
requirements
34. Automatic Test Pattern Generation
Terminologies
General approach to ATPG
Redundant Faults
35. ATPG: Objective, Challenges and Practical Solution
•ATPG: Automatic Test Pattern Generator
Objective: Generate test patterns (test
• vectors) that can be used to detect faults
Desired: small set of test vectors that
detect all faults considered for that
circuit
•Challenges
For generalized sequential circuits,
generating test vectors/sequences is
very difficult
Reaching certain states may take
• exponential clock cycles
Finding the test sequence that controls
or observes an internal point in the
circuit is runtime intensive
Practical Solution
Sequential ATPG problem is transformed to Combinational ATPG problem by Scan
Design Flow
Combinational ATPG problem, though NP-complete, has efficient algorithms
36. ATPG: Terminologies
Path: sequence of pins in topological order
On-path input or on-input: for a given path, the input pins lying on that path
Side path inputs or side-inputs: The input pins other than the on-inputs of the instances
lying
on that path
37. ATPG: Controlling/Non-controlling values
Type of Gate
Controlling
Value
Non-
Controlling
Value
AND 0 1
NAND 0 1
OR 1 0
NOR 1 1
XOR Not Defined Any Value
Controlling value of a multi-input gate
Value that can be assigned to any input of the
gate such that the output is known irrespective
of values on other inputs
Non-controlling value of a multi-input gate
Value that can be assigned to any input of the
gate such that the output is decided by the
value on other inputs
39. ATPG: Illustration of Path Sensitization Method
Given: Stuck-at 1 at G4/X1
To Find: A test vector (value of A, B,
C, D) which will be able to detect the
existence of SA1 at G4/X1
Test Vector: (1,1,0,0)
Fault Sensitization: Find the value at input ports
that will set the value at the fault site opposite of
the fault value
Find A, B, C, D such that G4/X1=0 (A=1,
B=1)
Fault Propagation: For the path from the fault
site to the output port, set the value of side-
inputs to non-controlling inputs
Set G4/X2 to non-controlling value
(G4/X2=1)
Line Justification: Find the value at input ports
that will set the side-inputs as found in fault
propagation
Find A, B, C, D such that G4/X2=1 (C=0
D=0)
40. ATPG: Illustration of Backtracking
•Given: Stuck-at 0 at G3/Y
•To Find: A test vector to detect this fault.
Fault Sensitization
Find A, B, C, D such that G3/Y=1 (B=1,
C=0)
Fault Propagation: Path to Y
Set G5/X1 to non-controlling value (i.e. 1)
Line Justification: A=0, B=0
B=0 is in conflict!
Must be Backtracked
Fault Propagation: Path to Z
Set G6/X2 to non-controlling value (i.e. 0)
Line Justification: C=0 D=0
41. ATPG: Illustration of Redundant Fault
Given: Stuck-at 1 at pin G3/X1
To Find: A test vector to detect this fault
Fault Sensitization
Find A, B, C such that G3/X1=0 (B=0)
Fault Propagation:
For Propagation to Z: Set G3.X2=1
and G4/X1=0
Line Justification:
B=1 is in conflict with earlier B=0
No test vector exists to detect this fault
This is known as redundant fault
42. ATPG: Redundant Fault based Optimization
Redundant faults can be used to reduce the hardware
Redundant fault means that the behavior of the circuit with/without fault is the same
Assume that the fault site has constant 0/1 optimize out gates that are not required
Assume that SA1 at G3/X1 is always present.
G3/X1=1 implies that G3/Y =C
43. ATPG : Challenges and Solutions
•Complications
Primarily due to re-convergent fanouts
Decisions required to be taken at
a particular point
Decision leads to implications
Some decisions can be wrong (leading
to conflicts in decisions)
Backtracking required
•Backtracking Limit
Too many backtrack => possible
redundant fault
User defined Backtrack Limit employed by
tool
Example Backtrack Limit = 1000
Abort finding test vector when
backtrack limit is hit, i.e. when 1000
times backtracking has been done
Algorithmic Advancements
D-algorithm: Roth 1966
PODEM (Path-oriented Decision Making): Prabhu Goel 1981
FAN (Fanout-oriented) Algorithm: Fujiwara
