Direct Memory Access & Interrrupts

Direct Memory Access
By,
Sharmila Chidaravalli
Assistant Professor,
Department of CS&E,
AIeMS

Introduction
The direct memory access (DMA) I/O technique provides
direct access to the memory while the microprocessor is
temporarily disabled.
• A DMA controller temporarily borrows the address bus, data
bus, and control bus from the microprocessor and transfers the
data bytes directly between an I/O port and a series of memory
locations.
• The DMA transfer is also used to do high-speed memory-to
memory transfers.
• Used in disk controllers, video/sound cards etc, or between
memory locations.

Basic DMA operation
• Two control signals are used to request and acknowledge a
DMA transfer in the microprocessor-based system.
HOLD pin - is an input used to request a DMA action
HLDA pin - is an output that acknowledges the DMA action

•The HOLD signal is a bus request signal which asks the
microprocessor to release control of the buses after the current bus
cycle.
•HOLD is sampled in any clocking cycle
•when the processor recognizes the hold, it stops executing software
and enters hold cycles
• The HLDA signal is a bus grant signal which indicates that the
microprocessor has indeed released control of its buses by placing
the buses at their high-impedance states.
• The HOLD input has a higher priority than the INTR or NMI
interrupt inputs.

Basic DMA Definitions
Direct memory accesses normally occur between an I/O device
and memory without the use of the microprocessor.
DMA read - transfers data from the memory
to the I/O device
DMA write - transfers data from an I/O device
to memory
Memory & I/O are controlled simultaneously.
which is why the system contains separate memory and
I/O control signals

A DMA read causes the MRDC and IOWC signals to activate
simultaneously.
-transferring data from memory to the I/O device
A DMA write causes the MWTC and IORC signals to both
activate.
The control Buses are available to all microprocessors in the Intel
family expect 8086/8088.
8086/8088 require a controller or circuit for control bus signal
generation.

Data transfers are performed by the control circuit that is a part of the I/O device
interface called DMA controller
DMA controller can transfer data without intervention of the processor, but its
operation must be under the control of a program executed by the processor.
To initiate the transfer of a block words, the processor sends the starting address,
the number of words in the block and the direction of the transfer.
Data transfer speed is determined by speed of the memory device or a DMA
controller.
-if memory speed is 50 ns, DMA transfers occur at rates up to 1/50 ns or 20
M bytes per second
-if the DMA controller functions at a maximum rate of 15 MHz with 50 ns
memory, maximum transfer rate is 15 MHz because the DMA controller is
slower than the memory
In many cases, the DMA controller slows the speed of the system when transfers
occur.

• DMA is implemented using a DMA controller
– DMA controller
• Acts as slave to processor
• Receives instructions from processor
– Processor gives details to the DMA controller
» I/O device number
» Main memory Starting address
» Number of bytes to transfer
» Direction of transfer (memory  I/O device, or
vice versa)
• On receiving this information, the DMA controller proceeds to
perform the requested operation.
• After completing, it informs the processor

• Steps in a DMA operation
– Processor initiates the DMA controller
• Gives device number, memory buffer pointer, …
– Called channel initialization
• Once initialized, it is ready for data transfer
– When ready, I/O device informs the DMA controller
• DMA controller starts the data transfer process
– Obtains bus by going through bus arbitration
– Places memory address and appropriate control signals
– Completes transfer and releases the bus
– Updates memory address and count value
– If more to read, loops back to repeat the process
– Notify the processor when done
• Typically uses an interrupt

Interrupts
By,
Sharmila Chidaravalli
Assistant Professor,
Department of CS&E,
AIeMS

What Are Interrupts ?
Interrupts alter a program’s flow of control
∗ Behavior is similar to a procedure call
» Some significant differences between the two
• Interrupt causes transfer of control to an interrupt
service routine (ISR) or Interrupt Service Procedure
» ISR is also called a handler
• When the ISR is completed, the original program resumes
execution
• Interrupts provide an efficient way to handle unanticipated
events

Types of interrupts
∗ Software interrupts
∗ Hardware interrupts
∗ Exceptions

Interrupt Vector Table

The processor uses the interrupt vector to determine the address of
the ISR of the interrupting device.
In the 8088/8086 processor as well as in the 80386/80486/Pentium
processors operating in Real Mode (16-bit operation), the interrupt
vector is a pointer to the Interrupt Vector Table.
The Interrupt Vector Table occupies the address range from 00000H
to 003FFH (the first 1024 bytes in the memory map).
Each entry in the Interrupt Vector Table is 4 bytes long:
The first two represent the offset address and the last two the segment address
of the ISR.
The first 5 vectors are reserved by Intel to be used by the processor.
The vectors 5 to 255 are free to be used by the user.

• Interrupt numbers range from 0 to 255
• Interrupt number acts as an index into the interrupt vector table
• Since each vector takes 4 bytes, interrupt number is multiplied by 4
to get the corresponding ISR pointer
Example
• For interrupt 2, the memory address is 2 ∗ 4 = 8H
• The first two bytes at 8H are taken as the offset value
• The next two bytes (i.e., at address AH) are used as the CS value

Interrupt Types
Type 0: Divide error – Division overflow or division by zero
Type 1: Single step or Trap – After the execution of each instruction
when trap flag set
Type 2: NMI Hardware Interrupt – ‘1’ in the NMI pin
Type 3: One-byte Interrupt – INT3 instruction (used for
breakpoints)
Type 4: Overflow – INTO instruction with an overflow flag
Type 5: BOUND – Register contents out-of-bounds
Type 6: Invalid Opcode – Undefined opcode occurred in program
Type 7: Coprocessor not available – MSW indicates a coprocessor
Type 8: Double Fault – Two separate interrupts occur during the
same instruction
Type 9: Coprocessor Segment Overrun – Coprocessor call operand
exceeds FFFFH

Interrupt Types
Type 10: Invalid Task State Segment – TSS invalid (probably not
initialized)
Type 11: Segment not present – Descriptor P bit indicates segment
not present or invalid
Type 12: Stack Segment Overrun – Stack segment not present or
exceeded
Type 13: General Protection – Protection violation in 286 (general
protection fault)
Type 14: Page Fault – 80386 and above
Type 16: Coprocessor Error – ERROR΄ = ‘0’ (80386 and above)
Type 17: Alignment Check – Word/Doubleword data addressed at
odd location (486 and above)
Type 18: Machine Check – Memory Management interrupt
(Pentium and above)

Operation of a Real Mode Interrupt
Push Flags
Clear IF
Clear TF
Push CS
Push IP
Fetch ISR Address
Pop IP
Pop CS
Pop Flags
Mainline Program
ISR
Push Register
Pop Register
IRET

Operation of a Protected Mode Interrupt
In the 80386/80486/Pentium processors operating in the Protected
Mode (32-bit operation), the interrupt vector is a pointer to the
Interrupt Descriptor Table.
The Interrupt Descriptor Table can be located anywhere in the
memory.
Its starting address is pointed by the Interrupt Descriptor Table Register
(IDTR).
Each entry in the Interrupt Vector Table is 8 bytes long:
Four bytes represent the 32-bit offset address, two the segment selector and
the rest information such as the privilege level.
The first 32 vectors are reserved by Intel to be used by the
processor.
The vectors 33 to 255 are free to be used by the user.
0
2
4
6
1
3
5
7 Offset (A31 - A16)
Offset (A15 - A0)
Segment Selector
00H01110PFThe protected mode
interrupt descriptor

Exception Interrupts
Divide by zero error
CPU generates a type 0 interrupt whenever the div/idiv
instructions result in a quotient that is larger than the
destination specified or an attempt is made to divide by zero.
Single step Interrupt
∗ Useful in debugging
∗ To single step, Trap Flag (TF) should be set
∗ CPU automatically generates a type 1 interrupt after
executing each instruction if TF is set
∗ Type 1 ISR can be used to present the system state to
the user

Exception Interrupts
There exists no instruction to directly set or reset trap flag.
TF=1 can be set by executing the following sequence of instructions:
PUSHF
MOV BP,SP
OR WORD PTR[BP+0],0100H
POPF
TF=0 can be set by executing the following sequence of instructions:
PUSHF
MOV BP,SP
AND WORD PTR[BP+0],0FEFFH
POPF

Software Interrupts
Initiated by executing an instruction
INT, INTO, INT 3, BOUND
INT and INT3 behave in a similar way.
INT n:
- n is an integer from range 0 to 255
- Calls ISR located at vector n (n*4).
- The INT instruction requires two bytes of memory, opcode
plus n.
- Each interrupt type can be parameterized to provide
several services.
- For example, DOS interrupt service int 21H
provides more than 80 different services
∗ AH register is used to identify the required
service under int 21H.

BOUND and INTO are both conditional.
BOUND:
Bound AX,DATA
AX is compared with DATA and DATA+1, if less than an
interrupt occurs.
AX is compared with DATA+2 and DATA+3, if greater than an
interrupt occurs.
INTO:
Checks the overflow flag (OF). If OF=1, the ISR is called.
IRET removes 6 bytes from the stack, 2 for IP, 2 for CS and 2 for
FLAGS.

Hardware Interrupts
• Software interrupts are synchronous events
∗ Caused by executing the int
instruction
• Hardware interrupts are of hardware origin and
asynchronous in nature
∗ Typically caused by applying an
electrical signal to the processor chip
• Hardware interrupts can be
∗ Maskable (INTR)
∗ Non-maskable (NMI)
» Causes a type 2 interrupt

Non-Maskable Interrupt
Non-maskable interrupt is triggered by applying an electrical signal to
the NMI pin of Pentium
∗ Processor always responds to this signal
∗ Cannot be disabled under program control
The non-maskable interrupt (NMI) is an edge-triggered input that
requests an interrupt on the positive edge (0-to-1 transition).
after a positive edge, the NMI pin must remain logic 1 until
recognized by the microprocessor
before the positive edge is recognized, NMI pin must be logic 0
for at least two clocking periods
The NMI input is often used for parity errors and other major faults,
such as power failures.
power failures are easily detected by monitoring the AC power
line and causing an NMI interrupt whenever AC power drops out .

INTR and INTA
The INTR pin must be externally decoded to select a vector.
Any vector is possible, but the interrupt vectors between
20H and FFH are usually used (Intel reserves vectors
between 00H and 1FH).
INTA is an output of the microprocessor to signal the external
decoder to place the interrupt number on data bus connections
D7-D0.
The INTR pin is set by an external device (8259A) and cleared
in the ISR.
The input is automatically disabled by the microprocessor
once it is recognized and re-enabled by IRET or IRETD
instruction.

INTR: Interrupt Request. Activated by a peripheral device to
interrupt the processor.
Level triggered. Activated with a logic 1.
INTA: Interrupt Acknowledge. Activated by the processor to
inform the interrupting device the interrupt request (INTR) is
accepted.
Level triggered. Activated with a logic 0.

Direct Memory Access & Interrrupts

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Direct Memory Access & Interrrupts