Dv3
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This document provides a block diagram and component list for a computer motherboard. The block diagram shows the system architecture including major components like the CPU, chipset, memory slots, graphics, and I/O. It depicts the connections between components and power delivery. Tables provide details on the integrated pull-ups/downs for chipset pins and strap pin functions for the chipset.
![A
B
C
D
E
INTEL ICH8-M STRAP PIN
19,21 +RTCVCC
4,5,6,7,9,10,11,19,21,37,47
+RTCVCC
Usage/When Sampled
HDA_SDOUT
XOR Chain Entrance/
PCIE Port Config 1 bit1,
Rising Edge of PWROK
4
HDA_SYNC
PCIE Port Config 1 bit0,
Rising Edge of PWROK.
GNT2#
PCIE Port Config 2 bit0,
Rising Edge of PWROK.
Comment
Allows entrance to XOR Chain testing when TP3
pulled low at rising edge of PWROK.When TP3 not
pulled low at rising edge of PWROK,sets bit1 of
RPC.PC(Config Registers:offset 224h)
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
XOR Chain Entrance Strap
ICH_RSVD
tp3
AZ_DOUT_ICH
0
0
1
1
0
1
0
1
1D05V_S0
3,7,10,21,38 1D25V_S0
Signal
1D05V_S0
1D25V_S0
27 1D2V_LAN_S5
1D2V_LAN_S5
28 1D5V_NEW_S0
Description
RSVD
Enter XOR Chain
Normal Operation(default)
Set PCIE port cofig bit1
1D5V_NEW_S0
5,10,17,19,20,21,26,28,38,47
7,10,11,13,14,34,37,38
GNT3#
GNT0#
SPI_CS1#
INTVRMEN
3
Reserved
Top-Block Swap Override.
Rising Edge of PWROK.
Boot BIOS Destination
Selection.
Rising Edge of PWROK.
Integrated VccSus1_05
VccSus1_5 and VccCL1_5
VRM Enable/Disable.Always
sampled.
2D5V_LAN_S5
3D3V_AUD_S0
Sampled low:Top-Block Swap mode(inverts A16 for all A16 swap override strap
cycles targeting FWH BIOS space).
PCI_GNT#3 low = A16 swap override enable
Note: Software will not be able to clear the
high = default
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.
BOOT BIOS Strap
PCI_GNT#0 SPI_CS#1
BOOT BIOS Location
Controllable via Boot BIOS Destination bit
0
1
SPI
(Config Registers:Offset 3410h:bit 11:10).
PCI
1
0
GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.
1
Enables integrated VccSus1_05,VccSus1_5 and
VccCL1_5 VRM when sampled high
1
Enables integrated
when sampled high
PCIE LAN REVERSAL.Rising
Edge of PWROK.
This signal has weak internal pull-up.
set bit27 of MPC.LR(Device28:Function0:Offset D8)
SPKR
No Reboot.
Rising Edge of PWROK.
If sampled high, the system is strapped to the
"No Reboot" mode(ICH8M will disable the TCO Timer
system reboot feature). The status is readable
via the NO REBOOT bit.(Offset:3410h:bit5)
TP3
XOR Chain Entrance.
Rising Edge of PWROK.
This signal should not be pull low unless using
XOR Chain testing.
GPIO33/
HDA_DOCK_EN#
3D3V_LAN_S5
3D3V_S0
17,18,20,21,22,26,27,28,29,31,34,36,39,47
22,26,29,31,34,36
3D3V_S0
3D3V_S5
3D3V_S5
5V_AUX_S5
16,23,32,33,34,36,37,38
5V_AUX_S5
5V_S3
5V_S3
5V_S0
5V_S0
16,21,34,37,40 5V_S5
5V_S5
15,16,17,20,21,22,23,29,30,31,32,33,34,35,47
LPC(Default)
17,39,46,47 AD+
16,17,34,35,36,37,39,40,47
Low=Disable
AD+
DCBATOUT
DCBATOUT
13,14,38 DDR_VREF_S0
VccLAN1_05,VccCL1_05 VRM
LAN100_SLP
High=Enable
Low=Disable
DDR_VREF_S0
7,13,14,38 DDR_VREF_S3
DDR_VREF_S3
22,31,33,39 KBC_3D3V_AUX
Integrated VccLAN1_05
VccCL1_05 VRM enable
/Disable. Always sampled.
SATALED#
3D3V_AUX_S5
3,4,7,10,11,13,14,15,16,18,19,20,21,22,23,24,25,26,27,28,29,31,32,33,34,35,36,40,41,42,43,47
integrated VccSus1_05,VccSus1_5,VccCL1_5
SM_INTVRMEN High=Enable
3D3V_AUX_S5
27,28 3D3V_LAN_S5
integrated VccLan1_05VccCL1_05
LAN100_SLP
1D8V_S3
29,30 3D3V_AUD_S0
Weak Internal PULL-DOWN.NOTE:This signal should
not be pull HIGH.
4
1D5V_S0
1D8V_S3
27,28 2D5V_LAN_S5
Sets bit2 of RPC.PC(Config Registers:Offset 224h)
19,31,32,33,36,39,46
GPIO20
1D5V_S0
KBC_3D3V_AUX
16
DEFAULE HIGH
LCDVDD_S0
3
LCDVDD_S0
5,6,35 VCC_CORE_S0
VCC_CORE_S0
No Reboot Strap
SPKR
LOW = Defaule
High=No Reboot
Internal Pull-Up.If sampled low,the Flash Descriptor
Flash Descriptor Security Security will be overidden.if high,the Security
Override Strap
measures defined in the Flash Descriptor will be in
8.2K PULL HIGH
Rising Edge of PWROK.
effect.
This should only be used in manufacturing
environments
INTEL ICH8-M INTEGRATED
PULL-UPS and PULL-DOWNS
SIGNAL
Resistor Type/Value
HDA_BIT_CLK
PULL-DOWN 20K
HDA_RST#
NONE
HDA_SDIN[3:0]
PULL-DOWN 20K
HDA_SDOUT
PULL-DOWN 20K
HDA_SYNC
PULL-DOWN 20K
GNT[3:0]
PULL-UP 20K
GPIO[20]
PULL-DOWN 20K
LDA[3:0]#/FHW[3:0]#
PULL-UP 20K
LAN_RXD[2:0]
PULL-UP 20K
LDRQ[0]
PULL-UP 20K
LDRQ[1]/GPIO23
PULL-UP 20K
PME#
PULL-UP 20K
CFG 20
Normal Operation ★ Reserved Lane
Only PCIE or SDVO
PCIE and SDVO are
is operation ★
operation simultaneous
PWRBTN#
PULL-UP 20K
SATALED#
PULL-UP 20K
SDVO_CTRL_DATA
NO SDVO Card
Present ★
SPI_CS1#
PULL-UP 20K
SPI_CLK
PULL-UP 20K
XOR/ALL-Z
SPI_MOSI
PULL-UP 20K
Reserved
XOR Mode Enabled
All Z Mode Enabled
Normal Operation
SPI_MISO
PULL-UP 20K
Wistron Corporation
TACH_[3:0]
PULL-UP 20K
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
SPKR
PULL-DOWN 20K
TP[3]
PULL-UP 20K
USB[9:0][P,N]
PULL-DOWN 15K
CL_RST#
TBD
2
INTEL CRESTLINE STRAP PIN
CFG Strap
CFG 5
CFG 8
Low Power PCI Express
CFG 9
PCI Express Graphics
Lane Reversal
CFG 16
FSB Dynamic ODT
CFG 19
DMI Lane Reserved
Concurrent SDVO/PCIE
LOW 0
DMI X 2
DMI X 4 ★
Normal
★
Low Power mode
Lane Reversal
Disabled
SDVO Present
1
CFG 12
CFG 13
LL(00)
LH(01)
HL(10)
HH(11)
HIGH 1
Normal Mode(Lanes★
number in order)
Enabled ★
SDVO Card Present
2
<Core Design>
1
Title
Table of Content
Size
A3
Document Number
Rev
Pamirs-Discrete
Date: Wednesday, November 01, 2006
Sheet
2
SA
of
47](https://image.slidesharecdn.com/dv3-131021001825-phpapp02/85/Dv3-2-320.jpg)
![5
4
3
2
1
XDP Connector
CN2
7
H_A#[3..35]
U62A 1 OF 4
19
H_A20M#
H_FERR#
H_IGNNE#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
TP13
TP16
TP7
TP9
TP5
TP10
TP6
TP18
TP8
TP17
A6
A5
C4
D5
C6
B4
A3
TPAD28 TP4
CPU_RSVD11
M4
N5
T2
V3
B2
C3
D2
D22
D3
F6
B1
RSVD#M4
RSVD#N5
RSVD#T2
RSVD#V3
RSVD#B2
RSVD#C3
RSVD#D2
RSVD#D22
RSVD#D3
RSVD#F6
C1
F3
F4
G3
G2
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
G6
E4
H_HIT#
H_HITM#
BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
XDP_BPM#0
AD4
XDP_BPM#1
AD3
XDP_BPM#2
AD1
XDP_BPM#3
AC4
XDP_BPM#4
AC2
XDP_BPM#5
AC1
XDP_TCK
AC5
XDP_TDI
AA6
XDP_TDO
AB3
XDP_TMS
AB5
XDP_TRST#
AB6
C20 XDP_DBRESET#
CONTROL
1
H_LOCK#
H_DEFER#
7
H_DRDY# 7
H_DBSY# 7
H_BR0#
H_INIT#
7
THERMTRIP#
HCLK
BCLK0
BCLK1
XDP_BPM#3
XDP_BPM#2
R156
56R2J-4-GP
XDP_BPM#1
XDP_BPM#0
2
H4
PROCHOT#
THRMDA
THRMDC
STPCLK#
LINT0
LINT1
SMI#
CPU_RSVD01
CPU_RSVD02
CPU_RSVD03
CPU_RSVD04
CPU_RSVD05
CPU_RSVD06
CPU_RSVD07
CPU_RSVD08
CPU_RSVD09
CPU_RSVD10
H_IERR#
H_INIT#
BR0#
XDP_BPM#5
XDP_BPM#4
19
H_LOCK# 7
H_RESET#
7
H_RS#0 7
H_RS#1 7
H_RS#2 7
H_TRDY#
7
5 H_PWRGOOD_R
C7
1
R164
A22 CLK_CPU_BCLK
A21 CLK_CPU_BCLK#
XDP_TCK
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
NP1
61
2
62
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
63
64
NP2
D
1218
H_RESET#_R
R57 1 DY
XDP_DBRESET#_R
1 DY
R55
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE
2
68R3J-GP
2 1KR2F-3-GP
2
200R2F-L-GP
1
R64
1D05V_S0
H_RESET#
XDP_DBRESET#
CLK_CPU_XDP 3
CLK_CPU_XDP# 3
2
0R0402-PAD
(Place R1431 with in 200ps (~1") to CPU
STC-CONN60A-GP-U1
H_THERMDA
H_THERMDC
H_THERMTRIP#
C120
SCD1U16V2KX-3GP
XDP_DBRESET# 20
CPU_PROCHOT#
D21
A24
B25
XDP_HOOK1
1D05V_S0
H_HIT#
7
H_HITM# 7
THERMAL
A20M#
FERR#
IGNNE#
H_SMI#
H_A20M#
H_FERR#
H_IGNNE#
D20
B3
HIT#
HITM#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
ADSTB1#
IERR#
INIT#
RESET#
RS0#
RS1#
RS2#
TRDY#
ICH
19
19
19
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
H_BR0#
LOCK#
ADDR GROUP 1
H_ADSTB#1
19
19
19
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
C
7
K3
H2
K2
J3
L1
F1
7
7
7
1
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_DEFER#
H_DRDY#
H_DBSY#
DEFER#
DRDY#
DBSY#
H_ADS#
H_BNR#
H_BPRI#
1
1D05V_S0
2
7
7
7
7
7
H5
F21
E1
ADS#
BNR#
BPRI#
XDP/ITP SIGNALS
H_ADSTB#0
H1
E2
G5
H_ADS#
H_BNR#
H_BPRI#
RESERVED
7
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
ADSTB0#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
D
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
ADDR GROUP 0
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
0630 Connector Vendor :SmaTec
Part Number : QSH-030-01-F-D-TR
35
1D05V_S0
C
H_THERMDA 22
H_THERMDC 22
H_THERMTRIP# 7,19
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3
layout note:Zo =55
ohm , 0.5" MAX for
GTLREF
layout note : Change R237 to 649 ohm if using XTP to ITP adapter
3D3V_S0
R59
KEY_NC
XDP_DBRESET#
1
BGA479-SKT6-GPU3
2
1KR2J-1-GP
1D05V_S0
original value:BGA479-SKT6-GPU1
XDP_TDI
R61
XDP_TMS
B
R60
XDP_TDO
R63
XDP_BPM#5
R89
XDP_HOOK1
R75
1
2
1
2
1
2
1
2
1
2
54D9R2F-L1-GP
B
54D9R2F-L1-GP
54D9R2F-L1-GP
54D9R2F-L1-GP
54D9R2F-L1-GP
DY
XDP_TRST#
R58
1D05V_S0
XDP_TCK
2
1
2
51R2F-2-GP
54D9R2F-L1-GP
1
R74
1
R165
56R2J-4-GP
B
2
DY
CPU_PROCHOT#
E
C
DY
Q10
OCP#
20
MMBT3904WT1G-GP
A
<Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Meron(1/3)-AGTL+/XDP
Size
Custom
Date:
Document Number
Rev
SC
Pamirs-Discrete
Tuesday, December 19, 2006
Sheet
4
of
47](https://image.slidesharecdn.com/dv3-131021001825-phpapp02/85/Dv3-4-320.jpg)
![5
4
3
7 H_D#[0..63]
2
1
VCC_CORE_S0
U62B 2 OF 4
VCC_CORE_S0
U62C
3 OF 4
3 CPU_BSEL0
3 CPU_BSEL1
3 CPU_BSEL2
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
B22
B23
C21
COMP0
COMP1
COMP2
COMP3
E5
B5
D24
D6
D7
AE6
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
PSI#
R171
R172
R132
R131
1
1
1
1
2
2 27D4R2F-L1-GP
2 54D9R2F-L1-GP
2 27D4R2F-L1-GP
54D9R2F-L1-GP
H_DPRSTP#
7,19
H_DPSLP#
19
H_DPWR# 7
H_PWRGOOD 19
H_CPUSLP#
7
PSI#
35
R145
BGA479-SKT6-GPU3
PLACE C173
make sure
routing is
away other
close to the TEST4 PIN,
TEST3,TEST4,TEST5 trace
reference to GND and
noisy signals
166
200
CPU_BSEL2
0
0
CPU_BSEL1
2
H_PWRGOOD_R
4
1KR2J-1-GP
B
CPU_BSEL
1
Resistor Placed
within 0.5" of CPU
pin. Trace should
be at least 25 mils
away from any other
toggling signal .
COMP[0,2] trace
width is 18 mils.
COMP[1,3] trace
width is 4 mils .
CPU_BSEL0
1
1
1
0
D
1D05V_S0
R155 1
R146 1
C
2
2 0R2J-2-GP
0R2J-2-GP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
VCCA
VCCA
B26
C26
VID0
VID1
VID2
VID3
VID4
VID5
VID6
AD6
AF5
AE5
AF4
AE3
AF3
AE2
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
VCCSENSE
AF7
VCC_SENSE
VSSSENSE
AE7
VSS_SENSE
BGA479-SKT6-GPU3
TC7
1
DATA GRP2
R26
U26
AA1
Y1
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
BSEL0
BSEL1
BSEL2
COMP0
COMP1
COMP2
COMP3
H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
DY
1D5V_S0
layout note:
place C3 near
PIN B26
C298
VCC_SENSE
VSS_SENSE
CPU_VID[0..6]
35
VCC_SENSE
35
VSS_SENSE
35
1
2
R143 100R2F-L1-GP-U
1
DY
MISC
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
2
TPAD28 TP3
TPAD28 TP21
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
SCD01U16V2KX-3GP
2 C296
1
AD26
C23
D25
C24
AF26
AF1
A26
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DSTBN3#
DSTBP3#
DINV3#
H_DSTBN#2 7
H_DSTBP#2 7
H_DINV#2 7
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
2
V_CPU_GTLREF
TPAD28 TP19
TPAD28 TP22
TPAD28 TP20
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
1
SCD1U16V2KX-3GP
H_DSTBN#1
H_DSTBP#1
H_DINV#1
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
SE330U2VDM-6-GP
7
7
7
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#
DATA GRP1
DATA GRP1
C
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DSTBN2#
DSTBP2#
DINV2#
2
H_DSTBN#0
H_DSTBP#0
H_DINV#0
DATA GRP3
7
7
7
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
D
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
DATA GRP0
DATA GRP0
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
C303
SC10U10V5ZY-1GP
Length match within
25 mils . The trace
width/space/other is
20/7/25 .
B
VCC_CORE_S0
1
2
R142 100R2F-L1-GP-U
Close to CPU pin
within 500mils
SCD01U16V2KX-3GP
R423
2KR2F-3-GP
C602
1
V_CPU_GTLREF
<Core Design>
2
1 1
R422
1KR2F-3-GP
2
A
Close to CPU
pin AD26
Z0=55 ohm
with in
500mils .
2
1D05V_S0
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Meron(2/3)-AGTL+/PWR
Size
A3
Document Number
Rev
SC
Pamirs-Discrete
Date: Tuesday, December 19, 2006
Sheet
5
of
47](https://image.slidesharecdn.com/dv3-131021001825-phpapp02/85/Dv3-5-320.jpg)
![B6
E5
H_RS#0
H_RS#1
H_RS#2
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
E12
D7
D8
H_RS#0
H_RS#1
H_RS#2
2
1
R400
2
10KR2J-3-GP
CLKREQ#_B
1
R399
2
10KR2J-3-GP
TP49
TP54
TP51
TP55
TP56
TP48
TP52
TP50
TP57
CFG16
TP47
TP46
TP45
From Astro demo schematic
4
4
4
4
4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
TP53
CFG[17:3] have internal pull up
CFG[19:18] have internal pull down
CFG18
CFG19
CFG20
4
4
4
CRESTLINE-GP-U
layout note :
Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces
20 PM_BMBUSY#
5,19 H_DPRSTP#
13 PM_EXTTS#0
14 PM_EXTTS#1
4,19 H_THERMTRIP#
20,35 DPRSLPVR
R112
1
20,22 PM_PWROK
20,35 VGATE_PWRGD
1D05V_S0
R114
1
DY
PM_POK_R
2
2
0R2J-2-GP
1
1
2
H_SWNG
SA 0928
2
1
1
1
Layout Note :
Place C151 within 100 mils of NB
R163
100R2F-L1-GP-U
2
SCD1U16V2ZY-2GP
1
2
2
A
R168
24D9R2F-L-GP
2
2
1
C290
H_RCOMP
C295
SCD1U16V2ZY-2GP
SM_CS#0
SM_CS#1
SM_CS#2
SM_CS#3
BG20 DDR_CS0_DIMMA#
BK16 DDR_CS1_DIMMA#
BG16 DDR_CS2_DIMMB#
BE13 DDR_CS3_DIMMB#
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
13
13
14
14
BH18
BJ15
BJ14
BE16
M_ODT0
M_ODT1
M_ODT2
M_ODT3
BK31
BL31
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_RCOMP
SM_RCOMP#
BL15
BK14
SM_RCOMP
SM_RCOMP#
SM_VREF#AR49
SM_VREF#AW4
AR49
AW4
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
M_ODT0
M_ODT1
M_ODT2
M_ODT3
D
13
13
14
14
1D8V_S3
1
R154 1
R413
2
2 20R2F-GP
20R2F-GP
DDR_VREF_S3
DDR_VREF_S3
B42
C42
H48
H47
PEG_CLK
PEG_CLK#
K44 CLK_MCH_3GPLL
K45 CLK_MCH_3GPLL#
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
AN47
AJ38
AN42
AN46
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
AM47
AJ39
AN41
AN45
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
AJ46
AJ41
AM40
AM44
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#0
PM_EXT_TS#1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
1
R597
2
2K2R2J-2-GP
BJ51
BK51
BK50
BL50
BL49
BL3
BL2
BK1
BJ1
E1
A5
C51
B50
A50
A49
BK2
NC#BJ51
NC#BK51
NC#BK50
NC#BL50
NC#BL49
NC#BL3
NC#BL2
NC#BK1
NC#BJ1
NC#E1
NC#A5
NC#C51
NC#B50
NC#A50
NC#A49
NC#BK2
NC
NC
R157
2KR2F-3-GP
R162
221R2F-2-GP
H_VREF
G41
L39
L36
J36
AW49
AV20
N20
G36
13
13
14
14
13
13
14
14
AJ47
AJ42
AM39
AM43
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
CLK_MCH_3GPLL 3
CLK_MCH_3GPLL# 3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
20
20
20
20
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
20
20
20
20
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
20
20
20
20
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
20
20
20
20
C
2D5V_S0
R401
R402
2K2R2J-2-GP
2K2R2J-2-GP
DY
DY
ICH_SDVO_DATA
ICH_SDVO_CLK
GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VR_EN
E35
A39
C38
B39
E36
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
AM49
AK50
AT43
AN49
AM50
DFGT_VID0
DFGT_VID1
DFGT_VID2
DFGT_VID3
DFGT_VR_EN
TP44
TP11
TP15
TP12
TP14
B
1D25V_S0
0R2J-2-GP
1D05V_S0
R158
1KR2F-3-GP
PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_POK_R
PLT_RST_R#
H_THERMTRIP#
DPRSLPVR
P27
N27
N24
C21
C23
F23
N23
G23
J20
C20
R24
L23
J23
E23
E20
K23
M20
M24
L32
N33
L35
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
SM_RCOMP_VOH
SM_RCOMP_VOL
PM
PM
B
Layout Note :
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
BE29 DDR_CKE0_DIMMA
AY32 DDR_CKE1_DIMMA
BD39 DDR_CKE2_DIMMB
BG37 DDR_CKE3_DIMMB
CLK
PM_EXTTS#1
SM_CKE0
SM_CKE1
SM_CKE3
SM_CKE4
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
1
2
SCD01U25V2KX-3GP
2
C266
2
10KR2J-3-GP
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
1
5
5
5
5
H_RS#0
H_RS#1
H_RS#2
1
R407
AW30 M_CLK_DDR#0
BA23 M_CLK_DDR#1
AW25 M_CLK_DDR#2
AW23 M_CLK_DDR#3
1
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
SM_CK#0
SM_CK#1
SM_CK#3
SM_CK#4
DDR MUXING
1
SCD01U25V2KX-3GP
1
2
1
2
C257
SC2D2U10V3ZY-1GP
2
1
C253
5
5
5
5
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
PM_EXTTS#0
13
13
14
14
2
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
M14
E13
A11
H13
B12
3D3V_S0
RSVD#H10
RSVD#B51
RSVD#BJ20
RSVD#BK22
RSVD#BF19
RSVD#BH20
RSVD#BK18
RSVD#BJ18
RSVD#BF23
RSVD#BG23
RSVD#BC23
RSVD#BD24
RSVD#BJ29
RSVD#BE24
RSVD#BH39
RSVD#AW20
RSVD#BK20
RSVD#C48
RSVD#D47
RSVD#B44
RSVD#C44
RSVD#A35
RSVD#B37
RSVD#B36
RSVD#B34
RSVD#C34
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
2
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
DDR_A_MA14
DDR_B_MA14
3 MCH_CLKSEL0
3 MCH_CLKSEL1
3 MCH_CLKSEL2
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H10
B51
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23
BG23
BC23
BD24
BJ29
BE24
BH39
AW20
BK20
C48
D47
B44
C44
A35
B37
B36
B34
C34
AV29
BB23
BA25
AV23
2
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
L7
K2
AC2
AJ10
R149
1KR2F-3-GP
13 DDR_A_MA14
14 DDR_B_MA14
5
5
5
5
SM_CK0
SM_CK1
SM_CK3
SM_CK4
CL_CLK0 20
CL_DATA0 20
2
VGATE_PWRGD 20,35
0R2J-2-GP
CL_RST#
20
CLPWROK_MCH 1
R410
CL_VREF
R115
1KR2F-3-GP
1
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
RSVD#P36
RSVD#P37
RSVD#R35
RSVD#N35
RSVD#AR12
RSVD#AR13
RSVD#AM12
RSVD#AN13
RSVD#J12
RSVD#AR37
RSVD#AM36
RSVD#AL36
RSVD#AM37
RSVD#D20
DMI
M7
K3
AD2
AH11
P36
P37
R35
N35
AR12
AR13
AM12
AN13
J12
AR37
AM36
AL36
AM37
D20
R147
1KR2F-3-GP
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
1
H_VREF
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_SCOMP
H_SCOMP#
B9
A9
H_RESET#
H_CPUSLP#
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI#
4
H_BR0# 4
H_DEFER#
4
H_DBSY# 4
CLK_MCH_BCLK 3
CLK_MCH_BCLK# 3
H_DPWR# 5
H_DRDY# 4
H_HIT#
4
H_HITM# 4
H_LOCK#
4
H_TRDY#
4
FOR Calero: 80.6 ohm
Crestline: 20 ohm
U23B 2 OF 10
1D8V_S3
R148
3K01R2F-3-GP
SM_RCOMP_VOL
1
R116
392R2F-GP
C193
SDVO_CTRL_CLK
SDVO_CTRL_DATA
CLKREQ#
ICH_SYNC#
TEST1
TEST2
H35
K36
G39
G40
ICH_SDVO_CLK
ICH_SDVO_DATA
TP43
TP42
CLKREQ#_B
3
MCH_ICH_SYNC#
MCH_ICH_SYNC#
A37 TEST1_GMCH
R32 TEST2_GMCH
1
R406
2
20
1
2
R144
0R2J-2-GP
CFG9
2
H_SWING
H_RCOMP
K5
L2
AD13
AE13
SM_RCOMP_VOH
2
1
4
5
H_RESET#
H_CPUSLP#
B3
C2
W1
W2
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
3
4
SCD1U16V2KX-3GP
2
H_SCOMP
H_SCOMP#
H_ADS#
G12
H_ADSTB#0
H17
H_ADSTB#1
G20
H_BNR#
C8
H_BPRI#
E8
H_BR0#
F12
H_DEFER#
D6
H_DBSY#
C10
CLK_MCH_BCLK
AM5
CLK_MCH_BCLK#
AM7
H_DPWR#
H8
H_DRDY#
K7
H_HIT#
E4
H_HITM#
C6
H_LOCK#
G10
H_TRDY#
B7
H_A#[3..35]
GRAPHICS VID
2
H_SWNG
H_RCOMP
4
CFG
CFG
54D9R2F-L1-GP
1
R178
54D9R2F-L1-GP
2
1
R179
H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19
ME
1D05V_S0
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
MISC
C
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
1
D
E2
G2
G7
M6
H7
H3
G4
F3
N8
H2
M10
N12
N9
H5
P13
K9
M2
W10
Y8
V4
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
W3
N1
AD12
AE3
AD9
AC9
AC7
AC14
AD11
AC11
AB2
AD7
AB1
Y3
AC6
AE2
AC5
AG3
AJ9
AH8
AJ14
AE9
AE11
AH12
AJ5
AH5
AJ6
AE7
AJ7
AJ2
AE5
AJ3
AH2
AH13
RSVD
RSVD
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
C270
SC2D2U10V3ZY-1GP
1
2
U23A 1 OF 10
5
H_D#[0..63]
HOST
5
20KR2J-L2-GP
CRESTLINE-GP-U
Layout Note :
Place C153 near
pin B3 of NB
1
R598
ICH_SDVO_DATA
2
2K2R2J-2-GP
A
<Core Design>
R414
PLT_RST_R#
1
2
Wistron Corporation
PLT_RST1# 18,20,26,28,31,33,34,41
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
100R2J-2-GP
Title
CRESTLINE(1/6)-AGTL+/DMI/DDR2
Size
Document Number
Custom
Date: Monday, December 11, 2006
Sheet
7
Rev
SA
Pamirs-Discrete
of
47](https://image.slidesharecdn.com/dv3-131021001825-phpapp02/85/Dv3-7-320.jpg)
![5
4
3
DDR_A_D[0..63]
1
13
DDR_A_BS[0..2]
2
13
DDR_B_D[0..63]
14
DDR_B_DM[0..7]
DDR_A_DM[0..7]
D
14
DDR_B_BS[0..2]
14
13
DDR_A_DQS[0..7]
DDR_B_DQS[0..7]
DDR_A_DQS#[0..7]
B
A
BB19
BK19
BF29
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
SA_CAS#
BL17
DDR_A_CAS#
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
CRESTLINE-GP-U
14
U23E 5 OF 10
SA_BS0
SA_BS1
SA_BS2
DDR SYSTEM MEMORRY A
C
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_DQS#0
SA_DQS#1
SA_DQS#2
SA_DQS#3
SA_DQS#4
SA_DQS#5
SA_DQS#6
SA_DQS#7
AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
SA_RAS#
SA_RCVEN#
BE18
AY20
DDR_A_RAS#
SA_RCVEN#
SA_WE#
BA19
DDR_A_WE#
DDR_A_CAS# 13
DDR_A_RAS# 13
TP58
DDR_A_WE# 13
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BL9
BK5
BL5
BK9
BK10
BJ8
BJ6
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
SB_BS0
SB_BS1
SB_BS2
AY17
BG18
BG36
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
SB_CAS#
BE17
DDR_B_CAS#
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7
DDR SYSTEM MEMORY B
U23D 4 OF 10
AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BF48
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BD8
AY9
BG10
AW9
BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8
AN10
AT9
AN9
AM9
AN11
14
13
DDR_B_MA[0..13]
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
14
13
DDR_B_DQS#[0..7]
DDR_A_MA[0..13]
D
13
AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS#0
SB_DQS#1
SB_DQS#2
SB_DQS#3
SB_DQS#4
SB_DQS#5
SB_DQS#6
SB_DQS#7
AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
SB_RAS#
SB_RCVEN#
AV16
AY18
DDR_B_RAS#
SB_RCVEN#
BC17
DDR_B_WE#
SB_WE#
DDR_B_CAS# 14
C
DDR_B_RAS#
DDR_B_WE#
B
14
14
TP59
CRESTLINE-GP-U
<Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CRESTLINE(2/6)-DDR2 A/B CH
Size
A3
Document Number
Rev
SA
Pamirs-Discrete
Date: Wednesday, October 18, 2006
Sheet
8
of
47](https://image.slidesharecdn.com/dv3-131021001825-phpapp02/85/Dv3-8-320.jpg)
![5
4
3
1D05V_S0
L41
L43
N41
N40
D46
C45
D44
E42
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
G51
E51
F49
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
G50
E50
F48
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
E44
A47
A45
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
C
TVA_DAC
TVB_DAC
TVC_DAC
F27
J27
L27
TVA_RTN
TVB_RTN
TVC_RTN
M35
P33
TV_DCONSEL0
TV_DCONSEL1
TV
E27
G27
K27
B
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
K33
G35
E33
C32
F33
CRT_DDC_CLK
CRT_DDC_DATA
CRT_VSYNC
CRT_TVO_IREF
CRT_HSYNC
VGA
H32
G32
K29
J29
F29
E29
N43
M43
PEGCOMP trace
width and spacing
is 20/25 mils.
PEGCOMP
PEG_RX#0
PEG_RX#1
PEG_RX#2
PEG_RX#3
PEG_RX#4
PEG_RX#5
PEG_RX#6
PEG_RX#7
PEG_RX#8
PEG_RX#9
PEG_RX#10
PEG_RX#11
PEG_RX#12
PEG_RX#13
PEG_RX#14
PEG_RX#15
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
G44
B47
B45
PEG_COMPI
PEG_COMPO
PCI_EXPRESS GRAPHICS
D
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN
LVDS
J40
H39
E39
E40
C37
D35
K40
J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41
PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15
J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42
PEG_RXN15 41
PEG_RXN14 41
PEG_RXN13 41
PEG_RXN12 41
PEG_RXN11 41
PEG_RXN10 41
PEG_RXN9 41
PEG_RXN8 41
PEG_RXN7 41
PEG_RXN6 41
PEG_RXN5 41
PEG_RXN4 41
PEG_RXN3 41
PEG_RXN2 41
PEG_RXN1 41
PEG_RXN0 41
PEG_TX#0
PEG_TX#1
PEG_TX#2
PEG_TX#3
PEG_TX#4
PEG_TX#5
PEG_TX#6
PEG_TX#7
PEG_TX#8
PEG_TX#9
PEG_TX#10
PEG_TX#11
PEG_TX#12
PEG_TX#13
PEG_TX#14
PEG_TX#15
PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15
M45 TXP0
T38 TXP1
T46 TXP2
N50 TXP3
R51 TXP4
U43 TXP5
W42 TXP6
Y47 TXP7
Y39 TXP8
AC38 TXP9
AD47 TXP10
AC50 TXP11
AD43 TXP12
AG39 TXP13
AE50 TXP14
AH43 TXP15
C489
C506
C480
C195
C196
C502
C499
C487
C512
C491
C494
C189
C486
C482
C191
C483
C490
C507
C479
C194
C197
C501
C500
C488
C515
C492
C495
C190
C485
C481
C192
C484
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved
CFG[2:0] FSB Freq select
CFG5 (DMI select)
PEG_RXP15 41
PEG_RXP14 41
PEG_RXP13 41
PEG_RXP12 41
PEG_RXP11 41
PEG_RXP10 41
PEG_RXP9 41
PEG_RXP8 41
PEG_RXP7 41
PEG_RXP6 41
PEG_RXP5 41
PEG_RXP4 41
PEG_RXP3 41
PEG_RXP2 41
PEG_RXP1 41
PEG_RXP0 41
N45 TXN0
U39 TXN1
U47 TXN2
N51 TXN3
R50 TXN4
T42 TXN5
Y43 TXN6
W46 TXN7
W38 TXN8
AD39 TXN9
AC46 TXN10
AC49 TXN11
AC42 TXN12
AH39 TXN13
AE49 TXN14
AH44 TXN15
1
Strap Pin Table
1
2
R398 24D9R2F-L-GP
U23C 3 OF 10
2
0 = DMI x 2
1 = DMI x 4
CFG6
D
Reserved
0 = Reserved
1 = Mobile CPU
CFG7 (CPU Strap)
*
0 = Normal mode
1 = Low Power mode
CFG8 (Low power PCIE)
CFG9
(PCIE Graphics Lane Reversal)
*
0 = Reverse Lane
1 = Normal Operation
CFG[11:10]
*
Reserved
00
01
10
11
CFG[13:12] (XOR/ALLZ)
CFG[15:14]
=
=
=
=
Reserved
XOR Mode Enabled
All Z Mode Enabled
Normal Operation (Default)*
Reserved
0 = Disable
1 = Enable *
CFG16 (FSB Dynamic ODT)
PEG_TXP15 41
PEG_TXP14 41
PEG_TXP13 41
PEG_TXP12 41
PEG_TXP11 41
PEG_TXP10 41
PEG_TXP9 41
PEG_TXP8 41
PEG_TXP7 41
PEG_TXP6 41
PEG_TXP5 41
PEG_TXP4 41
PEG_TXP3 41
PEG_TXP2 41
PEG_TXP1 41
PEG_TXP0 41
*
CFG[18:17]
C
Reversed
SDVO_CTRLDATA
0 = No SDVO Device Present *
1 = SDVO Device Present
0 = Normal Operation
(Lane number in Order)
1 = Reverse lane
CFG19(DMI Lane Reversal)
*
0 = Only PCIE or SDVO is operational *
1 = PCIE/SDVO are operating simu.
CFG20(PCIE/SDVO consurrent)
PEG_TXN15 41
PEG_TXN14 41
PEG_TXN13 41
PEG_TXN12 41
PEG_TXN11 41
PEG_TXN10 41
PEG_TXN9 41
PEG_TXN8 41
PEG_TXN7 41
PEG_TXN6 41
PEG_TXN5 41
PEG_TXN4 41
PEG_TXN3 41
PEG_TXN2 41
PEG_TXN1 41
PEG_TXN0 41
B
CRESTLINE-GP-U
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
CRESTLINE(3/6)-VGA/LVDS/TV
Document Number
Rev
SA
Pamirs-Discrete
Date: Monday, December 18, 2006
Sheet
9
of
47](https://image.slidesharecdn.com/dv3-131021001825-phpapp02/85/Dv3-9-320.jpg)
![5
4
3
2
8 DDR_A_DQS#[0..7]
DM2
1
2
2
TC5
ST220U2VBM-3GP
1
1
2
1
C224
SCD1U16V2ZY-2GP
2
1
C231
SCD1U16V2ZY-2GP
2
1
C242
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
1
C217
SCD1U16V2ZY-2GP
SC2D2U16V5ZY-2GP
2
1
C272
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
DDR_VREF_S0
1
C227
C255
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
1
C216
2
1
C241
2
1
C204
2
1
C519
2
1
C523
2
1
C514
2
1
DY
C516
2
1
C509
2
1
DY
2
1
C511
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
1
DY
C498
2
C503
SCD1U16V2ZY-2GP
2
1
DY
B
Layout Note:
Place these resistors
closely DM1,all
trace length Max=1.5"
DDR_VREF_S0
SRN56J-4-GP
DDR_A_BS2
1
DDR_CKE0_DIMMA
2
RN55 SRN56J-4-GP
DDR_A_MA7
4
1
DDR_A_MA6
3
2
11
29
49
68
129
146
167
186
RN58 SRN56J-4-GP
1
4
2
3
4
3
RN11 SRN56J-4-GP
DDR_A_MA12
1
DDR_A_MA9
2
DDR_A_MA10
DDR_A_BS0
RN20 SRN56J-4-GP
1
4
2
3
4
3
RN56 SRN56J-4-GP
DDR_A_MA4
1
DDR_A_MA2
2
13
31
51
70
131
148
169
188
DDR_A_WE#
DDR_CS1_DIMMA#
RN23 SRN56J-4-GP
1
4
2
3
4
3
RN57 SRN56J-4-GP
DDR_A_MA0
1
DDR_A_BS1
2
M_ODT1
DDR_A_CAS#
RN26 SRN56J-4-GP
1
4
2
3
4
3
RN59 SRN56J-4-GP
M_ODT0
1
DDR_A_MA13
2
RN53 SRN56J-4-GP
DDR_CKE1_DIMMA 1
4
2
3
4
3
RN54 SRN56J-4-GP
1 DDR_A_MA14
DDR_A_MA11
2
DDR_VREF_S3
7
7
M_ODT0
M_ODT1
DDR_VREF_S3
114
119
DDR_CKE0_DIMMA 7
DDR_CKE1_DIMMA 7
30
32
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR0 7
M_CLK_DDR#0 7
164
166
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1 7
M_CLK_DDR#1 7
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
OTD0
OTD1
1
2
SC2D2U16V5ZY-2GP
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
CK1
CK1#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DDR_CS0_DIMMA# 7
DDR_CS1_DIMMA# 7
79
80
CK0
CK0#
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
10
26
52
67
130
147
170
185
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
ICH_SMBDATA
ICH_SMBCLK
SDA
SCL
195
197
VDDSPD
199
SA0
SA1
198
200
NC#50
NC#69
NC#83
NC#120
NC#163/TEST
50
69
83
120
163
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DDR_A_RAS# 8
DDR_A_WE# 8
DDR_A_CAS# 8
D
81
82
87
88
95
96
103
104
111
112
117
118
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
ICH_SMBDATA 3,14,20
ICH_SMBCLK 3,14,20
SCD1U16V2ZY-2GP
R416 1
R417 1
2 10KR2J-3-GP
2 10KR2J-3-GP
3D3V_S0
C569
PM_EXTTS#0 7
C571
SC2D2U6D3V3KX-GP
1D8V_S3
VREF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
202
GND
GND
201
MH1
MH1
MH2
MH2
C
B
1
DDR_A_RAS#
DDR_CS0_DIMMA#
C76
C82
2
RN17 SRN56J-4-GP
1
4
2
3
1
DDR_A_MA3
DDR_A_MA1
A
RN8
4
3
2
DDR_A_MA8
DDR_A_MA5
RN13 SRN56J-4-GP
1
4
2
3
110
115
CKE0
CKE1
DY
C262
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
2
DY
C251
2
1
C238
SC2D2U16V5ZY-2GP
C
SC2D2U16V5ZY-2GP
2
1
DY
C213
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
M_ODT0
M_ODT1
1D8V_S3
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
7 DDR_A_MA14
DDR_A_RAS#
DDR_A_WE#
DDR_A_CAS#
CS0#
CS1#
BA0
BA1
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
8 DDR_A_BS[0..2]
Layout Note:
Place near DM1
107
106
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
8 DDR_A_MA[0..13]
108
109
113
1
DDR_A_BS0
DDR_A_BS1
8 DDR_A_DQS[0..7]
RAS#
WE#
CAS#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
2
DDR_A_BS2
8 DDR_A_DM[0..7]
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
1
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
2
8 DDR_A_D[0..63]
D
1
A
<Core Design>
SCD1U16V2ZY-2GP
Wistron Corporation
DDR2-200P-20-GP-U
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
DDRII-SODIMM SLOT1
Size
Custom
Document Number
Rev
Pamirs-Discrete
Date: Wednesday, October 18, 2006
5
4
3
2
Sheet
13
1
SA
of
47](https://image.slidesharecdn.com/dv3-131021001825-phpapp02/85/Dv3-13-320.jpg)
![5
4
3
2
1
8 DDR_B_DQS#[0..7]
8 DDR_B_D[0..63]
DM1
8 DDR_B_DM[0..7]
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA0
DDR_B_BS1
SRN56J-4-GP
1
4
2
3
4
3
RN22
DDR_CS2_DIMMB#
DDR_B_RAS#
SRN56J-4-GP
1
4
2
3
4
3
RN24
DDR_B_WE#
DDR_B_CAS#
SRN56J-4-GP
1
4
2
3
4
3
RN27
DDR_CS3_DIMMB#
M_ODT3
1
2
RN9
DDR_B_MA14
SRN56J-4-GP
4
3
SRN56J-4-GP
1
4
2
3
DDR_B_MA12
DDR_B_MA9
RN7
RN14
198
200
NC#50
NC#69
NC#83
NC#120
NC#163/TEST
50
69
83
120
163
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
81
82
87
88
95
96
103
104
111
112
117
118
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
RN16
RN25
GND
201
MH1
MH2
MH2
1
2
1
SRN56J-4-GP
M_ODT2
1
DDR_B_MA13
2
RN6
SRN56J-4-GP
DDR_B_BS2
1
DDR_CKE2_DIMMB
2
DDR_VREF_S3
7
7
M_ODT2
M_ODT3
DDR_VREF_S3
SC2D2U16V5ZY-2GP
SCD1U16V2ZY-2GP
R420 1
R421 1
2 10KR2J-3-GP
2 10KR2J-3-GP
3D3V_S0
3D3V_S0
C578
PM_EXTTS#1 7
C577
SC2D2U6D3V3KX-GP
C
1D8V_S3
B
A
1
1
C77
2
C71
2
ICH_SMBDATA 3,13,20
ICH_SMBCLK 3,13,20
1
GND
SRN56J-4-GP
DDR_B_MA4
1
DDR_B_MA2
2
D
2
VREF
VSS
SRN56J-4-GP
DDR_B_MA7
1
DDR_B_MA6
2
SRN56J-4-GP
A
SA0
SA1
OTD0
OTD1
SRN56J-4-GP
DDR_B_MA5
1
DDR_B_MA8
2
RN12
4
3
VDDSPD
1
2
SRN56J-4-GP
DDR_CKE3_DIMMB
1
DDR_B_MA11
2
4
3
ICH_SMBDATA
ICH_SMBCLK
114
119
2
1
2
1
2
1
2
1
2
1
2
1
2
195
197
199
DDR_B_RAS# 8
DDR_B_WE# 8
DDR_B_CAS# 8
1
1
2
1
1
2
2
2
1
1
1
2
1
4
3
RN19
DDR_B_MA10
DDR_B_BS0
RN10
4
3
SDA
SCL
M_ODT2
M_ODT3
SCD1U16V2ZY-2GP
SRN56J-4-GP
1
4
2
3
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
RN21
DDR_B_MA3
DDR_B_MA1
10
26
52
67
130
147
170
185
13
31
51
70
131
148
169
188
C225
Layout Note:
Place these resistors
closely DM2,all
trace length Max=1.5"
DDR_VREF_S0
SRN56J-4-GP
1
4
2
3
M_CLK_DDR3 7
M_CLK_DDR#3 7
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
C183
B
RN18
M_CLK_DDR3
M_CLK_DDR#3
11
29
49
68
129
146
167
186
C215
SCD1U16V2ZY-2GP
2
1
C237
SCD1U16V2ZY-2GP
2
1
C243
SCD1U16V2ZY-2GP
2
1
C235
SCD1U16V2ZY-2GP
2
1
C226
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
C265
164
166
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SCD1U16V2ZY-2GP
C234
M_CLK_DDR2 7
M_CLK_DDR#2 7
CK1
CK1#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DY
C207
M_CLK_DDR2
M_CLK_DDR#2
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
DY
C184
30
32
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_VREF_S0
C256
DDR_CKE2_DIMMB 7
DDR_CKE3_DIMMB 7
CK0
CK0#
BA0
BA1
C
C245
CKE0
CKE1
107
106
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
DY
DDR_CS2_DIMMB# 7
DDR_CS3_DIMMB# 7
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
C221
SCD1U16V2ZY-2GP
2
1
C170
SCD1U16V2ZY-2GP
2
1
C513
SCD1U16V2ZY-2GP
2
1
C232
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
2
1
C497
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
2
C244
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
79
80
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DY
C508
110
115
DDR_B_BS0
DDR_B_BS1
7 DDR_B_MA14
C541
CS0#
CS1#
C264
1D8V_S3
DY
DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#
DDR_B_BS2
8 DDR_B_BS[0..2]
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
2
Layout Note:
Place near DM2
108
109
113
DY
8 DDR_B_MA[0..13]
D
RAS#
WE#
CAS#
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
8 DDR_B_DQS[0..7]
202
MH1
<Core Design>
Wistron Corporation
SCD1U16V2ZY-2GP
DDR2-200P-21-GP-U
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
DDRII-SODIMM SLOT2
Size
Custom
Date:
5
4
3
2
Document Number
Rev
Pamirs-Discrete
Wednesday, October 18, 2006
Sheet
1
14
SA
of
47](https://image.slidesharecdn.com/dv3-131021001825-phpapp02/85/Dv3-14-320.jpg)
![5
4
3
PCI_AD[0..31]
24 PCI_AD[0..31]
PCI_FRAME#
PCI_GNT1#
PCI_REQ1#
PCI_REQ2#
8
7
6
5
SRN8K2J-4-GP
RN65
1
2
3
4
PCI_GNT3#
PCI_REQ3#
PCI_SERR#
PCI_PIRQG#
8
7
6
5
SRN8K2J-4-GP
RN68
1
2
3
4
PCI_GNT#0
PCI_PIRQA#
PCI_PLOCK#
PCI_PERR#
8
7
6
5
1
2
3
4
1
2
3
4
SRN8K2J-4-GP
RN67
PCI_IRDY#
8
7 PCI_TRDY#
6 PCI_PIRQE#
PCI_PIRQD#
5
1
2
3
4
C
SRN8K2J-4-GP
RN69
8 PCI_PIRQH#
PCI_PIRQC#
7
PCI_PIRQB#
6
5 PCI_REQ#0
D20
E19
D19
A20
D17
A21
A19
C19
A18
B16
A12
E16
A14
G16
A15
B6
C11
A9
D11
B12
C12
D10
C7
F13
E11
E13
E12
D8
A6
E8
D6
A3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
RN61
1
2
3
4
F9
B5
C5
A10
PIRQA#
PIRQB#
PIRQC#
PIRQD#
SRN8K2J-4-GP
RN63
8 PCI_PIRQF#
7 PCI_GNT2#
6 PCI_DEVSEL#
5 PCI_STOP#
24
PCI_PIRQA#
24
1
3
U32C OF 6
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
3D3V_S0
D
2
PCI_PIRQC#
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
GNT3#/GPIO55
REQ3#/GPIO54
A4
D7
E18
C18
B19
F18
C10
A11
C/BE0#
C/BE1#
C/BE2#
C/BE3#
C17
E15
F16
E17
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
FRAME#
PLOCK#
SERR#
STOP#
TRDY#
C8
D9
G6
D16
A7
A17
B7
F10
C16
C9
PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_FRAME#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PLTRST#
PCICLK
PME#
AG24
B10
G7
PCI_PLTRST#
CLK_PCI_ICH
PCI
PCI_REQ1#
PCI_GNT1#
PCI_REQ2#
PCI_GNT2#
PCI_GNT3#
PCI_REQ3#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
F8
G11
F12
B3
TP78
D
TP80
TP90
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3
R486
1
Interrupt I/F
PCI_REQ#0 24
PCI_GNT#0 24
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
24
24
24
24
PCI_IRDY# 24
PCI_PAR 24
PCI_DEVSEL# 24
PCI_PERR# 24
PCI_FRAME# 24
PCI_SERR# 24,31
PCI_STOP# 24
PCI_TRDY# 24
CLK_PCI_ICH 3
ICH_PME# 24
8K2R2J-3-GP
2
3D3V_S5
1218
C
ICH8-M-1-GP-U
3D3V_S5
U43A
14
SRN8K2J-4-GP
PCI_PCIRST#
1
3
PCIRST1# 24,27
1
2
SSLVC08APWR-GP
1
7
PCI_GNT3#
R257
100KR2J-1-GP
1KR2J-1-GP
1 R255
0R2J-2-GP
DY
2
2
Boot BIOS Strap
DY
B
PCI_GNT0#
SPI_CS#1
2
R236
B
Boot BIOS Location
3D3V_S5
SPI
1
0
PCI
1
A16 swap override Strap
1
U43B
4
6
Low= A16 swap override Enable
High= Default *
LPC *
3D3V_S5
PCI_GNT#0
2
R260
1
0R2J-2-GP
DY
1KR2J-1-GP
DY
1 1
1
DY
2
R465
10KR2J-3-GP
2
DY
PCI_PLTRST# 23
2
R237
R235
10R2J-2-GP
SC8P250V2CC-GP
SSLVC08APWR-GP
R264
100KR2J-1-GP
1
CLK_PCI_ICH
C357
PLT_RST1# 7,20,26,28,31,33,34,41
1
2
Place closely pin B10
A
PLT_RST1#
5
7
PCI_GNT3#
PCI_PLTRST#
2
1
14
0
20
SPI_CS1#
SPI_CS1#
<Core Design>
DY
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
ICH8(1/4)-PCI/INT
Size
A3
Document Number
Date: Monday, December 18, 2006
5
4
3
2
Rev
SA
Pamirs-Discrete
Sheet
1
18
of
47](https://image.slidesharecdn.com/dv3-131021001825-phpapp02/85/Dv3-18-320.jpg)
![5
4
3
2
1
+RTCVCC
3D3V_S0
LAN100_SLP
2
330KR2F-L-GP
ICH_INTVRMEN
2
330KR2F-L-GP
RN64
+RTCVCC
1
U32A OF 6
LPC_LAD[0..3]
INTRUDER#
AF25
AD21
INTVRMEN
LAN100_SLP
ICH_INTVRMEN
LAN100_SLP
B24
TP77
SC15P50V2JN-2-GP
LAN_TXD0
LAN_TXD1
LAN_TXD2
AH21
R451
1
1D5V_S0
RN62
1
2
4
3
GLAN_COMP
2
24D9R2F-L-GP
HDA_BITCLK
D25
C25
AJ16
AJ15
SRN33J-5-GP-U
G9
E6
LPC_DRQ0#
1
2
4
3
R459
H_FERR#
TP91
TP92
2
1
56R2J-4-GP
SATA_TXN0_C
SATA_TXP0_C
B
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AB7
AC6
1 R499
2
24D9R2F-L-GP
IGNNE#
AF27
H_IGNNE#
H_IGNNE# 4
INIT#
INTR
RCIN#
AE24
AC20
AH14
H_INIT#
KBRST#
H_INIT# 4
H_INTR 4
KBRST# 31
NMI
SMI#
AD23
AG28
H_NMI
H_SMI#
H_NMI 4
H_SMI# 4
AA24
H_STPCLK#
H_STPCLK# 4
AE27
THRMTRIP_ICH#
TP65
TP8
AA23
1
2
R188
within 2" from R184
C
IDE_PDD[0..15]
IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15
H_THERMTRIP# 4,7
24R2J-GP
V1
U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6
AA4
AA1
AB3
Y6
Y5
placed within 2" from ICH8M
IDE_PDCS1# 23
IDE_PDCS3# 23
W4
W3
Y2
Y3
Y1
W5
23
IDE_PDA0 23
IDE_PDA1 23
IDE_PDA2 23
DCS1#
DCS3#
SATARBIAS#
SATARBIAS
TP67
R182
56R2J-4-GP
DA0
DA1
DA2
Within 500 mils
H_DPSLP#
1D05V_S0
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
SATA_CLKN
SATA_CLKP
AG1
AG2
3 CLK_PCIE_SATA#
3 CLK_PCIE_SATA
H_PWRGOOD 5
H_DPSLP# 5
H_FERR# 4
DIOR#
DIOW#
DDACK#
IDEIRQ
IORDY
DDREQ
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA
SC3900P50V2KX-2GP
2
SC3900P50V2KX-2GP
2
H_PWRGOOD
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
AF2
AF1
AE4
AE3
C372 1
C373 1
AD24
AG29
SATALED#
AF6
AF5
AH5
AH6
SATA_LED#
TP64
H_DPRSTP# 5,7
FERR#
HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34
AF10
GAP-OPEN TP85
16
HDA_SDOUT
AE10
AG14
2
H_DPRSTP#
H_DPRSTP#
THRMTRIP#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
G72
1
KBGA20 31
H_A20M# 4
H_A20M#
H_DPSLP#
H_FERR#
HDA_RST#
AE13
SRN33J-5-GP-U
AF26
AE26
CPUPWRGD/GPIO49
HDA_BIT_CLK
HDA_SYNC
AG3
AG4
AJ4
AJ3
RN66
AF13
AG26
DPRSTP#
DPSLP#
GLAN_COMPI
GLAN_COMPO
AJ17
AH17
AH15
AD13
HDA_SDIN0
23 SATA_RXN0_C
23 SATA_RXP0_C
23 SATA_TXN0
23 SATA_TXP0
LDRQ0#
LDRQ1#/GPIO23
1D05V_S0
LPC_FRAME# 31,33,34
STPCLK#
GLAN_DOCK#/GPIO13
AE14
29 HDA_RST#_CODEC
29 HDA_SDOUT_CODEC
LPC_FRAME#
1
C333
SC15P50V2JN-2-GP
29
C4
SRN10KJ-5-GP
2
1
2
1
2
1031 SA
29 HDA_BITCLK_CODEC
29 HDA_SYNC_CODEC
FWH4/LFRAME#
A20GATE
A20M#
LAN_RXD0
LAN_RXD1
LAN_RXD2
4
C
4
3
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LAN_RSTSYNC
D21
E20
C20
X2
X-32D768KHZ-40GPU
E5
F5
G8
F6
GLAN_CLK
C21
B21
C22
3
LPC
2
RTCRST#
AD22
D22
C329
2
1
2
1
SC1U10V3KX-3GP
2
C624
ICH_RTCX2
1
2
R198 10MR2J-L-GP
AF23
SM_INTRUDER#
G69
GAP-OPEN
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
RTCX1
RTCX2
CPU
ICH_RTCX1
AG25
AF24
ICH_RTCRST#
2
20KR2J-L2-GP
1
1
R466
1
KBGA20
KBRST#
31,33,34
D
ICH_RTCX1
ICH_RTCX2
IDE
1
R452
RTC
D
SM_INTRUDER#
2
1MR2J-1-GP
LAN/GLAN
1
R461
IHDA
1
R467
IDE_PDIOR# 23
IDE_PDIOW# 23
IDE_PDDACK# 23
INT_IRQ14 23
IDE_PDIORDY 23
IDE_PDDREQ 23
3D3V_S0
IDE_PDIORDY
1
R507
2
4K7R2J-2-GP
INT_IRQ14
1
R491
2
8K2R2J-3-GP
B
ICH8-M-1-GP-U
20.F0736.003
ETY-CON3-1-GP
3D3V_AUX_S5
4
+RTCVCC
U25
BATT1.1
1
2
3
2
W=20mils
1
1
R457
A
W=20mils
3
W=20mils
1
CH715FPT-GP
1
R202
2
W=20mils
5
1KR2J-1-GP
RTC1
2
C625
SC1U10V3ZY-6GP
2
100R2J-2-GP
XOR CHAIN ENTRANCE STRAP : RSVD
<Core Design>
A
3D3V_S0
Wistron Corporation
R484
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
1KR2J-1-GP
1
2
HDA_SDOUT_CODEC
Title
ICH8(2/4) LAN,HD,IDE,LPC
DY
Size
A3
Document Number
Rev
Pamirs-Discrete
Date: Wednesday, December 13, 2006
5
4
3
2
Sheet
1
19
SA
of
47](https://image.slidesharecdn.com/dv3-131021001825-phpapp02/85/Dv3-19-320.jpg)
![IDE_PDD[0..15]
SATA HD Connector
CD-ROM CONNECTOR
3D3V_S0
CDROM_LED# 1
R518
INT_IRQ14
2
8K2R2J-3-GP
1
51
C681 1
4
2SATA_RXN0
5
SATA_RXP0 1
6
SC3900P50V2KX-2GP
7
SC3900P50V2KX-2GP SATA_RXP0_C 19
2
C679
8
9
10
11
12
100 mil
19 IDE_PDDREQ
19 IDE_PDIOR#
13
14
5V_S3
15
5V_USB1_S3
17
18
19 IDE_PDA2
19 IDE_PDCS3#
1
19
20
21
22
1
C684
SC10U10V5ZY-1GP
SYN-CONN22A-GP-U2
1
5V_S0
24
20.F0817.022
CD_AUDL 29
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
2
2
C462
SCD1U16V2ZY-2GP
1
FUSE-2A8V-3GP
2
2
19 IDE_PDDACK#
16
100 mil
2
F2
1
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
IDE_PDA2
34
36
38
40
42
44
DY
46
C685
C686
48
50
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP NP2
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15
CD_AGND 29
RSTDRV#_5
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0
3D3V_S0
1
SATA_TXP0 19
R270
4K7R2J-2-GP
2
2
19 SATA_RXN0_C
NP1
2
29 CD_AUDR
3
19 SATA_TXN0
1
R267
CDROM1
HDD1
23
1
1
2
4K7R2J-2-GP
3D3V_S0
C355
SCD1U16V2ZY-2GP
2
C656
SC10U10V5ZY-1GP
2
SCD1U16V2ZY-2GP
2
1
C669
2
C657
SC10U10V5ZY-1GP
5V_S0
1
1
5V_S0
19
IDE_PDIOW#
19
IDE_PDIORDY
19
INT_IRQ14 19
IDE_PDA1 19
IDE_PDA0 19
IDE_PDA1
IDE_PDA0
IDE_PDCS1# 19
CDROM_LED# 16
5V_S0
primary channel:low
52
TYCO-CONN50-4R-GP-U
20.80353.050
USB PORT
3
HDMI_1_TXC
13
2
2
C570
2
C572
3D3V_S0
TC21
SE100U16VM-L1-GP
3
2
D14
2
HDMI_1_TXC#
HDMI_TXC#
HDMI_HDP
3
DY
BAV99PT-GP-U
SKT2
20
4
1
5V_USB1_S3
1
HDMI_1_TXD1
HDMI_TXD1
TSAHCT08PWR-1GP
1
1
1
7
PCI_PLTRST#
SCD1U16V2ZY-2GP SC1000P50V3JN-GP
43
43
2
FUSE-1D1A6V-8GP
HDMI_1_TXD2#
HDMI_TXD2#
18
100 mil
4
1
43
1
RSTDRV#_5
11
5V_USB2_S3
F3
L57
ACM2012H-900-GP
ACM2012H-900-GP
L56
U68D
12
5V_S3
4
HDMI_TXC
1
43
5V_S0
14
HDMI_1_TXD2
HDMI_TXD2
2
43
L54
ACM2012H-900-GP
1
USB_PN0
R181
2
0R0402-PAD
USB_1-
USB1
22
12
10
9
8
7
6
5
4
3
2
20
43
HDMI_1_TXD2#
HDMI_1_TXD1
3
2
HDMI_1_TXD2
HDMI_1_TXD1#
HDMI_TXD1#
HDMI_1_TXD1#
HDMI_1_TXD0
HDMI_1_TXD0#
HDMI_1_TXC
42
HDMI_1_TXD0
42
42
TP60
HDMI_SCL
HDMI_SDA
5V_S0
HDMI_1_TXC#
1
2
R364
0R2J-2-GP
HDMI_SCL
HDMI_SDA
HDP
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
4A
3A
1
USB_PP0
2
150R2J-L1-GP-U
1
B
NUMLK_LED
C
R1
R2
PDTC124EU-1-GP
USB_1-
R85
1A
42
11
NUMLK_LED#
ACES-CON10-5-GP
E
HDMI_HDP
HDMI_HDP
1
2
L16
1
2
BLM15AG221SN-GP
20.F0735.010
HDP
<Core Design>
10KR3F-L-GP
R71
100KR3J-L-GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
1
SKT-HDMI23P-GP
4
1
R367
Q22
23
1
USB_1+
5V_USB2_S3
ACM2012H-900-GP
L55
HDMI_TXD0#
2
0R0402-PAD
USB_1+
21
43
R180
31
2A
USB_PN3
USB_PP3
USB_PN2
USB_PP2
5V_S3
20
2
3
HDMI_TXD0
2
43
HDMI_CEC
20
20
20
20
1
Title
HD/CDROM/USB
HDMI_1_TXD0#
Size
A3
Document Number
Date: Tuesday, December 12, 2006
Rev
Pamirs-Discrete
Sheet
23
of
SA
47](https://image.slidesharecdn.com/dv3-131021001825-phpapp02/85/Dv3-23-320.jpg)
![4
3
3D3V_S0
1
PCI_AD25
18
18
2
C723
SCD1U16V2ZY-2GP
GBRST#
18,27 PCIRST1#
PCLK_PCM
18
ICH_PME#
2
20,31,34 PM_CLKRUN#
R584
1
R554
2
2
1
DY 0R2J-2-GP
0R0402-PAD
1
SHIELD
GND
R553
10KR2J-3-GP
AGND1
AGND2
AGND3
AGND4
AGND5
99
102
103
107
111
PCICLK
70
117
R579
4K7R2J-2-GP
HWSPND#
69
MSEN
58
XDEN
55
UDIO5
57
UDIO3
UDIO4
8
7
6
5
60
72
DY
EC87
SCD1U16V2ZY-2GP
56
UDIO0/SRIRQ#
1
2
3
4
2
3D3V_S0
100KR2J-1-GP
65
59
UDIO2
1
R589
1
RN75
UDIO1
PME#
3D3V_S0
SRN10KJ-6-GP
INT_SERIRQ
B
20,31,34
INTA#
115
PCI_PIRQA# 18
INTB#
116
PCI_PIRQC#
18
1394 : INTA#
4in1 : INTB#
TEST
66
CLKRUN#
R555
R585
100KR2J-1-GP
A
2
1
2
1
GBRST#
PCIRST#
C
3D3V_S0
1
71
119
4
13
22
28
54
62
63
68
118
122
1KR2J-1-GP
DY
R5C833-GP
DY
1
REQ#
GNT#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
2
124
123
23
24
25
26
29
30
31
PCI_C/BE#3
PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#1
PCI_C/BE#0
PCI_C/BE#0
1
2 R5C834_IDSEL
R562
10R2J-2-GP
PCI_REQ#0
PCI_GNT#0
18 PCI_FRAME#
18
PCI_IRDY#
18
PCI_TRDY#
18 PCI_DEVSEL#
18
PCI_STOP#
18
PCI_PERR#
18,31 PCI_SERR#
1 2
R571
10KR2J-3-GP
18
18
18
18
86
2
PCI_PAR
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
PAR
C/BE3#
C/BE2#
C/BE1#
C/BE0#
IDSEL
121
18
125
126
127
1
2
3
5
6
9
11
12
14
15
17
18
19
36
37
38
39
40
42
43
44
46
47
48
49
50
51
52
53
33
7
21
35
45
8
C746
SC10U10V5ZY-1GP
2
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
18 PCI_AD[0..31]
3
VCC_ROUT1
VCC_ROUT2
VCC_ROUT3
VCC_ROUT4
VCC_ROUT5
VCC_MD
C
B
VCC_RIN
16
34
64
114
120
D
C714
2
61
VCC_3V
PCI / OTHER
1
C747
VCC_PCI1
VCC_PCI2
VCC_PCI3
VCC_PCI4
VCC_PCI5
VCC_PCI6
67
SCD01U16V2KX-3GP
10
20
27
32
41
128
1
2
SCD01U16V2KX-3GP
1
SCD01U16V2KX-3GP
C743
SCD01U16V2KX-3GP
SCD47U16V3ZY-3GP
C744
2
C707
SCD47U16V3ZY-3GP
1
2
2
C717
SCD1U16V2ZY-2GP
SCD01U16V2KX-3GP
2
1
1
C705
2
C742
VCC_ROUT
2
C710
SC10U10V5ZY-1GP
DY
C715
1
1
3D3V_S0
SCD01U16V2KX-3GP
2
1
2
C728
SCD01U16V2KX-3GP
2
1
SCD01U16V2KX-3GP
2
1
1
1
C730
SC10U10V5ZY-1GP
2
D
3D3V_S0
IC1B
C734
1
1
3D3V_S0
2
2
5
C706
SC10P50V2JN-4GP
<Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
R5C832/PCI
Size
A3
Document Number
Rev
Pamirs-Discrete
Date: Wednesday, December 06, 2006
Sheet
24
of
SA
47](https://image.slidesharecdn.com/dv3-131021001825-phpapp02/85/Dv3-24-320.jpg)
![2
GAP-CLOSE-PWR
33
KBCBIOS_RD# 150
KBCBIOS_WE# 151
KBCBIOS_CS# 173
152
KBC_D[0..7]
KBC_D0 138
KBC_D1 139
KBC_D2 140
KBC_D3 141
KBC_D4 144
KBC_D5 145
KBC_D6 146
KBC_D7 147
Add Label "VCC"
G70
E51_TXD
2
GAP-CLOSE-PWR
Add Label "TXD"
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
G71
E51_RXD
2
GAP-CLOSE-PWR
1
Add Label "RXD"
5V_S0
0126
G73
1
2
GAP-CLOSE-PWR
32
5V_S0
RN51 32
TDATA_5
TCLK_5
4
3
2
1
B
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
5
6
7
8
SRN10KJ-6-GP
1
2
2
X-bus
ROM
KB3910
PS/2
D
2
2
2
XCLKO
XCLKI
D0
D1
D2
D3
D4
D5
D6
D7
41
28
27
25
24
23
DOCK_IN# 17
ECSMI# 20
WIFI_RF_EN 26
PM_CLKRUN# 20,24,34
BLON_OUT 16
NUMLK_LED 23
98
97
94
93
92
91
BLUETOOTH_EN 32
GPIOI2D
GPIO2F
GPIO2E
GPIO2C
GPIO2B
GPIO2A
RD#
WR#
MEMCS#
IOCS#
PSDAT3
PSCLK3
PSDAT2
PSCLK2
PSDAT1
PSCLK1
R492
10KR2J-3-GP
KBC_3D3V_AUX
KBC_MATRIX1
KBC_MATRIX0
155
149
148
119
118
109
108
107
106
105
86
85
75
70
69
63
62
55
54
48
22
21
20
12
11
8
6
5
4
3
GPIO1F
GPIO1E
GPIO1D
GPIO1C
GPIO1B
GPIO1A
LPC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
1
1
2
1
160
158
163
164
169
170
SCL1
SDA1
SCL2
SDA2
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
R498
DUMMY-R2
GPIO29
GPIO28
GPIO27
GPIO26
GPIO25
GPIO24
GPIO23
GPIO22
GPIO21
GPIO20
GPIO19
GPIO18
GPIO17
GPIO16
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO09
GPIO08
GPIO07
GPIO06
GPIO05
GPIO04
GPIO03
GPIO02
GPIO01
GPIO00
KB Matrix
LFRAME#
LCLK
SERIRQ
117
116
115
114
111
110
R494
10KR2J-3-GP
GPIO0F
GPIO0E
GPIO0D
GPIO0C
GPIO0B
GPIO0A
LAD0
LAD1
LAD2
LAD3
124
125
126
127
128
131
132
133
143
142
135
134
130
129
121
120
113
112
104
103
1
2
4
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7
KROW8
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68
153
154
U42
168
175
171
165
162
156
TP102
TP104
GPIO13
E51_TXD
E51_RXD
E51CS#
2
10KR2J-3-GP
E51CS#
TP_BTN# 32
CHG_ON# 39
AD_OFF 46
EAPD
29,30,32
E51_TXD 26
E51_RXD 26
1 R500
1 R512
2
10KR2J-3-GP
BT_TH
1
2
R528
DUMMY-R2
TP101
Pull-up by devided-resistor to MAX8725_LDO
TP_LED 16
PWR_LED 16
3D3V_S5
VOL_DWN_DK# 17
VOL_UP_DK# 17
SB_PWR_BTN# 2
1
PM_SLP_S4# 17,20,28,36,37,38
R242
DY 10KR2J-3-GP
GPIO13
ICH8 integrated pull-up
CAPS_LED 16
CAP_ACK 32
CAP_XPRES 32
CAP_DAT 32
R243
S5_ENABLE
1
2
10KR2J-3-GP
C
FAN3FB
FAN3PWM
KBC_3D3V_AUX
WIRELESS_BTN# 33
KBRST# 19
KBGA20 19
BT_DET# 32
BT_TH 39,46
RN71
4 KBC_SCL0
3 KBC_SDA0
1
2
KBC_3D3V_AUX
SRN4K7J-8-GP
RN70
1
2
4 KBC_SCL1
3 KBC_SDA1
SRN10KJ-5-GP
3D3V_S5
1
33 KBCBIOS_RD#
33 KBCBIOS_WE#
33 KBCBIOS_CS#
TP103
G74
C
SC15P50V2JN-2-GP
R296
100KR2J-1-GP.Normal
MUTE_LED# 17,32
WLANONLED_KBC
CHG_LED 16
TP29
2
5V_AUX_S5
PCB_VER0
PCB_VER1
PCB_VER2
SB_RSMPWR
1
2
R278
0R2J-2-GP
PCI_SERR# 18,24
KBC_MUTE# 30
PLT_RST1# 7,18,20,26,28,33,34,41
THRM#_R 1 R538
2
0R2J-2-GP
1
9
18
7
19,33,34 LPC_FRAME#
3
PCLK_KBC
20,24,34 INT_SERIRQ
1
C398
1
2
Planar
ID(2,1,0)
SA: 0,0,0
SB: 0,0,1
SC: 0,1,0
SD: 0,1,1
SE: 1,0,0
-1: 1,0,1
R496
DUMMY-R2
R497
10KR2J-3-GP
BLON_IN 42
C407
SC1U10V3ZY-6GP
2
LPC_LAD0
15
LPC_LAD1
14
LPC_LAD2
13
LPC_LAD3
10
R495
DUMMY-R2
0110
1
19,33,34 LPC_LAD[0..3]
VCCBAT
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCA
GAP-CLOSE-PWR
1
SC15P50V2JN-2-GP
2
1
KBC_3D3V_AUX
X4
X-32D768KHZ-40GPU
KBC_XI
161
3D3V_AUX_S5
G75
1
1
C366
C367
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
KBC_3D3V_AUX
D
1
SCD1U16V2ZY-2GP
KBC_XO
23D3V_KBC_AUX_S5
2
16
34
45
123
136
157
166
95
SCD1U16V2ZY-2GP
1
BLM11P600S
SCD01U16V2KX-3GP
2
SC10U10V5ZY-1GP
L29
C390
2
2
C386
2
C673
1
1
1
1
KBC_3D3V_AUX
DY
C687
2
1031 SA
C399
1
2
KBC_SDA1
KBC_SCL1
KBC_SDA0
KBC_SCL0
3
22,32
22,32
46
46
1
3
KCOL[1..16] 32
KROW[1..8] 32
1
4
71
72
73
74
77
78
79
80
5
KBC_3D3V_AUX
R297
100KR2J-1-GP
THRM# 22
B
2
EC_SWI#
20 SB_PWR_BTN#
20 SB_RSMRST#
22 S5_ENABLE
16 BRIGHTNESS
1
R241
TP100
GND
GND
GND
GND
GND
GND
AGND
BATGND
ECRST#
ECSCI#
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
2
4
3
PCB_VER2
PCB_VER1
PCB_VER0
BT_SENSE
AIRLINE_VOLT
1
R646
2
0R2J-2-GP
1
1218
R248
PWR_BTN#
2
10KR2J-3-GP
R253
CHG_ON#
2
10KR2J-3-GP
1 R251
KBRST#
2
10KR2J-3-GP
2 PM_CLKRUN#
10KR2J-3-GP
1 R511
2 SB_RSMRST#
10KR2J-3-GP
DY
3D3V_S5
Intel checklist suggest no
external resistor needed
5V_AUX_S5
1
BT+
R238
CIR_SENSE
2
10KR2J-3-GP
1
AIRLINE_VOLT 39
R276
BT_DET#
2
10KR2J-3-GP
3D3V_S5
1
R246
R501
560KR2F-GP
1218
ECSMI#
1
R506
<Core Design>
2
100KR2J-1-GP
2
100KR2J-1-GP
EC_SWI#
A
Wistron Corporation
BT_SENSE
1
R502
AD_IA
1
C364
2
SCD1U16V2ZY-2GP
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2
100KR2F-L1-GP
A4 for DMRP==>High=Disable,Low=Enable
Title
A5 for EMWB==>High=Enable,Low=Disable
GPIO05 for Clock test mode==>High=test Mode,Low=32KHz clock in normal running(Recommended)
GPIO06 for DPLL test mode==>High=Test Mode,Low=Normal operation(Recommended)
1 R265
3D3V_S5
KBC_3D3V_AUX
1
CHG_I_PRE_SEL 39
CHG_I_SEL 39
CHG_4CELL 39
4CELL# 39
PM_LAN_ENABLE
M_WXMIT_OFF# 26
CHG_I_SEL
VOL_DWN_DK#
VOL_UP_DK#
SRN10KJ-5-GP
K
A
ECSCI# 20
EC_RST#
1N4148W-1-GP
EC_RST# 22
AD_IA
AD_IA 39
1
2
RN49
1
2
D20
2
0R0402-PAD
20,22,28,34,37,38,40 PM_SLP_S3#
17
PWR_BTN#
33 KBC_PWR_BTN#
39
AC_IN#
R261
33
LID_CLOSE#
10KR2J-3-GP R254
17
CIR_SENSE
10KR2J-3-GP
32 INSTANT_ON_BTN#
20,26,27,28 PCIE_WAKE#
KB3910SF-2-GP
1
1
EC_BEEP
2
2
2
DUMMY-R2
DUMMY-R2
R519
R525
A
R256
DUMMY-R2
2
1
1
1
FAN3PWM
FAN3FB
DUMMY-R2
2
A5
A4
19
R516
R258
10KR2J-3-GP
2
R521
10KR2J-3-GP
1
1
1
30
ECSCI#
2
R240 100KR2J-1-GP
KBGA20
1 R522
2
10KR2J-3-GP
1
3D3V_S0
3D3V_S0
2
3D3V_AUX_S5
PM_LAN_ENABLE1
DY
17
35
46
122
137
167
EXT_FWH# 33
96
159
2
1KR2J-1-GP
19
31
1
81
82
83
84
87
88
89
90
A5
BRIGHTNESS_PWM
2
43
40
39
38
37
36
33
32
1
100KR2J-1-GP
99
100
101
102
1
42
47
174
R530
R531
GPWU0
GPWU1
GPWU2
GPWU3
GPWU4
GPWU5
GPWU6
GPWU7
3D3V_AUX_S5
2
26
29
30
44
76
172
176
PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
DY
KBC_ENE K3910SF
Size
A3
Document Number
Rev
SA
Pamirs-Discrete
Date: Tuesday, December 19, 2006
Sheet
31
of
47](https://image.slidesharecdn.com/dv3-131021001825-phpapp02/85/Dv3-31-320.jpg)
![CAMERA
5V_S0
Blue thumb
3D3V_S0
MATRIXID2#
0
0
1
2
C749
BT_PRIORITY
WL_PRIORITY
BT_LED
20.D0197.105
1
20
2
0R0402-PAD
R137
EC92
SCD1U16V2ZY-2GP
DY
USB_4-
USB_PN4
4
ACES-CON24-2-GP
EC91
DY
SCD1U16V2ZY-2GP
5V_S3
1
2
DY
D36
2
20
USB_4+
USB_PP4
1
DY
1
R138
2
0R0402-PAD
3D3V_BT_S0
C740
SC1U10V3ZY-6GP
MAX 150mA
2
1
U74
4
1
C587
SC1U10V3ZY-6GP
G913CF-GP
TR4
20
5
1
2
2
TPAD1
1
2
3
4
6
CAPACITY BUTTON
BAV99W-1-GP
2
0R0402-PAD
R310
3D3V_AUX_S5
3D3V_S0
D19
3D3V_AUX_S5
D6
2
2
FOX-CON4-12-GP
TP_BTN_1#
1
C586
SC33P50V2JN-3GP
DY
1
3D3V_AUX_S5
2
2
C588
SC33P50V2JN-3GP
1
TDATA_5
TCLK_5
1
31
31
CAP_ACK 3
USB_5+
USB_PP5
SA 1011
DY
3
R43
10KR2J-3-GP
1
EC5
SCD1U16V2ZY-2GP
DY
1
KCOL3
KCOL5
KCOL8
KCOL9
2
KROW2
KROW8
KROW7
KCOL10
BAV99W-1-GP
EAPD# 17
5V_S0
3D3V_S0
D
KROW4
KCOL6
KCOL2
KROW1
EAPD#
8
7
6
5
29,30,31
G
EAPD
17,31 MUTE_LED#
3D3V_AUX_S5
D5
2
1
INSTANT_ON_BTN# 3
2
1
3
1
<Core Design>
2
100R2J-2-GP
R487
6
1
2
3
4
62.40009.451
3D3V_AUX_S5
D9
2
TP_BTN# 31
1
8
7
6
5
8
7
6
5
1
2
3
4
ACES-CON12-4-GP
2
SCD1U16V2ZY-2GP
20.K0228.012
2
SC100P50V2JN-3GP
2
SCD1U16V2ZY-2GP
2
SCD1U16V2ZY-2GP
2
SCD1U16V2ZY-2GP
BAV99W-1-GP
SW1
SW-TACT-68-GP-U
2
RC6
SRC100P50V-2-GP
1
TP_BTN_1#
4
RC7
SRC100P50V-2-GP
1
DY EC44
CAP_ACK
1
CAP_DAT
DY EC7
1
INSTANT_ON_BTN# DY EC8
1
EAPD#
DY EC9
1
DY EC12
DY
R488
10KR2J-3-GP
TOUCH-PAD SWITCH
5
KCOL7
KCOL4
KCOL13
KCOL14
2
for EMI
KCOL15
KCOL12
KCOL11
KCOL16
14
5V_S0
3D3V_S0
for EMI
2
2
31 CAP_XPRES
DY 1 0R2J-2-GP
R327
2
3
DY 1 0R2J-2-GP
22,31 KBC_SCL1
R326
2
4
DY 1 0R2J-2-GP
22,31 KBC_SDA1
R325
5
31
CAP_ACK
6
31
CAP_DAT
7
31 INSTANT_ON_BTN#
R345 DY 1
2
8
R342 0R2J-2-GP
MUTE_LED_1#
1
2
9
0R2J-2-GP
10
EAPD#
1
2
11
R81 1
0R2J-2-GP
2
12
R80 DY
0R2J-2-GP
S
RC2
SRC100P50V-2-GP
1
2
3
4
RC5
SRC100P50V-2-GP
1
2
3
4
RC4
SRC100P50V-2-GP
1
2
3
4
1
2
3
4
8
7
6
5
8
7
6
5
8
7
6
5
Q3
2N7002-11-GP
RC3
SRC100P50V-2-GP
CAP1
13
CAP_DAT 3
1
BAV99W-1-GP
KROW3
KROW6
KCOL1
KROW5
C735
SCD1U16V2ZY-2GP
2
2
R424
10KR2J-3-GP
10KR2J-3-GP
1
R428
C739
SC4D7U10V5ZY-3GP
D7
DY
1
1
1
4
3D3V_AUX_S5
L-63UH-GP
BAV99W-1-GP
SET
OUT
SHDN#
GND
IN
1
C585
SCD1U16V2ZY-2GP
DY
3
31 BLUETOOTH_EN
2
2
5V_S3
2
1
2
USB_5-
USB_PN5
5
1
20
1
2
3
2
5V_S3
D35
3D3V_AUX_S5
2
0R0402-PAD
R311
1
1
2
TouchPad Connector
3
BAV99W-1-GP
TCLK_5
EC93
DY
SCD1U16V2ZY-2GP
Close to CN8
L-63UH-GP
20.K0220.024
EC90
DY
SCD1U16V2ZY-2GP
TR2
3D3V_AUX_S5
20.F0772.008
3D3V_BT_S0
1
CAM1
10
ACES-CON8-4-GP
2
2
R600=31K6R2
1
31K6R2F-GP
(3.93V)
33
BT_LED
26 WL_PRIORITY
26 BT_PRIORITY
31
BT_DET#
DY
R600
2
1
4
G913CF-GP
USB_4+
1
6
OUT
2
3
4
5
6
7
8
USB_5+
USB_5-
5
2
C478
SC4D7U10V5ZY-3GP
2
USB_4-
SET
1
1
C493
26
TDATA_5 3
SC1U10V3ZY-6GP
2
1
SCD1U16V2ZY-2GP
1
7
5
4
3
2
SHDN#
GND
IN
1
0
1
2
3
DY
2
1
ACES-CON5-1GP
1
3D3V_BT_S0
U77
C748
DY
1
0
Jap
0R5J-6-GP
DY
2
MATRIXID1#
Eur
9
SC10U10V5ZY-1GP
US
BT1
R599
68KR2F-GP
3D3V_CAM_S0
3
Keyboard matrix ( from vendor )
R386
5V_S0
0R5J-6-GP
1
31 KCOL[1..16]
KROW8
KROW7
KCOL10
KROW5
KROW6
KCOL1
KROW3
KROW4
KCOL6
KCOL2
KROW1
KCOL3
KCOL5
KCOL8
KCOL9
KCOL7
KCOL4
KCOL13
KCOL14
KCOL15
KCOL12
KCOL11
KCOL16
R381
2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
31 KROW[1..8]
KROW2
1
1
2
25
Internal KeyBoard Connector
2
1
KB1
3D3V_CAM_S0
(3.3V)
C670
SC1000P50V3JN-GP
DY
EAPD#
3
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
DY
1
Title
KeyBoard-CONN
BAV99W-1-GP
Size
A3
Document Number
for EMI
Date: Monday, December 18, 2006
Rev
Pamirs-Discrete
Sheet
32
of
SA
47](https://image.slidesharecdn.com/dv3-131021001825-phpapp02/85/Dv3-32-320.jpg)
![A
B
C
D
E
GOLDEN FINGER FOR DEBUG BOARD
TOP VIEW
5V_S0_LPC
5V_S0_LPC
U76
3D3V_AUX_S5
A14
U64
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31
16
17
48
1
2
3
4
5
6
7
8
18
19
20
21
22
23
24
25
31 KBCBIOS_CS#
31 KBCBIOS_RD#
31 KBCBIOS_WE#
R533
10KR2J-3-GP
1
3D3V_AUX_S5
3
R515
1
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
26
28
11
47
12
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
VCC
CE#
OE#
WE#
BYTE#
RESET#
2
2
10KR2J-3-GP
Q15/A-1
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
45
43
41
39
36
34
32
30
44
42
40
38
35
33
31
29
RY/BY#
(B2)
PLT_RST1#_1
LPC_LFRAME#_1
LPC_GND
PCLK_FWH_1
A2
KBC_D[0..7]
KBC_D7
KBC_D6
KBC_D5
KBC_D4
KBC_D3
KBC_D2
KBC_D1
KBC_D0
(B14)
A1
31
(B15)
LPC_LAD3_1
LPC_LAD2_1
LPC_LAD1_1
LPC_LAD0_1
EXT_FWH#_1
3D3V_S0_LPC
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
(BOTTOM VIEW)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
46
27
G81
LPC_LAD[0..3]
19,31,34
7,18,20,26,28,31,34,41
PLT_RST1#
PLT_RST1#
R2
LPC_FRAME#
E
KBC_3D3V_AUX
1
R28
2
200R2J-L1-GP
1
2
100R2J-2-GP
EC1
4
ACES-CON3-1-GP
20.F0735.003
2
3D3V_S0
LPC_LAD3
KBC_PWR_BTN# 31
1
1 R6
1
C441
SCD22U16V3ZY-GP
C8
SC1000P50V3JN-GP
DY
1
LPC_LAD1_1
2
1
R431
100KR2J-1-GP
D
1
LPC_LAD0_1
2
GAP-OPEN-PWR
1
2
G49
LPC_LAD0
G50
31
EXT_FWH#
EXT_FWH#
1
EXT_FWH#_1
2
2
GAP-OPEN-PWR
3D3V_S0
WLANONLED 26
3D3V_S0_LPC
G51
1
2
GAP-OPEN-PWR
1
G80
1
R435
1KR2J-1-GP
LPC_GND
2
GAP-OPEN-PWR
Put near board edge
2
1
2
3
4
2
G48
LPC_LAD1
3D3V_S0
1
LPC_LAD2_1
2
GAP-OPEN-PWR
S
1
G47
1
LPC_LAD2
BT_LED 32
2
5
WLAN1
ACES-CON4-1-GP
LPC_LAD3_1
2
GAP-OPEN-PWR
G
EC31
DY
SCD1U16V2ZY-2GP
1
SCD1U16V2ZY-2GP
3D3V_S0
Q31
2N7002-11-GP
5V_S0
PCLK_FWH_1
2
GAP-OPEN-PWR
R425
100KR2J-1-GP
WIRELESS SWITCH
1
GAP-OPEN-PWR
R5
10KR2J-3-GP
G46
3
2
1
2
20.D0197.102
SCD1U16V2ZY-2GP
2
2
SC1000P50V3JN-GP
DY
2
2
LID_CLOSE# 31
C445
SCD1U16V2ZY-2GP
LPC_LFRAME#_1
2
EC3
5
2
100R2J-2-GP
3
2
POWER SWITCH
2
PDTA124EU-1-GP
1
PCLK_FWH
3 PCLK_FWH
EC6
1
C
1
1
2
ACES-CON2-1-GP-U
1
PLT_RST1#_1
2
GAP-OPEN-PWR
G79
1
B
PWR_LED#
1
16
R1
COVER_SW
1
GAP-OPEN-PWR
G78
PWR1
2
4
5V_S0_LPC
2
GAP-OPEN-PWR
G77
5V_S3
R319
10KR2J-3-GP
R320
3D3V_S0_LPC
1
MX29LV800CBTC-GP
KBC_3D3V_AUX
3
1
4
LPC_LAD3_1
LPC_LAD2_1
LPC_LAD1_1
LPC_LAD0_1
EXT_FWH#_1
5V_S0
19,31,34 LPC_FRAME#
LID1
PLT_RST1#_1
LPC_LFRAME#_1
LPC_GND
PCLK_FWH_1
Boot Device must have ID[3:0] = 0000
Has internal pull-down resistors
All may be left floated
FPET7 Elec. P3-46
Q1
COVER SWITCH
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
FOX-GF30
ZZ.GF030.XXX
14
13
10
9
GND
GND
31
15
NC#14
NC#13
NC#10
NC#9
A0
....
37
4
(B1)
....
A15
R442
10KR2J-3-GP
<Core Design>
1
6
2
1
2
100R2J-2-GP
Wistron Corporation
WIRELESS_BTN# 31
2
1
1
R443
20.D0197.104
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
C593
SC1000P50V3JN-GP
DY
Title
FWH and Debug
Size
A3
Document Number
Date: Thursday, November 02, 2006
A
B
C
D
Rev
Pamirs-Discrete
Sheet
E
33
of
SA
47](https://image.slidesharecdn.com/dv3-131021001825-phpapp02/85/Dv3-33-320.jpg)
![5
4
3
2
1
5V_S0
2
SC4D7U25V5MX-1GP
SC4D7U25V5MX-1GP
2
1
SC4D7U25V5MX-1GP
2
1
4
3
2
1
4
3
2
1
ST330U2D5VDM-9GP
C171
1
2 C161
SC1000P50V2JN-GP
ST330U2D5VDM-9GP
ST330U2D5VDM-9GP
GND
20
VPS
13
MAX8736_VPS
FBS
12
MAX8736_FBS
ST330U2D5VDM-9GP
1
2
ST330U2D5VDM-9GP
1
2
1
2
1
1
ST330U2D5VDM-9GP
2
2
2
1
2
4
3
2
1
4
3
2
1
3K3R3F-GP
2
1
2
1
5
6
7
8
5
6
7
8
11
TC19
NTC-10K-9-GP
C
2
Panasonic , 330uF/2V
ESR = 9m ohm
7.3*4.3*1.9
SCD22U10V3KX-2GP
9
GNDS
TC6
10
CSN3
C289
DY
2
CSP3
5
VCC_SENSE
5
DCBATOUT
C304
D16
1
4
3
2
1
4
3
2
1
1
C164
MAX8552ETB-1-GP
2
NTC-10K-9-GP
SCD01U16V2KX-3GP
1
2
1
R160
2 1
3K3R3F-GP
DY
2
1
2
R161
4
3
2
1
C331
SC1000P50V2JN-GP
G30
GAP-CLOSE-PWR
1
AO4430-1-GP
DY
C294
2
L-D36UH-1-GP
R159
2KR3F-L-GP
5
6
7
8
5
6
7
8
AO4430-1-GP
4
3
2
1
PWM
1
6
2
EN
PWM2
MAX8552_DL
Q28
S
S
S
S
G
7
2
Q9
S
S
S
S
G
DRSKP#
MAX8552_LX
3
L45
1
MAX8552_DH
8
1
1
1
VCC
2
2
MAX8552_AGND
9
AO4422-1-GP
MAX8552_BST
DH
C335
SCD22U16V3KX-2-GP
D
D
D
D
D
DLY
B
SCD1U50V3KX-GP
Q29
AO4422-1-GP
D
D
D
D
D
5
10
PGND
GND
BST
DL
4
2
2
1
U27
LX
A
C755
S
S
S
S
G
R187
0R3-0-U-GP
R_ILIMPK=402K ohm , Iocp=28/phase
1
1KR2F-3-GP
C754
2
SSM5818SLPT-GP
C319
SC2D2U10V3ZY-1GP
R_OSC=143K ohm , Fsw=300K Hz
2
C582
SC4D7U25V5MX-1GP
2
1
Q11
1
D
D
D
D
D
5V_S0
2
EC53
2
C581
SCD1U50V3KX-GP
5
6
7
8
C119
SC1000P50V3JN-GP
5
6
7
8
GND
MAX8736AGTL-GP-U
R204
C584
SC4D7U25V5MX-1GP
2
1
2
SC4D7U25V5MX-1GP
2
1
1
SC4D7U25V5MX-1GP
2
1
2
9K53R3F-2-GP
10R2J-2-GP
GAP-CLOSE-PWR
C305
R69
1
R68
THRM
VSS_SENSE
C153
SC1000P50V3JN-GP
SC4D7U25V5MX-1GP
2
1
VRHOT#
R72
1
2
10R2J-2-GP
1
CLKEN#
MAX8736_GNDS
SC4D7U25V5MX-1GP
2
1
IMVPOK
C160
SC1000P50V2JN-GP
DY
G57
1
SC4D7U25V5MX-1GP
2
1
SC4D7U25V5MX-1GP
2
1
1
1
5
6
7
8
5
6
7
8
2
1
2
1
29
41
1
2 1
S
S
S
S
G
SCD1U10V2MX-3GP
1
2
R140
1
D
D
D
D
D
DY
8
5V_S0
PSI#
G24
GAP-CLOSE-PWR
1
2
R136
AO4430-1-GP
2
2
C279
MAX8736_CSN2
MAX8736_CSP2
CSP2
GAP-CLOSE-PWR
R92
1KR2J-1-GP
1
2MAX8736_IMVPOK
24
1
2
7,20 VGATE_PWRGD
G15
GAP-CLOSE-PWR
R384 2MAX8736_CLKEN#
1
1
3D3V_S0
10KR2J-3-GP
1
2
22
20
CLK_EN#
G58
GAP-CLOSE-PWR
23
1
2 MAX8736_PWR
4 CPU_PROCHOT#
R82
10R2J-2-GP
C159
DY
R79
10KR2J-3-GP
DY
7
DPRSLPVR
GAP-CLOSE-PWR
C273
PWM2
28
PWM3
3
AO4430-1-GP
5
PWM2
SHDN#
R139
2KR3F-L-GP
Q26
DRSKP#
1
3D3V_S0
B
2
CSN1
C258
1
1
PSI#
MAX8736_CSP1
DY
C201
SC1000P50V2JN-GP
2
5
33
6
CSN2
4
2
1
2
30
VDD
DRSKP#
CSP1
D0
D1
D2
D3
D4
D5
D6
2
L-D36UH-1-GP
1
34
35
36
37
38
39
40
TRC
1102 SA
1
Q8
2
G17
31
AO4422-1-GP
L42
MAX8736_DL1
REF
G16
1
32
AO4422-1-GP
MAX8736_LX1
DL1
36A/44A
ILIMPK
GAP-CLOSE-PWR
7,20 DPRSLPVR
2
1
2
1
2
1
21
2
26
C753
D
S
S
S
S
S
G
G14
1
36,37,38,40 CPUCORE_ON
LX1
16
C750
C222
SCD1U50V3KX-GP
D
D
D
D
D
D
CPU_VID[0..6]
C
MAX8736_DH1
C496
VCC_CORE_S0
S
S
S
S
G
5
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
DH1
27
CCV
MAX8736_REF
2
19
SCD22U10V2KX-1GP
1
2MAX8736_TRC 18
R77
1K47R2F-GP
1
C149
25
TIME
17
2
1
1
MAX8736_BST1
BST1
OSC
Q25
D
D
D
D
D
R66
1
15
Q7
R98
0R3-0-U-GP
U16
C504
S
S
S
S
S
G
VCC
C178
PGND
1025 SA
14
C182
SC2D2U10V3ZY-1GP
S
S
S
G
G
MAX8736_OSC
2
140KR3F-GP
MAX8736_TIME
2
100KR2F-L1-GP
1
2 MAX8736_CCV
C150
SC680P50V2KX-2GP
2 360KR3F-GP MAX8736_ILIMPK
EC46
SCD1U50V3KX-GP
SCD22U16V3KX-2-GP
2
C152
SC1U10V3ZY-6GP
1
R48
1
R67
D31
SSM5818SLPT-GP
R70
C211
SC4D7U25V5MX-1GP
2
1
1
1
R101
100KR2J-1-GP
CPU_VID6
2
1
R103
100KR2J-1-GP
CPU_VID5
2
1
1
100KR2J-1-GP
CPU_VID4
2
1
100KR2J-1-GP
2
CPU_VID2
100KR2J-1-GP
CPU_VID3
2
1
R106
C210
D
D
D
D
D
D
100KR2J-1-GP
CPU_VID1
2
D
R111
D
D
D
D
D
CPU_VID0
R126 R122 R119
DCBATOUT
10R3J-3-GP
100KR2J-1-GP
2
5V_S0
MAX8736_CSN2
2
SCD22U10V3KX-2GP
MAX8736_CSP2
<Core Design>
A
G31
1
2
Wistron Corporation
GAP-CLOSE-PWR
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
MAX8552_AGND
Title
DC-DC VCCCPUCORE
Size
A3
Document Number
Rev
5
4
3
2
SA
Pamirs-Discrete
Date: Wednesday, December 13, 2006
Sheet
1
35
of
47](https://image.slidesharecdn.com/dv3-131021001825-phpapp02/85/Dv3-35-320.jpg)
![PEG_RXP12
PEG_RXN12
9
9
PEG_RXP13
PEG_RXN13
9
9
A
9
9
PEG_TXN13
PEG_TXP13
PEG_RXP14
PEG_RXN14
9
9
9
9
PEG_TXP14
PEG_TXN14
PEG_RXP15
PEG_RXN15
9
9
PEG_TXP15
PEG_TXN15
C169
1
1
C168
C175
1
1
C174
C167
1
1
C166
NV_PLLAVDD
PEX_TX12
PEX_TX12#
C59
PEX_PLLGND
C30
NB8M-GS-GP
1
SCD1U10V2KX-5GP
2
1
SCD1U10V2KX-5GP
2
SC1U10V2KX-GP
1
SC1U6D3V2ZY-GP
1
2
C68
3D3V_S0
C15
DY R362
1
2
1
R395
A16
17,29
SPDIF
SPDIF
C209
1
2
2
2KR2-GP
R127 SCD01U16V2KX-3GP
75R2J-1-GP
DY
DY
SC1U10V2KX-GP
1
SC4D7U6D3V3KX-GP
1
1
SCD1U16V2ZY-2GP
2
2
1D2V_S0
NB8M-GS-GP
R93
18KR2J-GP
L15
C472
1
2
BLM15AG221SN-GP
C107
SC4D7U6D3V3KX-GP
reserve for NB86
1D2V_S0
L14
1
2
BLM15AG221SN-GP
C96
FB_VREF
C101
place near GPU
A
<Core Design>
3D3V_S0
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
D39
HDMI_SPDIF
R86
9K09R2F-GP
SCD1U16V2ZY-2GP
2
For NB86
FBA_PLLAVDD
3D3V_S0
For NB86
SCD1U16V2ZY-2GP
1
2
1
TPAD30
place near balls
0R2J-2-GP
DY
HDMI_SPDIF
SCD1U16V2ZY-2GP
1
2
1
2
1
D13
FBA_PLLGND
TPAD30
TP38
1
2
C54
C446 COIL-10NH-GP
SC4D7U6D3V3KX-GP
SCD01U16V2KX-3GP 44,45
VRAM_VREF
SCD1U10V2KX-5GP
AA6
D12
E12
F12
C13
SCD1U16V2ZY-2GP
2
SC1U6D3V2ZY-GP
2
SC1U10V3KX-3GP
2
1
SC1U10V2KX-GP
2
1
SC1U6D3V2ZY-GP
FBA_PLLAVDD
PEX_RX14
PEX_RX14#
NC#D12
NC#E12
NC#F12
NC#C13
TP2
D14
L7
PEX_TX14
PEX_TX14#
PEX_RX15
PEX_RX15#
M23
M24
FBA_PLLVDD
1D2V_S0
PEX_PLLADVDD 1
SC1U10V3ZY-6GP
2
40D2R2F-GP
C74
SCD01U16V2KX-3GP
Y6
AA5
SCD1U16V2ZY-2GP
1
1
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2
1
1
2
1
2
SC1U10V3KX-3GP
2
1
2
2
1
2
FBA_REFCLK
FBA_REFCLK#
SCD1U10V2KX-5GP
PEX_PLLAVDD
PEX_PLLDVDD
R84
1
1
place near GPU
PEX_RX12
PEX_RX12#
PEX_TX15
PEX_TX15#
K22
VGA_CORE_S0
place near balls
PEX_RX11
PEX_RX11#
PEX_RX13
PEX_RX13#
FBA_DEBUG
R50
1
E13
H22
SCD01U16V2KX-3GP
N9
PEX_TX11
PEX_TX11#
PEX_TX13
PEX_TX13#
FBCAL_PU_GND
FBCAL_TERM_GND
B
1D8V_S0
2
40D2R2F-GP
R359
2
30R2J-1-GP
1
PEX_RX10
PEX_RX10#
45
45
45
45
C114
SC10U10V5KX-2GP
9
9
PEG_TXP12
PEG_TXN12
C158
1
1
C157
PEX_TX10
PEX_TX10#
C80
1
1
9
9
PEG_TXN11
PEG_TXP11
D15
C751
44
44
45
45
2
9
9
C156
1
1
C155
FBCAL_PD_VDDQ
FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_RN3
FBADQS_RN4
FBADQS_RN5
FBADQS_RN6
FBADQS_RN7
2
PEG_RXP11
PEG_RXN11
C70
44
44
44
44
1
9
9
PEG_TXP10
PEG_TXN10
FBA_CLKP0
FBA_CLKN0
FBA_CLKP1
FBA_CLKN1
2
9
9
PEX_RX9
PEX_RX9#
A22
E22
F21
B21
V26
W23
V23
W27
L24
K23
M22
N22
SCD01U16V2KX-3GP
PEG_RXP10
PEG_RXN10
C142
1
1
C146
FBADQSN0
FBADQSN1
FBADQSN2
FBADQSN3
FBADQSN4
FBADQSN5
FBADQSN6
FBADQSN7
FBA_CLK0
FBA_CLK0#
FBA_CLK1
FBA_CLK1#
1
9
9
PEG_TXP9
PEG_TXN9
PEX_TX9
PEX_TX9#
J12
F13
J13
F14
J15
J16
C99
D
FBA_RST 44,45
FBA_A7 44,45
FBA_A10 44,45
FBA_CKE 44,45
FBA_A0 44,45
FBA_A9 44,45
FBA_A6 44,45
FBA_A2 45
FBA_A8 44,45
FBA_A3 45
FBA_A1 44,45
place near balls
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
C131
C140
C
2
9
9
C128
1
1
C141
PEX_RX8
PEX_RX8#
VDD_LP
VDD_LP
VDD_LP
VDD_LP
1
PEG_RXP9
PEG_RXN9
PEX_TX8
PEX_TX8#
C752
FBA_A4 45
FBA_RAS# 44,45
FBA_A5 45
FBA_BA1 44,45
FBB_A2 44
FBB_A4 44
FBB_A3 44
FBA_CS1#/BA2 44,45
FBA_CS0# 44,45
FBA_A11 44,45
FBA_CAS# 44,45
FBA_WE# 44,45
FBA_BA0 44,45
FBB_A5 44
FBADQS_WP0
FBADQS_WP1
FBADQS_WP2
FBADQS_WP3
FBADQS_WP4
FBADQS_WP5
FBADQS_WP6
FBADQS_WP7
2
9
9
PEG_TXP8
PEG_TXN8
PEX_RX7
PEX_RX7#
B22
D22
E21
C21
V25
W24
U24
W26
C106
C118
G27
D25
F26
F25
G25
J25
J27
M26
C27
C25
D24
N27
G24
J26
M27
C26
M25
D26
D27
K26
K25
K24
F27
K27
G26
B27
N24
FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7
FBADQSP0
FBADQSP1
FBADQSP2
FBADQSP3
FBADQSP4
FBADQSP5
FBADQSP6
FBADQSP7
44
44
44
44
45
45
45
3D3V_S0 45
C130
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
2
1
9
9
C117
1
1
C122
W9
W10
W11
W12
D21
F22
F20
A21
V27
W22
V22
V24
FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7
2
PEG_RXP8
PEG_RXN8
PEX_TX7
PEX_TX7#
C212
2
B
9
9
PEG_TXP7
PEG_TXN7
PEX_RX6
PEX_RX6#
1
9
9
C102
1
1
C108
PEX_TX6
PEX_TX6#
C95
44
44
44
44
45
45
45
45
SC1U10V2KX-GP
PEG_RXP7
PEG_RXN7
1
1
W13
M14
T14
L15
M15
T15
U15
W15
L16
M16
T16
U16
W16
M17
N17
R17
T17
1
9
9
PEG_TXP6
PEG_TXN6
C97
PEX_RX5
PEX_RX5#
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
C104
2
9
9
C92
PEX_TX5
PEX_TX5#
1214
1
PEG_RXP6
PEG_RXN6
C89
PEX_RX4
PEX_RX4#
45 FBAD[48..63]
1214
C148
F17
F19
J19
M19
T19
J22
L22
P22
U22
Y22
2
9
9
PEG_TXP5
PEG_TXN5
1
1
C83
SCD1U10V2KX-5GP
9
9
C85
C88
SC1U10V2KX-GP
2
PEG_RXP5
PEG_RXN5
C81
PEX_TX4
PEX_TX4#
C79
C94
C100
1
9
9
PEG_TXP4
PEG_TXN4
1
1
FBAD[32..47]
1D8V_S0
place below GPU
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
2
9
9
C72
PEX_RX3
PEX_RX3#
R9
T9
J10
J11
M11
N11
R11
T11
L12
M12
T12
U12
L13
M13
T13
U13
C56
1
PEG_RXP4
PEG_RXN4
C67
PEX_TX3
PEX_TX3#
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
C111
SC10U10V5KX-2GP
9
9
PEG_TXP3
PEG_TXN3
1
1
PEX_RX2
PEX_RX2#
J9
M9
2
9
9
C63
PEX_TX2
PEX_TX2#
45
C115
VDD
VDD
SCD1U10V2KX-5GP
PEG_RXP3
PEG_RXN3
C62
PEX_RX1
PEX_RX1#
C84
VGA_CORE_S0
1
9
9
PEG_TXP2
PEG_TXN2
1
1
C91
place near balls
2
9
9
C55
PEX_TX1
PEX_TX1#
SCD1U16V2ZY-2GP
C
PEG_RXP2
PEG_RXN2
C51
PEX_RX0
PEX_RX0#
1
9
9
PEG_TXP1
PEG_TXN1
1
1
SC10U10V5KX-2GP
9
9
C45
C75
2
PEG_RXP1
PEG_RXN1
C41
PEX_TX0
PEX_TX0#
AB13
AB16
AC16
AB17
AC17
AB18
AB19
AC19
AC20
1
9
9
PEG_TXP0
PEG_TXN0
1
1
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
C129
2
9
9
C39
PEX_REFCLK
PEX_REFCLK#
1
PEG_RXP0
PEG_RXN0
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#
2
9
9
AE3
AE4
SCD1U10V2KX-5GP
RXP0
2
AD5
RXN0
2
AD6
SCD1U10V2KX-5GP
AF1
AG2
SCD1U10V2KX-5GP
2 RXP1
AE6
2 RXN1
AE7
SCD1U10V2KX-5GP
AG3
AG4
SCD1U10V2KX-5GP
2 RXP2
AD7
2 RXN2
AC7
SCD1U10V2KX-5GP
AF4
AF5
SCD1U10V2KX-5GP
2 RXP3
AE9
2 RXN3
AE10
SCD1U10V2KX-5GP
AG6
AG7
SCD1U10V2KX-5GP
2 RXP4
AD10
RXN4
2
AC10
SCD1U10V2KX-5GP
AF7
AF8
SCD1U10V2KX-5GP
2 RXP5
AE12
2 RXN5
AE13
SCD1U10V2KX-5GP
AG9
AG10
SCD1U10V2KX-5GP
2 RXP6
AD13
2 RXN6
AC13
SCD1U10V2KX-5GP
AF10
AF11
SCD1U10V2KX-5GP
2 RXP7
AC15
2 RXN7
AD15
SCD1U10V2KX-5GP
AG12
AG13
SCD1U10V2KX-5GP
2 RXP8
AE15
2 RXN8
AE16
SCD1U10V2KX-5GP
AG15
AG16
SCD1U10V2KX-5GP
2 RXP9
AC18
2 RXN9
AD18
SCD1U10V2KX-5GP
AF16
AF17
SCD1U10V2KX-5GP
2 RXP10
AE18
2 RXN10
AE19
SCD1U10V2KX-5GP
AG18
AG19
SCD1U10V2KX-5GP
2 RXP11
AC21
2 RXN11
AD21
SCD1U10V2KX-5GP
AF19
AF20
SCD1U10V2KX-5GP
2 RXP12
AE21
2 RXN12
AE22
SCD1U10V2KX-5GP
AG21
AG22
SCD1U10V2KX-5GP
2 RXP13
AD22
2 RXN13
AD23
SCD1U10V2KX-5GP
AF22
AF23
SCD1U10V2KX-5GP
2 RXP14
AF25
2 RXN14
AE25
SCD1U10V2KX-5GP
AG24
AG25
SCD1U10V2KX-5GP
AE24
2 RXP15
2 RXN15
AD24
SCD1U10V2KX-5GP
AG26
AF27
PEX_RST#
1
3 PEG_REFCLKP
3 PEG_REFCLKN
AC6
AF13
AF14
2
K
1N4148W-1-GP
1
A
PLT_RST1#
2
8,31,33,34
1
D25
2
2
10KR2J-3-GP
C23
SC10U10V5KX-2GP
SC10U10V5KX-2GP
1
R348
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
1
E15
F15
F16
J17
J18
L19
N19
R19
U19
W19
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
FBVTT
SCD1U16V2ZY-2GP
FBAD[16..31]
place near balls
AA4
AB5
AB6
AB7
AB8
AB9
AC9
AC11
AB12
AC12
2
FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63
1
1
1
2
44
1D2V_S0
C28
A26
C24
B24
A24
C22
A25
B25
D23
G22
J23
E24
F23
J24
F24
G23
H24
D16
E16
D17
F18
E19
E18
D20
D19
A18
B18
A19
B19
D18
C19
C16
C18
N26
N25
R25
R26
R27
T25
T27
T26
AB23
Y24
AB24
AB22
AC24
AC22
AA23
AA22
T24
T23
R24
R23
R22
T22
N23
P24
AA24
AA27
AA26
AB25
AB26
AB27
AA25
W25
2
FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63
1
D
C135
2
1
C116
SCD1U10V2KX-5GP
1
C126
2
C103
SC1U10V2KX-GP
2
AB10
AB11
AB14
AB15
W17
W18
AB20
AB21
SC10U10V5KX-2GP
SC10U10V5KX-2GP
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
U59B
2/12
FBAD[0..15]
place near GPU
2
3 44
1214
SC1U10V3KX-3GP
1D2V_S0
place near balls
SCD1U10V2KX-5GP
4
1
U59A
1/12
2
5
Title
3
1
BAV99W-1-GP
NB8M-GS (1 of 3)
Size
Custom
Date:
Document Number
Rev
SC
Pamirs-Discrete
Tuesday, December 19, 2006
Sheet
41
of
47](https://image.slidesharecdn.com/dv3-131021001825-phpapp02/85/Dv3-41-320.jpg)
![U59I
9/12
MIOB_D11
C1
J5
2
MIOB_VREF
F1
G4
G1
F2
2
3
1
VGA_27MHZ
2
MIOB_HSYNC
R318
150R2F-1-GP
DY
0R2J-2-GP
MIOB_CTL3
Put near GPU
MIOB_CLKOUT
MIOB_CLKOUT#
MIOB_CLKIN
K2
K3
R2
reserve for NB86
1
Vram : Samsung
M5
1
2
BLM15AG221SN-GP
M4
J3
1
1
C444 C48
R1
T1
T2
T3
DY
HDMI_TXD0#
HDMI_TXD0
HDMI_TXD1#
HDMI_TXD1
IFPCD_PLLVDD
IFPCD_RSET
IFPC_TXD2#
IFPC_TXD2
R31
2
For NB86
IFPC_TXD0#
IFPC_TXD0
IFPC_TXD1#
IFPC_TXD1
IFPCD_VPROBE
SCD1U16V2ZY-2GP
L6
1
2
R33810KR2J-3-GP
U59L
12/12
2
1
2
HDMI_TXD0# 23
HDMI_TXD0 23 R341 DY
10KR2J-3-GP
1
2
HDMI_TXD1# 23 R335 DY
10KR2J-3-GP
HDMI_TXD1 23
1
2
R336
10KR2J-3-GP
HDMI_TXD2# 23
HDMI_TXD2#
HDMI_TXD2
V3
V2
MIOB_D0:
1
R340
2
10KR2J-3-GP
MIOB_D9
1
49D9R2F-GP
R9 1
R10 1 49D9R2F-GP
49D9R2F-GP
R7 1
R11 1 49D9R2F-GP
R8 1 49D9R2F-GP
0101
0110
0111
R25
DY
RAM_CFG_3
MIOB_D4:
PCI_DEVID_1
MIOB_D3:
2
2KR2-GP
PCI_DEVID_0
MIOB_D5:
2
2KR2-GP
PCI_DEVID_2
G72M
G72M-V
G72M-Z
1000
0111
0110
MIOB_D11: PCI_DEVID_3
MIOB_CTL3: PCI_DEVID_4
MIOA_D1:
SUB_VENDOR
MIOA_D0:
PEX_PLL_EN_TERM100
MIOA_D6:
1
R375
Infineon
Hynix
Samsung
1 -->8M*32
0-->16M*32
2
2KR2-GP
3GIO_PADCFG_LUT_ADDR[0]
MIOA_D8:
3GIO_PADCFG_LUT_ADDR[1]
1
2
DY 2KR2-GP
R22
MIOB_CTL3
1
2
R27
DY
2KR2-GP
1
R376
2
10KR2J-3-GP
0 SYSTEM BIOS
1 ADAPTER BIOS
0 ENABLED
1 DISABLED
(DEFAULT)
(DEFAULT)
MIOA_D1 42
2
SLOT_CLOCK_CFG 42
DY 10KR2J-3-GP
MIOA_D9:
42
MIOA_D0
MIOA_D0
1
R372
2
DY 2KR2-GP
MIOA_D6
MIOA_D6
1
R373
42
MIOA_D8
MIOA_D8
1
R374 DY
MIOA_D9
1
DY
2
2KR2-GP
MIOB_HSYNC
1
R37
DY
3GIO_PADCFG_LUT_ADDR[2]
2
2KR2-GP
42
0 DESKTOP
1 MOBILE (DEFAULT)
2
2KR2-GP
2
2KR2-GP
2
2
2
2
2
2
SCD01U16V2KX-3GP
2
1
2
2
DY
RAM_CFG_2
2
10KR2J-3-GP
R26
42
DY
RAM_CFG_1
MIOB_D9:
MIOB_D8
1
MIOB_D11
HDMI_TXC# 23
HDMI_TXC 23
DY DY DY DY DY DY DY DY
C17
2
SC1U10V3ZY-6GP
SC4700P25V2KX-LGP
2
3D3V_S0
R12 1 49D9R2F-GP
NB8M-GS-GP
R14 1 49D9R2F-GP
R13 1 49D9R2F-GP
IFPC_IOVDD
SCD01U16V2KX-3GP
C16
2
1
1
1
C47
L4
HDMI_TXC#
HDMI_TXC
GDDR3 8Mx32 64bit
MIOB_D8:
2
10KR2J-3-GP
1
R321
W1
V1
RAM_CFG_0
MIOB_D1:
MIOB_D1
MIOB_D5
IFPCD_PLLGND
IFPC_TXC#
IFPC_TXC
Values
MIOA_D9
R36
MIOB_HSYNC:
3GIO_PADCFG_LUT_ADDR[3]
<Core Design>
R16
AD16
B17
E17
L17
P17
U17
AD17
AF18
K19
P19
V19
AD19
B20
E20
AD20
AF21
B23
E23
H23
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Bit Signal
2
10KR2J-3-GP
1
R323
C38
A
1
R339
1
R322
1
2
SC4700P25V2KX-LGP
2
SC1U10V3ZY-6GP
B
3D3V_S0
MIOB_D3
L9
1
2
BLM15AG221SN-GP
64.25505.6DL
N13
P13
R13
B14
E14
J14
L14
N14
P14
R14
U14
W14
AC14
AD14
N15
P15
R15
AF15
N16
P16
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C440 DY
SC27P50V2JN-2-GP
B8
E8
AD8
K9
P9
V9
AD9
AF9
B11
E11
F11
L11
P11
U11
AD11
N12
P12
R12
AD12
AF12
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
27MHZ_XOUT
For NB86
HDMI_TXD2 23
1KR2J-1-GP
3D3V_S0
XTAL-27MHZ-29-GP
C447 DY
SC22P50V2JN-4GP
MIOB_D0
MIOB_D4
M6
DY
2
2
NB8M-GS-GP
C66
C2
R21
1
10KR2J-3-GP
C
TPAD30
G72 : R324=255ohm , R318=150ohm
G86 : R324=0ohm , R318=DY
2
MIOB_VSYNC
MIOB_HSYNC
MIOB_DE
MIOB_CTL3
R324
1
J4
R337
2KR2-GP
DY
X6
TP36
1
1
MIOBCAL_PU_GND
NC
1D8V_S0
1
MIOBCAL_PD_VDDQ
M3
C3
XTALOUT
NB8M-GS-GP
27MHZ_XIN
3 VGA_27MHZSS
XTALOUTBUFF
XTALIN
1
1
XTALSSIN
B1
3D3V_S0
TPAD30 TP35
PLLGND
B2
E2
H2
L2
P2
U2
Y2
AC2
AF2
AF3
B5
E5
L5
P5
U5
Y5
AC5
H6
AF6
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PLLVDD
H5
1
1
H4
C58
SCD1U16V2ZY-2GP
MIOB_D8
MIOB_D9
C46
2
MIOB_D3
MIOB_D4
MIOB_D5
C50
SC4700P25V2KX-LGP
2
1
PLL_VDD
C49
SC1U10V3ZY-6GP
2
D
SCD1U16V2ZY-2GP
C98
MIOB_VDDQ
MIOB_VDDQ
MIOB_VDDQ
L11
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
U59J
10/12
For NB86
reserve for NB86
MIOB_D0
MIOB_D1
G2
G3
J2
J1
K4
K1
M2
M1
N1
N2
N3
R3
2
1
K5
K6
L6
MIOBD0
MIOBD1
MIOBD2
MIOBD3
MIOBD4
MIOBD5
MIOBD6
MIOBD7
MIOBD8
MIOBD9
MIOBD10
MIOBD11
SC4D7U6D3V3KX-GP
2
1
3D3V_S0
1
2
BLM15AG221SN-GP
1
1D2V_S0
11/12
1
2
L23
P23
U23
Y23
AC23
AF24
B26
E26
H26
L26
P26
U26
Y26
AC26
AF26
D
3D3V_S0
2
3
R561
2KR2-GP
1
4
2
5
C
B
A
NB8M-GS-GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
NB8M-GS (3 of 3)
Document Number
Rev
SC
Pamirs-Discrete
Date: Monday, December 18, 2006
Sheet
43
of
47](https://image.slidesharecdn.com/dv3-131021001825-phpapp02/85/Dv3-43-320.jpg)
![5
4
3
2
1
1D8V_S0
41,45
FBA_CAS#
F9
CS#
41,45
FBA_CKE
H9
WE#
41,45 FBA_CS1#/BA2
R16
60D4R2F-GP
41,45
FBA_CS0#
H3
RAS#
F4
CAS#
41,45
H4
CKE
J10
J11
CK#
CK
2
FBA_A7
FBA_A8
FBA_A3
FBA_A10
FBA_A11
FBA_A2
FBA_A1
FBA_A0
FBA_A9
FBA_A6
FBA_A5
FBA_A4
1
1
1
2
C19
1
SCD01U16V2KX-3GP
B
41
41
2
2
R18
60D4R2F-GP
FBA_WE#
FBA_CLKN0
FBA_CLKP0
41
41
41
41
P2
P11
D11
D2
WDQS3
WDQS2
WDQS1
WDQS0
FBADQM3
FBADQM2
FBADQM1
FBADQM0
N3
N10
E10
E3
DM3
DM2
DM1
DM0
1
FBA_RST
1
R29
10KR2J-3-GP
V9
FBA_RST
1
R4
2
A4
240R2F-1-GP
VRAM_VREF
1
VRAM_VREF
SC1U6D3V2ZY-GP
1
1
2
2
1
2
2
SC4D7U10V5ZY-3GP
1
2
1
2
SC1U6D3V2ZY-GP
C53
SC1U6D3V2ZY-GP
1
C147
2
2
1
C24
SC1U6D3V2ZY-GP
SC1U6D3V2ZY-GP
1
2
1
2
SC1U6D3V2ZY-GP
C14
C
1D8V_S0
B
C65
SCD1U16V2ZY-2GP
R24
1
2
0R2J-2-GP
1D8V_S0
ZQ
H1
VREF
H12
41,45
C137
RES
2
41,45
V4
D
1D8V_S0
J2
RFU
C25
J3
RFU
C132
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C474
C4
C110
PAR
C61
2
VSSA
VSSA
SCD1U16V2ZY-2GP
J12
J1
1
K1
K12
1
VDDA
VDDA
1
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3
A10
G1
G12
L1
L12
V3
V10
C93
1D8V_S0
2
FBADQSP3
FBADQSP2
FBADQSP1
FBADQSP0
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RDQS3
RDQS2
RDQS1
RDQS0
41
41
41
41
R42
10KR2J-3-GP
2
P3
P10
D10
D3
41
41
41
41
FBA_CKE
FBADQSN3
FBADQSN2
FBADQSN1
FBADQSN0
A2
A11
F1
F12
M1
M12
V2
V11
2
A11
A10
A9
A8/AP
A7
A6
A5
A4
A3
A2
A1
A0
41,45
41,45
41
41,45
41,45
41
41,45
41,45
41,45
41,45
41
41
R17
0R2J-2-GP
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
C138
SCD1U16V2ZY-2GP
1
BA2
BA1
BA0
L4
K2
M9
K11
L9
K10
H11
K9
M4
K3
H2
K4
41,45 FBA_RAS#
41,45
FBA_BA0
41,45
FBA_BA1
1D8V_S0
A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12
1
C
FBAD[0..15]
C136
1D8V_S0
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
SC1U6D3V2ZY-GP
41
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
H10
G9
G4
D
T3
T2
R3
R2
M3
N2
L3
M2
T10
T11
R10
R11
M10
N11
L10
M11
G10
F11
F10
E11
C10
C11
B10
B11
G3
F2
F3
E2
C3
C2
B3
B2
2
FBAD31
FBAD30
FBAD29
FBAD28
FBAD27
FBAD26
FBAD25
FBAD24
FBAD23
FBAD22
FBAD21
FBAD20
FBAD19
FBAD18
FBAD17
FBAD16
FBAD15
FBAD14
FBAD13
FBAD12
FBAD11
FBAD10
FBAD9
FBAD8
FBAD7
FBAD6
FBAD5
FBAD4
FBAD3
FBAD2
FBAD1
FBAD0
1
FBAD[16..31]
2
41
SC1U6D3V2ZY-GP
U2
VREF
MF
A9
HY5RS573225AFP-GP
2
C121
A
SCD1U16V2ZY-2GP
<Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
VRAM1
Document Number
Rev
SC
Pamirs-Discrete
Date: Monday, December 18, 2006
Sheet
44
of
47](https://image.slidesharecdn.com/dv3-131021001825-phpapp02/85/Dv3-44-320.jpg)
![4
3
U7
1
1
WE#
41,44
FBA_RAS#
H3
RAS#
41,44
FBA_CAS#
F4
CAS#
FBA_CKE
H4
CKE
CK#
CK
2
R46
60D4R2F-GP
B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12
A3
A10
G1
G12
L1
L12
V3
V10
VDDA
VDDA
K1
K12
VSSA
VSSA
SCD1U16V2ZY-2GP
J12
J1
RDQS3
RDQS2
RDQS1
RDQS0
1103 SA
1
2
1
CS#
H9
J10
J11
2
41
41
F9
FBA_WE#
41,44
R47
60D4R2F-GP
B
FBA_CS0#
41,44
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FBA_CLKN1
FBA_CLKP1
FBADQSN7
FBADQSN6
FBADQSN5
FBADQSN4
41
41
41
41
FBADQSP7
FBADQSP6
FBADQSP5
FBADQSP4
P2
P11
D11
D2
WDQS3
WDQS2
WDQS1
WDQS0
41
41
41
41
FBADQM7
FBADQM6
FBADQM5
FBADQM4
N3
N10
E10
E3
DM3
DM2
DM1
DM0
1D8V_S0
V9
FBA_RST
1
1
2
A4
240R2F-1-GP
SC1U6D3V2ZY-GP
1
2
2
2
2
1
1
1
1
2
SC4D7U10V5ZY-3GP
1
2
SC1U6D3V2ZY-GP
1
2
SC1U6D3V2ZY-GP
1
2
1
2
SC1U6D3V2ZY-GP
SC1U6D3V2ZY-GP
1
2
1
2
SC1U6D3V2ZY-GP
C44
C
B
C7
SCD1U16V2ZY-2GP
V4
R30
0R2J-2-GP
ZQ
H1
VREF
VREF
A9
2
MF
1
R73
0R2J-2-GP
HY5RS573225AFP-GP
VRAM_VREF
SCD1U16V2ZY-2GP
<Core Design>
A
2
41,44
Wistron Corporation
2
C18
2
1
C73
SCD1U16V2ZY-2GP
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2
G
C31
2
VRAM_VREF
2
910R2F-1-GP
1
D
MEM_VREF
S
42
C43
1D8V_S0
RES
H12
R40
Q20
1K33R2F-GP
2N7002-11-GP
C134
1
R15
510R2F-L-GP
A
SC1U6D3V2ZY-GP
C276
C10
R62
R363
1
C143
1
41,44
1D8V_S0
C5
J2
RFU
C133
J3
RFU
C27
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1D8V_S0
C12
PAR
C139
C36
2
41
41
41
41
P3
P10
D10
D3
C6
1
41,44
SCD01U16V2KX-3GP
C112
FBA_A11
FBA_A10
FBA_A9
FBA_A8
FBA_A7
FBA_A6
FBB_A5
FBB_A4
FBB_A3
FBB_A2
FBA_A1
FBA_A0
A2
A11
F1
F12
M1
M12
V2
V11
1D8V_S0
SC1U6D3V2ZY-GP
A11
A10
A9
A8/AP
A7
A6
A5
A4
A3
A2
A1
A0
41,44
41,44
41,44
41,44
41,44
41,44
41
41
41
41
41,44
41,44
R52
0R2J-2-GP
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
D
1
L4
K2
M9
K11
L9
K10
H11
K9
M4
K3
H2
K4
2
41,44 FBA_CS1#/BA2
41,44
FBA_BA1
41,44
FBA_BA0
A1
A12
C1
C4
C9
C12
E1
E4
E9
E12
J4
J9
N1
N4
N9
N12
R1
R4
R9
R12
V1
V12
2
BA2
BA1
BA0
1D8V_S0
C
1D8V_S0
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
1
41 FBAD[32..47]
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
H10
G9
G4
D
T3
T2
R3
R2
M3
N2
L3
M2
T10
T11
R10
R11
M10
N11
L10
M11
G10
F11
F10
E11
C10
C11
B10
B11
G3
F2
F3
E2
C3
C2
B3
B2
2
FBAD63
FBAD62
FBAD61
FBAD60
FBAD59
FBAD58
FBAD57
FBAD56
FBAD55
FBAD54
FBAD53
FBAD52
FBAD51
FBAD50
FBAD49
FBAD48
FBAD47
FBAD46
FBAD45
FBAD44
FBAD43
FBAD42
FBAD41
FBAD40
FBAD39
FBAD38
FBAD37
FBAD36
FBAD35
FBAD34
FBAD33
FBAD32
1
1
41 FBAD[48..63]
2
2
5
Title
Size
A3
VRAM2
Document Number
Rev
SC
Pamirs-Discrete
Date: Monday, December 18, 2006
Sheet
45
of
47](https://image.slidesharecdn.com/dv3-131021001825-phpapp02/85/Dv3-45-320.jpg)
Dv3
- 1. 5 4 3 2 1 Pamirs-Discrete Block Diagram SYSTEM DC/DC TPS51120 OUTPUTS INPUTS Project code : 91.4S401.001 PCB P/N :06230 Revision : SC Intel CPU Meron 2M/4M SV FSB:667 or 800 MHz CLK GEN D ICS9LPRS355A 5V_S3 DCBATOUT 3V_S5 SYSTEM DC/DC 4,5,6 INPUTS 3 RGB CRT CRT 1D05V_S0 DCBATOUT 1D8V_S3 LVDS DDRII Slot 0 533/667 13 DDRII 667 Channel A Crestline-GM/GML AGTL+ CPU I/F LVDS, CRT I/F 14 LCD SYSTEM DC/DC 14 FAN5234 nVIDIA INPUTS DDR I/F INTEGRATED GRAHPICS DDR II 667 Channel B Slot 1 OUTPUTS 13 Host BUS 533/667MHz DDRII 533/667 D MAX8743 SVIDEO PCIE x 16 NB8M-GS OUTPUTS VGA_CORE_S0 TVOUT 13 DCBATOUT 11A 38,39,40 7,8,9,10,11,12 MAXIM CHARGER MAX8725 C 1394 Ricoh R5C833 SD/SDIO/MMC MS/MS Pro/xD 25 18V 3.0A 100mA PCI CardReader BLUE TOOTH 32 INTEL 24,25 10/100 NIC Marvell 88E8039 LCI CPU DC/DC USB 2.0 USB x 3 23 INPUTS OUTPUTS 10 USB 2.0/1.1 ports 27 VCC_CORE ETHERNET (10/100/1000Mb) SATA HDD ODD DCBATOUT 23 PATA High Definition Audio 23 0.844~1.3V 44A ATA 66/100 ACPI 1.1 AMOM B RJ11 CONN 29 HD Audio MODEM CX20548 PCB LAYER LPC I/F PCI/PCI BRIDGE TPM SLB9635TT LPC Bus 18,19,20,21 L1: L2: L3: L4: L5: L6: L7: L8: L9: L10: 34 INTERNAL ARRAY MIC PCIE+USB 2.0 29 LINE OUT Ricoh R5538 SPDIF PCIE x 1 USB 2.0 x 1 MIC IN PCIE x 1 HD AUDIO CODEC CX20549-12Z KBC ENE KB3910SF 31 28 OP AMP APA2031 A New Card 30 28 Mini-Card 802.11a/b/g26 C MAX8736ETL ICH8-M RJ45 CONN 28 DCBATOUT CAMERA32 OUTPUTS BT+ 5V DMI I/F 100MHz 1394 25 INPUTS Mini-Card WWAN26 Capacity Button32 Touch Pad 32 Int. KB32 Thermal & Fan G792 22 CIR Flash ROM 1MB 33 Signal GND Signal Signal GND VCC Signal Signal GND Signal B 1 2 3 4 5 5 <Core Design> A Wistron Corporation 2CH SPEAKER 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. DOCK CRT MIC IN LINE OUT S/PDIF TVOUT Title 10/100 Ethernet Block Diagram CIR Size A3 Document Number Rev Pamirs-Discrete Date: Monday, December 18, 2006 5 4 3 2 Sheet 1 1 SC of 47
- 2. A B C D E INTEL ICH8-M STRAP PIN 19,21 +RTCVCC 4,5,6,7,9,10,11,19,21,37,47 +RTCVCC Usage/When Sampled HDA_SDOUT XOR Chain Entrance/ PCIE Port Config 1 bit1, Rising Edge of PWROK 4 HDA_SYNC PCIE Port Config 1 bit0, Rising Edge of PWROK. GNT2# PCIE Port Config 2 bit0, Rising Edge of PWROK. Comment Allows entrance to XOR Chain testing when TP3 pulled low at rising edge of PWROK.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers:offset 224h) Sets bit0 of RPC.PC(Config Registers:Offset 224h) XOR Chain Entrance Strap ICH_RSVD tp3 AZ_DOUT_ICH 0 0 1 1 0 1 0 1 1D05V_S0 3,7,10,21,38 1D25V_S0 Signal 1D05V_S0 1D25V_S0 27 1D2V_LAN_S5 1D2V_LAN_S5 28 1D5V_NEW_S0 Description RSVD Enter XOR Chain Normal Operation(default) Set PCIE port cofig bit1 1D5V_NEW_S0 5,10,17,19,20,21,26,28,38,47 7,10,11,13,14,34,37,38 GNT3# GNT0# SPI_CS1# INTVRMEN 3 Reserved Top-Block Swap Override. Rising Edge of PWROK. Boot BIOS Destination Selection. Rising Edge of PWROK. Integrated VccSus1_05 VccSus1_5 and VccCL1_5 VRM Enable/Disable.Always sampled. 2D5V_LAN_S5 3D3V_AUD_S0 Sampled low:Top-Block Swap mode(inverts A16 for all A16 swap override strap cycles targeting FWH BIOS space). PCI_GNT#3 low = A16 swap override enable Note: Software will not be able to clear the high = default Top-Swap bit until the system is rebooted without GNT3# being pulled down. BOOT BIOS Strap PCI_GNT#0 SPI_CS#1 BOOT BIOS Location Controllable via Boot BIOS Destination bit 0 1 SPI (Config Registers:Offset 3410h:bit 11:10). PCI 1 0 GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. 1 Enables integrated VccSus1_05,VccSus1_5 and VccCL1_5 VRM when sampled high 1 Enables integrated when sampled high PCIE LAN REVERSAL.Rising Edge of PWROK. This signal has weak internal pull-up. set bit27 of MPC.LR(Device28:Function0:Offset D8) SPKR No Reboot. Rising Edge of PWROK. If sampled high, the system is strapped to the "No Reboot" mode(ICH8M will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit.(Offset:3410h:bit5) TP3 XOR Chain Entrance. Rising Edge of PWROK. This signal should not be pull low unless using XOR Chain testing. GPIO33/ HDA_DOCK_EN# 3D3V_LAN_S5 3D3V_S0 17,18,20,21,22,26,27,28,29,31,34,36,39,47 22,26,29,31,34,36 3D3V_S0 3D3V_S5 3D3V_S5 5V_AUX_S5 16,23,32,33,34,36,37,38 5V_AUX_S5 5V_S3 5V_S3 5V_S0 5V_S0 16,21,34,37,40 5V_S5 5V_S5 15,16,17,20,21,22,23,29,30,31,32,33,34,35,47 LPC(Default) 17,39,46,47 AD+ 16,17,34,35,36,37,39,40,47 Low=Disable AD+ DCBATOUT DCBATOUT 13,14,38 DDR_VREF_S0 VccLAN1_05,VccCL1_05 VRM LAN100_SLP High=Enable Low=Disable DDR_VREF_S0 7,13,14,38 DDR_VREF_S3 DDR_VREF_S3 22,31,33,39 KBC_3D3V_AUX Integrated VccLAN1_05 VccCL1_05 VRM enable /Disable. Always sampled. SATALED# 3D3V_AUX_S5 3,4,7,10,11,13,14,15,16,18,19,20,21,22,23,24,25,26,27,28,29,31,32,33,34,35,36,40,41,42,43,47 integrated VccSus1_05,VccSus1_5,VccCL1_5 SM_INTVRMEN High=Enable 3D3V_AUX_S5 27,28 3D3V_LAN_S5 integrated VccLan1_05VccCL1_05 LAN100_SLP 1D8V_S3 29,30 3D3V_AUD_S0 Weak Internal PULL-DOWN.NOTE:This signal should not be pull HIGH. 4 1D5V_S0 1D8V_S3 27,28 2D5V_LAN_S5 Sets bit2 of RPC.PC(Config Registers:Offset 224h) 19,31,32,33,36,39,46 GPIO20 1D5V_S0 KBC_3D3V_AUX 16 DEFAULE HIGH LCDVDD_S0 3 LCDVDD_S0 5,6,35 VCC_CORE_S0 VCC_CORE_S0 No Reboot Strap SPKR LOW = Defaule High=No Reboot Internal Pull-Up.If sampled low,the Flash Descriptor Flash Descriptor Security Security will be overidden.if high,the Security Override Strap measures defined in the Flash Descriptor will be in 8.2K PULL HIGH Rising Edge of PWROK. effect. This should only be used in manufacturing environments INTEL ICH8-M INTEGRATED PULL-UPS and PULL-DOWNS SIGNAL Resistor Type/Value HDA_BIT_CLK PULL-DOWN 20K HDA_RST# NONE HDA_SDIN[3:0] PULL-DOWN 20K HDA_SDOUT PULL-DOWN 20K HDA_SYNC PULL-DOWN 20K GNT[3:0] PULL-UP 20K GPIO[20] PULL-DOWN 20K LDA[3:0]#/FHW[3:0]# PULL-UP 20K LAN_RXD[2:0] PULL-UP 20K LDRQ[0] PULL-UP 20K LDRQ[1]/GPIO23 PULL-UP 20K PME# PULL-UP 20K CFG 20 Normal Operation ★ Reserved Lane Only PCIE or SDVO PCIE and SDVO are is operation ★ operation simultaneous PWRBTN# PULL-UP 20K SATALED# PULL-UP 20K SDVO_CTRL_DATA NO SDVO Card Present ★ SPI_CS1# PULL-UP 20K SPI_CLK PULL-UP 20K XOR/ALL-Z SPI_MOSI PULL-UP 20K Reserved XOR Mode Enabled All Z Mode Enabled Normal Operation SPI_MISO PULL-UP 20K Wistron Corporation TACH_[3:0] PULL-UP 20K 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. SPKR PULL-DOWN 20K TP[3] PULL-UP 20K USB[9:0][P,N] PULL-DOWN 15K CL_RST# TBD 2 INTEL CRESTLINE STRAP PIN CFG Strap CFG 5 CFG 8 Low Power PCI Express CFG 9 PCI Express Graphics Lane Reversal CFG 16 FSB Dynamic ODT CFG 19 DMI Lane Reserved Concurrent SDVO/PCIE LOW 0 DMI X 2 DMI X 4 ★ Normal ★ Low Power mode Lane Reversal Disabled SDVO Present 1 CFG 12 CFG 13 LL(00) LH(01) HL(10) HH(11) HIGH 1 Normal Mode(Lanes★ number in order) Enabled ★ SDVO Card Present 2 <Core Design> 1 Title Table of Content Size A3 Document Number Rev Pamirs-Discrete Date: Wednesday, November 01, 2006 Sheet 2 SA of 47
- 3. 5 3D3V_S0 4 3D3V_S0_CK505 3 2 1 L21 1 SCD1U16V2ZY-2GP X1 CLK_XTAL_OUT C332 SC4D7P50V2CN-1GP 1 1 C348 20 SC10U10V5ZY-1GP 2 1 C342 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP 2 1 C620 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SC10U10V5ZY-1GP SC1U10V3KX-3GP 2 1 C621 DY C614 2 1 C596 2 1 C354 2 1 2 MLB-160808-18-GP C601 2 1 1 CLK_XTAL_IN CLK_XTAL_OUT 3 2 1 FSA 2 R200 17 45 44 13,14,20 ICH_SMBCLK 13,14,20 ICH_SMBDATA 7 6 20 63 CK_PWRGD 19 27 43 52 33 56 CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8 54 53 USB_48MHZ/FSLA SRCT6 SRCC6 48 47 SRCT10 SRCC10 41 42 SRCT11/CR#_H SRCC11/CR#_G 40 39 SRCT9 SRCC9 37 38 SRCT4 SRCC4 34 35 2 1 RN41 MCH_3GPLL 2 MCH_3GPLL# 1 SRCT3/CR#_C SRCC3/CR#_D 31 32 SRCT2/SATAT SRCC2/SATAC 28 29 PCIE_SATA PCIE_SATA# 2 1 27MHZ_NONSS/SRCT1/SE1 27MHZ_SS/SRCC1/SE2 24 25 27MHZ 27MHZSS 2 1 SRCT0/DOTT_96 SRCC0/DOTC_96 20 21 REFCLKP REFCLKN 2 1 CK_PWRGD/PD# 33R2J-2-GP 33R2J-2-GP 33R2J-2-GP 33R2J-2-GP 33R2J-2-GP PCI2_TME 27_SEL ITP_EN 2 15R2J-GP NC#55 18 15 1 C612 1 FS_B 0 0 1 1 FS_A 2 1 DY SRC8 CPU_ITP 1 1 0 1 100M 133M 200M 166M DY 5 CPU_BSEL2 R449 5 CPU_BSEL1 R203 5 CPU_BSEL0 R201 1 2 1 2 1 2 FSC 10KR2J-3-GP 2 SA 1011 3 4 3 4 3 4 CLK_PCIE_SATA 19 CLK_PCIE_SATA# 19 SRN0J-6-GP SRN33J-5-GP-U VGA_27MHZ 43 VGA_27MHZSS 43 PEG_REFCLKP 41 PEG_REFCLKN 41 SRN0J-6-GP B 27_SEL FSB R184 10KR2J-3-GP 27_SEL 0 1 PIN 20 PIN 21 DOT96T SRCT0 DOT96C SRCC0 PIN 24 PIN 25 SRCT1/LCDT_100 27M_NSS SRCT1/LCDT_100 27M_SS 0R2J-2-GP FSA 2K2R2J-2-GP R191 1 2 1KR2J-1-GP MCH_CLKSEL0 7 R174 1 A CLK_PCIE_ICH 20 CLK_PCIE_ICH# 20 R183 10KR2J-3-GP 2 0 1 ITP_EN SRN0J-6-GP RN32 CPU R448 10KR2J-3-GP R447 10KR2J-3-GP CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7 1 C313 1 2 1 0 0 0 3D3V_S0_CK505 Output SRN0J-6-GP 3D3V_S0_CK505 FS_C ITP_EN 3 4 C CLK_PCIE_MINI2 26 CLK_PCIE_MINI2# 26 ICS9LPRS355AKLFT-GP SC4D7P50V2CN-1GP C315 1 2 SC4D7P50V2CN-1GP R454 10KR2J-3-GP 2 DY SC4D7P50V2CN-1GP C316 1 2 SC4D7P50V2CN-1GP 2 1 B PCI2_TME SC4D7P50V2CN-1GP 1 C314 1 2 1 2 3D3V_S0_CK505 R453 10KR2J-3-GP 3 4 RN34 GND 1 RN42 R227 1 DY 2 10KR2J-3-GP 3 4 SRN0J-6-GP CLK_PCIE_NEW 28 CLK_PCIE_NEW# 28 3D3V_S0 NEWCARD_CLKREQ# 28 65 R450 GND48 GNDPCI GNDREF CLK_14M_ICH FSLB/TEST_MODE REF0/FSLC/TEST_SEL 55 20 64 5 CLK_PCIE_MINI1 26 CLK_PCIE_MINI1# 26 3 4 SRN0J-6-GP 1 2 R228 10KR2J-3-GP RN37 FSB FSC 2 2 2 2 2 2 CLK_PCIE_LAN 27 CLK_PCIE_LAN# 27 4 SRN0J-6-GP 3 1 DY GND GNDSRC GNDSRC GNDSRC GNDCPU GND 1 1 1 1 1 PCI0/CR#_A PCI1/CR#_B PCI2/TME PCI3 PCI4/27_SELECT PCI_F5/ITP_EN PCIE_MINI2 PCIE_MINI2# CLK_CPU_XDP 4 CLK_CPU_XDP# 4 SA 1011 4 SRN0J-6-GP 3 PCIE_ICH RN40 2 PCIE_ICH# 1 SCLK SDATA CLK_MCH_BCLK 7 CLK_MCH_BCLK# 7 4 SRN0J-6-GP 3 DY 1 2 RN39 PCIE_MINI1 1 PCIE_MINI1# 2 RN45 PCIE_NEW 2 PCIE_NEW# 1 RN43 51 50 CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4 4 SRN0J-6-GP 3 PCIE_LAN PCIE_LAN# SRCT7/CR#_F SRCC7/CR#_E PCI_STOP# CPU_STOP# 22 30 36 49 59 26 R185 R192 R193 R195 R194 8 10 11 12 13 14 4 SRN0J-6-GP 3 1 2 RN30 MCH_BCLK 1 MCH_BCLK# 2 RN33 CPU_XDP 1 CPU_XDP# 2 RN36 58 57 SA 1011 20 CLKSATAREQ# 7 CLKREQ#_B 33 PCLK_FWH 34 CLK_PCI_TCG 31 PCLK_KBC 18 CLK_PCI_ICH 24 PCLK_PCM CPU_BCLK CPU_BCLK# 61 60 CPUT1_F CPUC1_F 33R2J-2-GP H_STP_PCI# H_STP_CPU# C CPUT0 CPUC0 X1 X2 2 CLK_48M_ICH 20 20 VDD96_IO VDDPLL3_IO VDDSRC_IO VDDSRC_IO VDDSRC_IO VDDCPU_IO 1D25V_S0_CK505 L49 2 D C327 SC18P50V2JN-1-GP U28 VDDREF VDD48 VDDPCI VDDSRC VDDCPU VDDPLL3 1D25V_S0 C328 SC18P50V2JN-1-GP 4 16 9 46 62 23 2 X-14D31818M-40GP 2 1 1 CLK_XTAL_IN 2 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP D 1D25V_S0_CK505 C600 1 C595 2 1 C630 2 1 3D3V_S0_CK505 2 1 DY C597 2 1 C594 SCD1U16V2ZY-2GP 2 DY C603 SCD1U16V2ZY-2GP SC10U10V5ZY-1GP 2 1 C337 2 1 2 SC1U10V3KX-3GP 2 1 1 MLB-160808-18-GP C639 2 1KR2J-1-GP MCH_CLKSEL1 7 R445 1 2 1KR2J-1-GP MCH_CLKSEL2 7 <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Design Note: 1. All of Input pin didn't have internal pull up resistor. 2. Clock Request (CR) function are enable by registers. 3. CY28548 integrated serial resistor of differential clock, so put 0 ohm serial resistor in the schematic. Title Size A3 Clock generator CY28548 Document Number Rev Pamirs-Discrete Date: Tuesday, December 19, 2006 Sheet 3 SC of 47
- 4. 5 4 3 2 1 XDP Connector CN2 7 H_A#[3..35] U62A 1 OF 4 19 H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI# TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TPAD28 TP13 TP16 TP7 TP9 TP5 TP10 TP6 TP18 TP8 TP17 A6 A5 C4 D5 C6 B4 A3 TPAD28 TP4 CPU_RSVD11 M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 B1 RSVD#M4 RSVD#N5 RSVD#T2 RSVD#V3 RSVD#B2 RSVD#C3 RSVD#D2 RSVD#D22 RSVD#D3 RSVD#F6 C1 F3 F4 G3 G2 H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY# G6 E4 H_HIT# H_HITM# BPM0# BPM1# BPM2# BPM3# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# XDP_BPM#0 AD4 XDP_BPM#1 AD3 XDP_BPM#2 AD1 XDP_BPM#3 AC4 XDP_BPM#4 AC2 XDP_BPM#5 AC1 XDP_TCK AC5 XDP_TDI AA6 XDP_TDO AB3 XDP_TMS AB5 XDP_TRST# AB6 C20 XDP_DBRESET# CONTROL 1 H_LOCK# H_DEFER# 7 H_DRDY# 7 H_DBSY# 7 H_BR0# H_INIT# 7 THERMTRIP# HCLK BCLK0 BCLK1 XDP_BPM#3 XDP_BPM#2 R156 56R2J-4-GP XDP_BPM#1 XDP_BPM#0 2 H4 PROCHOT# THRMDA THRMDC STPCLK# LINT0 LINT1 SMI# CPU_RSVD01 CPU_RSVD02 CPU_RSVD03 CPU_RSVD04 CPU_RSVD05 CPU_RSVD06 CPU_RSVD07 CPU_RSVD08 CPU_RSVD09 CPU_RSVD10 H_IERR# H_INIT# BR0# XDP_BPM#5 XDP_BPM#4 19 H_LOCK# 7 H_RESET# 7 H_RS#0 7 H_RS#1 7 H_RS#2 7 H_TRDY# 7 5 H_PWRGOOD_R C7 1 R164 A22 CLK_CPU_BCLK A21 CLK_CPU_BCLK# XDP_TCK 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 NP1 61 2 62 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 63 64 NP2 D 1218 H_RESET#_R R57 1 DY XDP_DBRESET#_R 1 DY R55 XDP_TDO XDP_TRST# XDP_TDI XDP_TMS XDP_PRE 2 68R3J-GP 2 1KR2F-3-GP 2 200R2F-L-GP 1 R64 1D05V_S0 H_RESET# XDP_DBRESET# CLK_CPU_XDP 3 CLK_CPU_XDP# 3 2 0R0402-PAD (Place R1431 with in 200ps (~1") to CPU STC-CONN60A-GP-U1 H_THERMDA H_THERMDC H_THERMTRIP# C120 SCD1U16V2KX-3GP XDP_DBRESET# 20 CPU_PROCHOT# D21 A24 B25 XDP_HOOK1 1D05V_S0 H_HIT# 7 H_HITM# 7 THERMAL A20M# FERR# IGNNE# H_SMI# H_A20M# H_FERR# H_IGNNE# D20 B3 HIT# HITM# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADSTB1# IERR# INIT# RESET# RS0# RS1# RS2# TRDY# ICH 19 19 19 Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 H_BR0# LOCK# ADDR GROUP 1 H_ADSTB#1 19 19 19 REQ0# REQ1# REQ2# REQ3# REQ4# H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1 C 7 K3 H2 K2 J3 L1 F1 7 7 7 1 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_DEFER# H_DRDY# H_DBSY# DEFER# DRDY# DBSY# H_ADS# H_BNR# H_BPRI# 1 1D05V_S0 2 7 7 7 7 7 H5 F21 E1 ADS# BNR# BPRI# XDP/ITP SIGNALS H_ADSTB#0 H1 E2 G5 H_ADS# H_BNR# H_BPRI# RESERVED 7 A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB0# H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 D J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 ADDR GROUP 0 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0 0630 Connector Vendor :SmaTec Part Number : QSH-030-01-F-D-TR 35 1D05V_S0 C H_THERMDA 22 H_THERMDC 22 H_THERMTRIP# 7,19 H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3 layout note:Zo =55 ohm , 0.5" MAX for GTLREF layout note : Change R237 to 649 ohm if using XTP to ITP adapter 3D3V_S0 R59 KEY_NC XDP_DBRESET# 1 BGA479-SKT6-GPU3 2 1KR2J-1-GP 1D05V_S0 original value:BGA479-SKT6-GPU1 XDP_TDI R61 XDP_TMS B R60 XDP_TDO R63 XDP_BPM#5 R89 XDP_HOOK1 R75 1 2 1 2 1 2 1 2 1 2 54D9R2F-L1-GP B 54D9R2F-L1-GP 54D9R2F-L1-GP 54D9R2F-L1-GP 54D9R2F-L1-GP DY XDP_TRST# R58 1D05V_S0 XDP_TCK 2 1 2 51R2F-2-GP 54D9R2F-L1-GP 1 R74 1 R165 56R2J-4-GP B 2 DY CPU_PROCHOT# E C DY Q10 OCP# 20 MMBT3904WT1G-GP A <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Meron(1/3)-AGTL+/XDP Size Custom Date: Document Number Rev SC Pamirs-Discrete Tuesday, December 19, 2006 Sheet 4 of 47
- 5. 5 4 3 7 H_D#[0..63] 2 1 VCC_CORE_S0 U62B 2 OF 4 VCC_CORE_S0 U62C 3 OF 4 3 CPU_BSEL0 3 CPU_BSEL1 3 CPU_BSEL2 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 B22 B23 C21 COMP0 COMP1 COMP2 COMP3 E5 B5 D24 D6 D7 AE6 H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# PSI# R171 R172 R132 R131 1 1 1 1 2 2 27D4R2F-L1-GP 2 54D9R2F-L1-GP 2 27D4R2F-L1-GP 54D9R2F-L1-GP H_DPRSTP# 7,19 H_DPSLP# 19 H_DPWR# 7 H_PWRGOOD 19 H_CPUSLP# 7 PSI# 35 R145 BGA479-SKT6-GPU3 PLACE C173 make sure routing is away other close to the TEST4 PIN, TEST3,TEST4,TEST5 trace reference to GND and noisy signals 166 200 CPU_BSEL2 0 0 CPU_BSEL1 2 H_PWRGOOD_R 4 1KR2J-1-GP B CPU_BSEL 1 Resistor Placed within 0.5" of CPU pin. Trace should be at least 25 mils away from any other toggling signal . COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils . CPU_BSEL0 1 1 1 0 D 1D05V_S0 R155 1 R146 1 C 2 2 0R2J-2-GP 0R2J-2-GP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 VCCA VCCA B26 C26 VID0 VID1 VID2 VID3 VID4 VID5 VID6 AD6 AF5 AE5 AF4 AE3 AF3 AE2 CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 VCCSENSE AF7 VCC_SENSE VSSSENSE AE7 VSS_SENSE BGA479-SKT6-GPU3 TC7 1 DATA GRP2 R26 U26 AA1 Y1 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# BSEL0 BSEL1 BSEL2 COMP0 COMP1 COMP2 COMP3 H_DSTBN#3 7 H_DSTBP#3 7 H_DINV#3 7 AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 DY 1D5V_S0 layout note: place C3 near PIN B26 C298 VCC_SENSE VSS_SENSE CPU_VID[0..6] 35 VCC_SENSE 35 VSS_SENSE 35 1 2 R143 100R2F-L1-GP-U 1 DY MISC H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 2 TPAD28 TP3 TPAD28 TP21 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC SCD01U16V2KX-3GP 2 C296 1 AD26 C23 D25 C24 AF26 AF1 A26 TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3# DINV3# H_DSTBN#2 7 H_DSTBP#2 7 H_DINV#2 7 A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 2 V_CPU_GTLREF TPAD28 TP19 TPAD28 TP22 TPAD28 TP20 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2 1 SCD1U16V2KX-3GP H_DSTBN#1 H_DSTBP#1 H_DINV#1 Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 SE330U2VDM-6-GP 7 7 7 D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1# DATA GRP1 DATA GRP1 C N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# DSTBN2# DSTBP2# DINV2# 2 H_DSTBN#0 H_DSTBP#0 H_DINV#0 DATA GRP3 7 7 7 D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0# H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1 D E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 DATA GRP0 DATA GRP0 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0 C303 SC10U10V5ZY-1GP Length match within 25 mils . The trace width/space/other is 20/7/25 . B VCC_CORE_S0 1 2 R142 100R2F-L1-GP-U Close to CPU pin within 500mils SCD01U16V2KX-3GP R423 2KR2F-3-GP C602 1 V_CPU_GTLREF <Core Design> 2 1 1 R422 1KR2F-3-GP 2 A Close to CPU pin AD26 Z0=55 ohm with in 500mils . 2 1D05V_S0 A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Meron(2/3)-AGTL+/PWR Size A3 Document Number Rev SC Pamirs-Discrete Date: Tuesday, December 19, 2006 Sheet 5 of 47
- 6. 5 4 3 2 1 VCC_CORE_S0 2 1 C286 SC10U10V5KX-2GP SC10U10V5KX-2GP 1 C288 2 SC10U10V5KX-2GP 1 C284 DY 2 2 1 C277 SC10U10V5KX-2GP SC10U10V5KX-2GP 1 C274 DY 2 SC10U10V5KX-2GP 1 C271 2 2 1 C263 SC10U10V5KX-2GP 1 2 Place these capacitors on L1 (North side ,Secondary Layer) D VCC_CORE_S0 SC10U10V5KX-2GP 1 C259 2 SC10U10V5KX-2GP 1 C278 2 SC10U10V5KX-2GP 1 C269 2 SC10U10V5KX-2GP 1 C287 2 SC10U10V5KX-2GP 1 C267 DY 2 2 1 C275 SC10U10V5KX-2GP 1 2 Place these capacitors on L1 (North side ,Secondary Layer) SC10U10V5KX-2GP C281 C Mid Frequencd Decoupling B 2 C292 SCD1U16V2KX-3GP 1 2 C293 SCD1U16V2KX-3GP 1 2 C247 SCD1U16V2KX-3GP 1 C249 SCD1U16V2KX-3GP 1 C246 SCD1U16V2KX-3GP 2 1D05V_S0 2 B P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25 1 C VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 2 D 4 OF 4 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 1 U62D A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 SC10U10V5KX-2GP C252 C291 SCD1U16V2KX-3GP Place these inside socket cavity on L1 (North side Secondary) BGA479-SKT6-GPU3 <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Meron(3/3)-GND&Bypass Size A3 Document Number Rev SC Pamirs-Discrete Date: Monday, December 18, 2006 Sheet 6 of 47
- 7. B6 E5 H_RS#0 H_RS#1 H_RS#2 H_CPURST# H_CPUSLP# H_AVREF H_DVREF H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 E12 D7 D8 H_RS#0 H_RS#1 H_RS#2 2 1 R400 2 10KR2J-3-GP CLKREQ#_B 1 R399 2 10KR2J-3-GP TP49 TP54 TP51 TP55 TP56 TP48 TP52 TP50 TP57 CFG16 TP47 TP46 TP45 From Astro demo schematic 4 4 4 4 4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 TP53 CFG[17:3] have internal pull up CFG[19:18] have internal pull down CFG18 CFG19 CFG20 4 4 4 CRESTLINE-GP-U layout note : Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces 20 PM_BMBUSY# 5,19 H_DPRSTP# 13 PM_EXTTS#0 14 PM_EXTTS#1 4,19 H_THERMTRIP# 20,35 DPRSLPVR R112 1 20,22 PM_PWROK 20,35 VGATE_PWRGD 1D05V_S0 R114 1 DY PM_POK_R 2 2 0R2J-2-GP 1 1 2 H_SWNG SA 0928 2 1 1 1 Layout Note : Place C151 within 100 mils of NB R163 100R2F-L1-GP-U 2 SCD1U16V2ZY-2GP 1 2 2 A R168 24D9R2F-L-GP 2 2 1 C290 H_RCOMP C295 SCD1U16V2ZY-2GP SM_CS#0 SM_CS#1 SM_CS#2 SM_CS#3 BG20 DDR_CS0_DIMMA# BK16 DDR_CS1_DIMMA# BG16 DDR_CS2_DIMMB# BE13 DDR_CS3_DIMMB# DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# 13 13 14 14 BH18 BJ15 BJ14 BE16 M_ODT0 M_ODT1 M_ODT2 M_ODT3 BK31 BL31 SM_RCOMP_VOH SM_RCOMP_VOL SM_RCOMP SM_RCOMP# BL15 BK14 SM_RCOMP SM_RCOMP# SM_VREF#AR49 SM_VREF#AW4 AR49 AW4 DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# M_ODT0 M_ODT1 M_ODT2 M_ODT3 D 13 13 14 14 1D8V_S3 1 R154 1 R413 2 2 20R2F-GP 20R2F-GP DDR_VREF_S3 DDR_VREF_S3 B42 C42 H48 H47 PEG_CLK PEG_CLK# K44 CLK_MCH_3GPLL K45 CLK_MCH_3GPLL# DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 AN47 AJ38 AN42 AN46 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 AM47 AJ39 AN41 AN45 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 AJ46 AJ41 AM40 AM44 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#0 PM_EXT_TS#1 PWROK RSTIN# THERMTRIP# DPRSLPVR 1 R597 2 2K2R2J-2-GP BJ51 BK51 BK50 BL50 BL49 BL3 BL2 BK1 BJ1 E1 A5 C51 B50 A50 A49 BK2 NC#BJ51 NC#BK51 NC#BK50 NC#BL50 NC#BL49 NC#BL3 NC#BL2 NC#BK1 NC#BJ1 NC#E1 NC#A5 NC#C51 NC#B50 NC#A50 NC#A49 NC#BK2 NC NC R157 2KR2F-3-GP R162 221R2F-2-GP H_VREF G41 L39 L36 J36 AW49 AV20 N20 G36 13 13 14 14 13 13 14 14 AJ47 AJ42 AM39 AM43 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 CLK_MCH_3GPLL 3 CLK_MCH_3GPLL# 3 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 20 20 20 20 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 20 20 20 20 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 20 20 20 20 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 20 20 20 20 C 2D5V_S0 R401 R402 2K2R2J-2-GP 2K2R2J-2-GP DY DY ICH_SDVO_DATA ICH_SDVO_CLK GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VR_EN E35 A39 C38 B39 E36 CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF AM49 AK50 AT43 AN49 AM50 DFGT_VID0 DFGT_VID1 DFGT_VID2 DFGT_VID3 DFGT_VR_EN TP44 TP11 TP15 TP12 TP14 B 1D25V_S0 0R2J-2-GP 1D05V_S0 R158 1KR2F-3-GP PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PM_POK_R PLT_RST_R# H_THERMTRIP# DPRSLPVR P27 N27 N24 C21 C23 F23 N23 G23 J20 C20 R24 L23 J23 E23 E20 K23 M20 M24 L32 N33 L35 DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB SM_RCOMP_VOH SM_RCOMP_VOL PM PM B Layout Note : H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20 MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 BE29 DDR_CKE0_DIMMA AY32 DDR_CKE1_DIMMA BD39 DDR_CKE2_DIMMB BG37 DDR_CKE3_DIMMB CLK PM_EXTTS#1 SM_CKE0 SM_CKE1 SM_CKE3 SM_CKE4 SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3 1 2 SCD01U25V2KX-3GP 2 C266 2 10KR2J-3-GP M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 1 5 5 5 5 H_RS#0 H_RS#1 H_RS#2 1 R407 AW30 M_CLK_DDR#0 BA23 M_CLK_DDR#1 AW25 M_CLK_DDR#2 AW23 M_CLK_DDR#3 1 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 SM_CK#0 SM_CK#1 SM_CK#3 SM_CK#4 DDR MUXING 1 SCD01U25V2KX-3GP 1 2 1 2 C257 SC2D2U10V3ZY-1GP 2 1 C253 5 5 5 5 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 PM_EXTTS#0 13 13 14 14 2 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 M14 E13 A11 H13 B12 3D3V_S0 RSVD#H10 RSVD#B51 RSVD#BJ20 RSVD#BK22 RSVD#BF19 RSVD#BH20 RSVD#BK18 RSVD#BJ18 RSVD#BF23 RSVD#BG23 RSVD#BC23 RSVD#BD24 RSVD#BJ29 RSVD#BE24 RSVD#BH39 RSVD#AW20 RSVD#BK20 RSVD#C48 RSVD#D47 RSVD#B44 RSVD#C44 RSVD#A35 RSVD#B37 RSVD#B36 RSVD#B34 RSVD#C34 M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 2 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 DDR_A_MA14 DDR_B_MA14 3 MCH_CLKSEL0 3 MCH_CLKSEL1 3 MCH_CLKSEL2 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H10 B51 BJ20 BK22 BF19 BH20 BK18 BJ18 BF23 BG23 BC23 BD24 BJ29 BE24 BH39 AW20 BK20 C48 D47 B44 C44 A35 B37 B36 B34 C34 AV29 BB23 BA25 AV23 2 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 L7 K2 AC2 AJ10 R149 1KR2F-3-GP 13 DDR_A_MA14 14 DDR_B_MA14 5 5 5 5 SM_CK0 SM_CK1 SM_CK3 SM_CK4 CL_CLK0 20 CL_DATA0 20 2 VGATE_PWRGD 20,35 0R2J-2-GP CL_RST# 20 CLPWROK_MCH 1 R410 CL_VREF R115 1KR2F-3-GP 1 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 RSVD#P36 RSVD#P37 RSVD#R35 RSVD#N35 RSVD#AR12 RSVD#AR13 RSVD#AM12 RSVD#AN13 RSVD#J12 RSVD#AR37 RSVD#AM36 RSVD#AL36 RSVD#AM37 RSVD#D20 DMI M7 K3 AD2 AH11 P36 P37 R35 N35 AR12 AR13 AM12 AN13 J12 AR37 AM36 AL36 AM37 D20 R147 1KR2F-3-GP M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 1 H_VREF H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_SCOMP H_SCOMP# B9 A9 H_RESET# H_CPUSLP# H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4 H_BNR# 4 H_BPRI# 4 H_BR0# 4 H_DEFER# 4 H_DBSY# 4 CLK_MCH_BCLK 3 CLK_MCH_BCLK# 3 H_DPWR# 5 H_DRDY# 4 H_HIT# 4 H_HITM# 4 H_LOCK# 4 H_TRDY# 4 FOR Calero: 80.6 ohm Crestline: 20 ohm U23B 2 OF 10 1D8V_S3 R148 3K01R2F-3-GP SM_RCOMP_VOL 1 R116 392R2F-GP C193 SDVO_CTRL_CLK SDVO_CTRL_DATA CLKREQ# ICH_SYNC# TEST1 TEST2 H35 K36 G39 G40 ICH_SDVO_CLK ICH_SDVO_DATA TP43 TP42 CLKREQ#_B 3 MCH_ICH_SYNC# MCH_ICH_SYNC# A37 TEST1_GMCH R32 TEST2_GMCH 1 R406 2 20 1 2 R144 0R2J-2-GP CFG9 2 H_SWING H_RCOMP K5 L2 AD13 AE13 SM_RCOMP_VOH 2 1 4 5 H_RESET# H_CPUSLP# B3 C2 W1 W2 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 3 4 SCD1U16V2KX-3GP 2 H_SCOMP H_SCOMP# H_ADS# G12 H_ADSTB#0 H17 H_ADSTB#1 G20 H_BNR# C8 H_BPRI# E8 H_BR0# F12 H_DEFER# D6 H_DBSY# C10 CLK_MCH_BCLK AM5 CLK_MCH_BCLK# AM7 H_DPWR# H8 H_DRDY# K7 H_HIT# E4 H_HITM# C6 H_LOCK# G10 H_TRDY# B7 H_A#[3..35] GRAPHICS VID 2 H_SWNG H_RCOMP 4 CFG CFG 54D9R2F-L1-GP 1 R178 54D9R2F-L1-GP 2 1 R179 H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19 ME 1D05V_S0 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 MISC C H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 1 D E2 G2 G7 M6 H7 H3 G4 F3 N8 H2 M10 N12 N9 H5 P13 K9 M2 W10 Y8 V4 M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4 W3 N1 AD12 AE3 AD9 AC9 AC7 AC14 AD11 AC11 AB2 AD7 AB1 Y3 AC6 AE2 AC5 AG3 AJ9 AH8 AJ14 AE9 AE11 AH12 AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2 AH13 RSVD RSVD H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 C270 SC2D2U10V3ZY-1GP 1 2 U23A 1 OF 10 5 H_D#[0..63] HOST 5 20KR2J-L2-GP CRESTLINE-GP-U Layout Note : Place C153 near pin B3 of NB 1 R598 ICH_SDVO_DATA 2 2K2R2J-2-GP A <Core Design> R414 PLT_RST_R# 1 2 Wistron Corporation PLT_RST1# 18,20,26,28,31,33,34,41 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 100R2J-2-GP Title CRESTLINE(1/6)-AGTL+/DMI/DDR2 Size Document Number Custom Date: Monday, December 11, 2006 Sheet 7 Rev SA Pamirs-Discrete of 47
- 8. 5 4 3 DDR_A_D[0..63] 1 13 DDR_A_BS[0..2] 2 13 DDR_B_D[0..63] 14 DDR_B_DM[0..7] DDR_A_DM[0..7] D 14 DDR_B_BS[0..2] 14 13 DDR_A_DQS[0..7] DDR_B_DQS[0..7] DDR_A_DQS#[0..7] B A BB19 BK19 BF29 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 SA_CAS# BL17 DDR_A_CAS# SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7 CRESTLINE-GP-U 14 U23E 5 OF 10 SA_BS0 SA_BS1 SA_BS2 DDR SYSTEM MEMORRY A C SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7 SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7 AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 SA_RAS# SA_RCVEN# BE18 AY20 DDR_A_RAS# SA_RCVEN# SA_WE# BA19 DDR_A_WE# DDR_A_CAS# 13 DDR_A_RAS# 13 TP58 DDR_A_WE# 13 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 AP49 AR51 AW50 AW51 AN51 AN50 AV50 AV49 BA50 BB50 BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43 BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40 BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12 BJ10 BL9 BK5 BL5 BK9 BK10 BJ8 BJ6 BF4 BH5 BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2 SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 SB_BS0 SB_BS1 SB_BS2 AY17 BG18 BG36 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 SB_CAS# BE17 DDR_B_CAS# SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7 DDR SYSTEM MEMORY B U23D 4 OF 10 AR43 AW44 BA45 AY46 AR41 AR45 AT42 AW47 BB45 BF48 BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41 AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11 BE10 BD10 BD8 AY9 BG10 AW9 BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8 AN10 AT9 AN9 AM9 AN11 14 13 DDR_B_MA[0..13] DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 14 13 DDR_B_DQS#[0..7] DDR_A_MA[0..13] D 13 AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7 SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7 AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 SB_RAS# SB_RCVEN# AV16 AY18 DDR_B_RAS# SB_RCVEN# BC17 DDR_B_WE# SB_WE# DDR_B_CAS# 14 C DDR_B_RAS# DDR_B_WE# B 14 14 TP59 CRESTLINE-GP-U <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CRESTLINE(2/6)-DDR2 A/B CH Size A3 Document Number Rev SA Pamirs-Discrete Date: Wednesday, October 18, 2006 Sheet 8 of 47
- 9. 5 4 3 1D05V_S0 L41 L43 N41 N40 D46 C45 D44 E42 LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK G51 E51 F49 LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 G50 E50 F48 LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 E44 A47 A45 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 C TVA_DAC TVB_DAC TVC_DAC F27 J27 L27 TVA_RTN TVB_RTN TVC_RTN M35 P33 TV_DCONSEL0 TV_DCONSEL1 TV E27 G27 K27 B CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# K33 G35 E33 C32 F33 CRT_DDC_CLK CRT_DDC_DATA CRT_VSYNC CRT_TVO_IREF CRT_HSYNC VGA H32 G32 K29 J29 F29 E29 N43 M43 PEGCOMP trace width and spacing is 20/25 mils. PEGCOMP PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 G44 B47 B45 PEG_COMPI PEG_COMPO PCI_EXPRESS GRAPHICS D L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN LVDS J40 H39 E39 E40 C37 D35 K40 J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41 PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15 J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42 PEG_RXN15 41 PEG_RXN14 41 PEG_RXN13 41 PEG_RXN12 41 PEG_RXN11 41 PEG_RXN10 41 PEG_RXN9 41 PEG_RXN8 41 PEG_RXN7 41 PEG_RXN6 41 PEG_RXN5 41 PEG_RXN4 41 PEG_RXN3 41 PEG_RXN2 41 PEG_RXN1 41 PEG_RXN0 41 PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9 PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15 PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15 M45 TXP0 T38 TXP1 T46 TXP2 N50 TXP3 R51 TXP4 U43 TXP5 W42 TXP6 Y47 TXP7 Y39 TXP8 AC38 TXP9 AD47 TXP10 AC50 TXP11 AD43 TXP12 AG39 TXP13 AE50 TXP14 AH43 TXP15 C489 C506 C480 C195 C196 C502 C499 C487 C512 C491 C494 C189 C486 C482 C191 C483 C490 C507 C479 C194 C197 C501 C500 C488 C515 C492 C495 C190 C485 C481 C192 C484 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP 010 = FSB 800MHz 011 = FSB 667MHz Others = Reserved CFG[2:0] FSB Freq select CFG5 (DMI select) PEG_RXP15 41 PEG_RXP14 41 PEG_RXP13 41 PEG_RXP12 41 PEG_RXP11 41 PEG_RXP10 41 PEG_RXP9 41 PEG_RXP8 41 PEG_RXP7 41 PEG_RXP6 41 PEG_RXP5 41 PEG_RXP4 41 PEG_RXP3 41 PEG_RXP2 41 PEG_RXP1 41 PEG_RXP0 41 N45 TXN0 U39 TXN1 U47 TXN2 N51 TXN3 R50 TXN4 T42 TXN5 Y43 TXN6 W46 TXN7 W38 TXN8 AD39 TXN9 AC46 TXN10 AC49 TXN11 AC42 TXN12 AH39 TXN13 AE49 TXN14 AH44 TXN15 1 Strap Pin Table 1 2 R398 24D9R2F-L-GP U23C 3 OF 10 2 0 = DMI x 2 1 = DMI x 4 CFG6 D Reserved 0 = Reserved 1 = Mobile CPU CFG7 (CPU Strap) * 0 = Normal mode 1 = Low Power mode CFG8 (Low power PCIE) CFG9 (PCIE Graphics Lane Reversal) * 0 = Reverse Lane 1 = Normal Operation CFG[11:10] * Reserved 00 01 10 11 CFG[13:12] (XOR/ALLZ) CFG[15:14] = = = = Reserved XOR Mode Enabled All Z Mode Enabled Normal Operation (Default)* Reserved 0 = Disable 1 = Enable * CFG16 (FSB Dynamic ODT) PEG_TXP15 41 PEG_TXP14 41 PEG_TXP13 41 PEG_TXP12 41 PEG_TXP11 41 PEG_TXP10 41 PEG_TXP9 41 PEG_TXP8 41 PEG_TXP7 41 PEG_TXP6 41 PEG_TXP5 41 PEG_TXP4 41 PEG_TXP3 41 PEG_TXP2 41 PEG_TXP1 41 PEG_TXP0 41 * CFG[18:17] C Reversed SDVO_CTRLDATA 0 = No SDVO Device Present * 1 = SDVO Device Present 0 = Normal Operation (Lane number in Order) 1 = Reverse lane CFG19(DMI Lane Reversal) * 0 = Only PCIE or SDVO is operational * 1 = PCIE/SDVO are operating simu. CFG20(PCIE/SDVO consurrent) PEG_TXN15 41 PEG_TXN14 41 PEG_TXN13 41 PEG_TXN12 41 PEG_TXN11 41 PEG_TXN10 41 PEG_TXN9 41 PEG_TXN8 41 PEG_TXN7 41 PEG_TXN6 41 PEG_TXN5 41 PEG_TXN4 41 PEG_TXN3 41 PEG_TXN2 41 PEG_TXN1 41 PEG_TXN0 41 B CRESTLINE-GP-U <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 CRESTLINE(3/6)-VGA/LVDS/TV Document Number Rev SA Pamirs-Discrete Date: Monday, December 18, 2006 Sheet 9 of 47
- 10. 5 4 3 2 1 1D25V_S0_AXF R412 1 1 C525 1 2 2 2 1 1 2 2 L46 C300 2 SSM5818SLPT-GP 1 2 1D25V_S0 1 C297 BLM18AG121SN-1GP 3D3V_S0_HV R128 2 2 2 SC10U10V5KX-2GP 1 1 2 1 1 C302 1D05V_S0_D D15 1D05V_S0 1 0R5J-5-GP 0R5J-5-GP B L20 1D05V_S0 R87 SC10U10V5KX-2GP 1 DY 2 1D25V_S0 1D25V_S0 R403 1 2 1 0R2J-2-GP 1 C301 TC3 ST220U2VBM-3GP C299 TC15 2 2 20mil C176 2 C573 BLM18AG121SN-1GP 1D25V_S0_MPLL 2 10R2J-2-GP 3D3V_S0 2 CRESTLINE-GP-U 2 1 HV 2 A7 F2 AH1 VTTLF1 VTTLF2 VTTLF3 R91 1 1 VCCD_LVDS VCCD_LVDS AH50 AH51 1D05V_S0_PEG 2 J41 H42 VTTLF VTTLF VTTLF 1D05V_S0_PEG ST220U2VBM-3GP VCCD_PEG_PLL VCC_RXR_DMI VCC_RXR_DMI AD51 W50 W51 V49 V50 SCD47U16V3ZY-3GP 1D25V_S0_PEGPLL C SC10U10V5KX-2GP C522 VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG 1 VCCD_HPLL U48 C40 B40 1 AN2 VCC_HV VCC_HV SCD47U16V3ZY-3GP 2 1D25V_S0_HPLL SCD22U16V3ZY-GP 1 1 2 1 1 2 2 SC4D7U6D3V3KX-GP 1 2 1 C575 A43 1 VCCD_QDAC 2 1D5V_S0 0R5J-5-GP C537 1 SCD47U16V3ZY-3GP 2 N28 TV/CRT VCCD_CRT VCCD_TVDAC 1D8V_S3 R176 1D25V_S0_HPLL 1 SM CK A SM 1D25V_S0_AXF SCD1U16V2ZY-2GP M32 L29 2 1D8V_S3_SM_CK VTTLF VCCA_TVA_DAC VCCA_TVA_DAC VCCA_TVB_DAC VCCA_TVB_DAC VCCA_TVC_DAC VCCA_TVC_DAC PEG VCCA_SM_CK VCCA_SM_CK A CK BC29 BB29 C536 2 A PEG 2 VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK AXF 1D25V_S0_DMI BK24 BK23 BJ24 BJ23 BLM18PG121SN-1GP D 0R5J-5-GP 1 3D3V_S0_HV C25 B25 C27 B27 B28 A28 1D5V_S0_TVDAC AJ50 VCC_TX_LVDS TV 1 1 2 VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM_NCTF VCCA_SM_NCTF DMI 1 SC1U10V3KX-3GP SCD22U16V3ZY-GP 2 AT22 AT21 AT19 AT18 AT17 AR17 AR16 LVDS 2 SC4D7U25V5KX-GP 1 ST22U6D3VBM-1GP 2 C538 C535 SC1U10V3KX-3GP 2 SCD22U16V3ZY-GP 2 1 C533 C555 B23 B21 A21 SCD1U16V2ZY-2GP B C528 C560 SCD1U16V2ZY-2GP 2 1 2 DY 1 DY 1 1D25V_S0_SM_CK C580 SC10U10V5KX-2GP VCC_AXF VCC_AXF VCC_AXF VCC_DMI VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM C203 C550 1D25V_S0 SCD1U16V2ZY-2GP 0R3-0-U-GP C579 2 TC9 ST100U4VBM-U 1 DY SC1U10V3KX-3GP 2 1 2 2 0R5J-5-GP R173 1 1D25V_S0_A_SM R177 1 AW18 AV19 AU19 AU18 AU17 VCCA_PEG_PLL C185 2 SCD1U16V2ZY-2GP 1D25V_S0 U51 AR29 C540 1D5V_S0_TVDAC L17 1 SCD022U16V2KX-3GP 20mil 1D25V_S0_PEGPLL VCC_AXD_NCTF 1D25V_S0_PEGPLL C546 SC10U10V5KX-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP C C202 SCD1U16V2ZY-2GP C549 DY C542 2 0R5J-5-GP 1D25V_S0 R117 1 1D25V_S0 0R3-0-U-GP 1 VSSA_PEG_BG 1D25V_S0 R175 1 2 2 K49 1 0R3-0-U-GP 1D25V_S0_AXD AT23 AU28 AU24 AT29 AT25 AT30 1D8V_S3_SM_CK 2 VCCA_PEG_BG 2 VCC_AXD VCC_AXD VCC_AXD VCC_AXD VCC_AXD VCC_AXD C198 1 K50 2 R107 1 POWER C565 2 VSSA_LVDS SC1KP50V2KX-1GP 3D3V_S0_PEG_BG 1D25V_S0_DMI R105 1 SC2D2U6D3V3MX-1-GP VCCA_LVDS B41 C517 3D3V_S0 SC4D7U6D3V3KX-GP VCCA_MPLL A41 1D8V_S0_TXLVDS SC1U10V3KX-3GP AM2 AXD VCCA_HPLL 1D25V_S0_MPLL PLL AL2 A LVDS VCCA_DPLLB 1D25V_S0_HPLL C520 2 0R3-0-U-GP C548 SC1U16V3ZY-GP SCD1U16V2ZY-2GP VCCA_DPLLA C521 SCD1U16V2ZY-2GP B49 H49 C547 SC10U10V5KX-2GP 1 VSSA_DAC_BG TC17 2 VCCA_DAC_BG B32 DY 2 A30 U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1 1 VCCA_CRT_DAC VCCA_CRT_DAC VTT A33 B33 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT SCD47U16V3ZY-3GP 2 1 VCC_SYNC 2 J32 CRT D 1 ST220U2VBM-3GP SCD22U16V3ZY-GP U23H 8 OF 10 1 1D05V_S0 C518 SCD1U16V2KX-3GP <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 CRESTLINE(4/6)-PWR Document Number Rev SA Pamirs-Discrete Date: Thursday, December 14, 2006 Sheet 10 of 47
- 11. 5 4 3 2 1 1D05V_S0 1D05V_S0 LIB C U23F 6 OF 10 A SCD22U10V2KX-1GP 2 1 SC4D7U6D3V3KX-GP 2 1 1 C187 1 SC1U10V3KX-3GP 2 SC1U10V3KX-3GP C186 C188 1 SCD47U16V3ZY-3GP 2 C576 1 SCD22U10V2KX-1GP C559 2 1 CRESTLINE-GP-U SCD22U10V2KX-1GP 2 VCC GFX NCTF 2 VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7 C567 1 1 2 AW45 BC39 BE39 BD17 BD4 AW8 AT6 2 1 2 1 2 VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF B SCD1U16V2ZY-2GP 1 10R2J-2-GP VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG C568 1 2 C557 SC10U10V5KX-2GP R20 T14 W13 W14 Y12 AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31 AJ20 AN14 1 R408 K SC10U10V5KX-2GP C551 D C545 C 2 D33 A 2 1 2 3D3V_S0 TC20 C553 2 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD22U10V2KX-1GP SCD1U16V2ZY-2GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP 1D05V_S0 1 1D05V_S0 VCC SM LF 1 1 SC22U6D3V5MX-2GP 2 1 2 SC22U6D3V5MX-2GP 2 1D05V_S0 CRESTLINE-GP-U CH751H-40PT-1GP 2 0R2J-2-GP 0R2J-2-GP 0R2J-2-GP 0R2J-2-GP 0R2J-2-GP 0R2J-2-GP VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC SM 2 2 2 2 2 2 AU32 AU33 AU35 AV33 AW33 AW35 AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33 BJ34 BK32 BK33 BK34 BK35 BL33 AU30 VCC GFX DY DY DY DY DY DY ST220U2VBM-3GP 1 AT33 AT31 AK29 AK24 AK23 AJ26 AJ23 1 R166 1 R167 1 R169 1 R170 1 R113 1 R120 SC1U10V3KX-3GP C558 VCC_AXM VCC_AXM VCC_AXM VCC_AXM VCC_AXM VCC_AXM VCC_AXM MCHGND1 MCHGND2 MCHGND3 MCHGND4 MCHGND5 MCHGND6 ST220U2VBM-3GP VSS NCTF VCC NCTF VSS SCB A3 B2 C1 BL1 BL51 A51 VSS AXM NCTF 1 2 1 VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VSS_SCB VSS_SCB VSS_SCB VSS_SCB VSS_SCB VSS_SCB 2 1 2 1 1 2 2 1 2 DY SCD1U16V2ZY-2GP 1 TC4 C556 2 POWER 1D8V_S3 C524 SCD01U16V2KX-3GP C531 C529 C532 C527 C552 0R3-0-U-GP T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31 SCD1U16V2ZY-2GP VCC R409 1 C261 B T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28 POWER 1D05V_S0 AL24 AL26 AL28 C563 AM26 C566 AM28 SC10U10V5KX-2GP AM29 SC10U10V5KX-2GP AM31 AM32 AM33 AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33 VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF C530 C VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VSS AXM 1 2 1 1 1 2 2 SC22U6D3V5MX-2GP 2 SCD1U16V2ZY-2GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP ST220U2VBM-3GP 2 C543 C544 C544 C534 TC8 C574 1 D AB33 AB36 AB37 AC33 AC35 AC36 AD35 AD36 AF33 AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36 AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35 AP36 AR35 AR36 Y32 Y33 Y35 Y36 Y37 T30 T34 T35 U29 U31 U32 U33 U35 U36 V32 V33 V36 V37 VCC CORE 2VCC_GMCH1 R30 U23G 7 OF 10 1D05V_S0 VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF SCD1U16V2ZY-2GP VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC C539 AT35 AT34 AH28 AC32 AC31 AK32 AJ31 AJ28 AH32 AH31 AH29 AF32 A <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CRESTLINE(5/6)-PWR/GND Document Number Size Custom Rev SA Pamirs-Discrete Date: Monday, December 18, 2006 Sheet 11 of 47
- 12. 5 4 U23I D C B A A13 A15 A17 A24 AA21 AA24 AA29 AB20 AB23 AB26 AB28 AB31 AC10 AC13 AC3 AC39 AC43 AC47 AD1 AD21 AD26 AD29 AD3 AD41 AD45 AD49 AD5 AD50 AD8 AE10 AE14 AE6 AF20 AF23 AF24 AF31 AG2 AG38 AG43 AG47 AG50 AH3 AH40 AH41 AH7 AH9 AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51 AL1 AM11 AM13 AM3 AM4 AM41 AM45 AN1 AN38 AN39 AN43 AN5 AN7 AP4 AP48 AP50 AR11 AR2 AR39 AR44 AR47 AR7 AT10 AT14 AT41 AT49 AU1 AU23 AU29 AU3 AU36 AU49 AU51 AV39 AV48 AW1 AW12 AW16 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 3 9 OF 10 VSS CRESTLINE-GP-U 2 U23J VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41 C46 C50 C7 D13 D24 D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36 F4 F40 F50 G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48 G8 H24 H28 H4 H45 J11 J16 J2 J24 J28 J33 J35 J39 K12 K47 K8 L1 L17 L20 L24 L28 L3 L33 L49 M28 M42 M46 M49 M5 M50 M9 N11 N14 N17 N29 N32 N36 N39 N44 N49 N7 P19 P2 P23 P3 P50 R49 T39 T43 T47 U41 U45 U50 V2 V3 1 10 OF 10 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28 VSS VSS VSS VSS VSS VSS VSS VSS AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50 D C VSS B CRESTLINE-GP-U <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 CRESTLINE(6/6)-PWR/GND Document Number Rev SA Pamirs-Discrete Date: Wednesday, October 18, 2006 Sheet 12 of 47
- 13. 5 4 3 2 8 DDR_A_DQS#[0..7] DM2 1 2 2 TC5 ST220U2VBM-3GP 1 1 2 1 C224 SCD1U16V2ZY-2GP 2 1 C231 SCD1U16V2ZY-2GP 2 1 C242 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP 2 1 C217 SCD1U16V2ZY-2GP SC2D2U16V5ZY-2GP 2 1 C272 Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS DDR_VREF_S0 1 C227 C255 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP 2 1 C216 2 1 C241 2 1 C204 2 1 C519 2 1 C523 2 1 C514 2 1 DY C516 2 1 C509 2 1 DY 2 1 C511 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP 2 1 DY C498 2 C503 SCD1U16V2ZY-2GP 2 1 DY B Layout Note: Place these resistors closely DM1,all trace length Max=1.5" DDR_VREF_S0 SRN56J-4-GP DDR_A_BS2 1 DDR_CKE0_DIMMA 2 RN55 SRN56J-4-GP DDR_A_MA7 4 1 DDR_A_MA6 3 2 11 29 49 68 129 146 167 186 RN58 SRN56J-4-GP 1 4 2 3 4 3 RN11 SRN56J-4-GP DDR_A_MA12 1 DDR_A_MA9 2 DDR_A_MA10 DDR_A_BS0 RN20 SRN56J-4-GP 1 4 2 3 4 3 RN56 SRN56J-4-GP DDR_A_MA4 1 DDR_A_MA2 2 13 31 51 70 131 148 169 188 DDR_A_WE# DDR_CS1_DIMMA# RN23 SRN56J-4-GP 1 4 2 3 4 3 RN57 SRN56J-4-GP DDR_A_MA0 1 DDR_A_BS1 2 M_ODT1 DDR_A_CAS# RN26 SRN56J-4-GP 1 4 2 3 4 3 RN59 SRN56J-4-GP M_ODT0 1 DDR_A_MA13 2 RN53 SRN56J-4-GP DDR_CKE1_DIMMA 1 4 2 3 4 3 RN54 SRN56J-4-GP 1 DDR_A_MA14 DDR_A_MA11 2 DDR_VREF_S3 7 7 M_ODT0 M_ODT1 DDR_VREF_S3 114 119 DDR_CKE0_DIMMA 7 DDR_CKE1_DIMMA 7 30 32 M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR0 7 M_CLK_DDR#0 7 164 166 M_CLK_DDR1 M_CLK_DDR#1 M_CLK_DDR1 7 M_CLK_DDR#1 7 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 OTD0 OTD1 1 2 SC2D2U16V5ZY-2GP DDR_CKE0_DIMMA DDR_CKE1_DIMMA CK1 CK1# DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DDR_CS0_DIMMA# 7 DDR_CS1_DIMMA# 7 79 80 CK0 CK0# DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DDR_CS0_DIMMA# DDR_CS1_DIMMA# 10 26 52 67 130 147 170 185 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 ICH_SMBDATA ICH_SMBCLK SDA SCL 195 197 VDDSPD 199 SA0 SA1 198 200 NC#50 NC#69 NC#83 NC#120 NC#163/TEST 50 69 83 120 163 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD DDR_A_RAS# 8 DDR_A_WE# 8 DDR_A_CAS# 8 D 81 82 87 88 95 96 103 104 111 112 117 118 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196 ICH_SMBDATA 3,14,20 ICH_SMBCLK 3,14,20 SCD1U16V2ZY-2GP R416 1 R417 1 2 10KR2J-3-GP 2 10KR2J-3-GP 3D3V_S0 C569 PM_EXTTS#0 7 C571 SC2D2U6D3V3KX-GP 1D8V_S3 VREF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 202 GND GND 201 MH1 MH1 MH2 MH2 C B 1 DDR_A_RAS# DDR_CS0_DIMMA# C76 C82 2 RN17 SRN56J-4-GP 1 4 2 3 1 DDR_A_MA3 DDR_A_MA1 A RN8 4 3 2 DDR_A_MA8 DDR_A_MA5 RN13 SRN56J-4-GP 1 4 2 3 110 115 CKE0 CKE1 DY C262 SC2D2U16V5ZY-2GP SC2D2U16V5ZY-2GP 2 DY C251 2 1 C238 SC2D2U16V5ZY-2GP C SC2D2U16V5ZY-2GP 2 1 DY C213 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 M_ODT0 M_ODT1 1D8V_S3 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 7 DDR_A_MA14 DDR_A_RAS# DDR_A_WE# DDR_A_CAS# CS0# CS1# BA0 BA1 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 8 DDR_A_BS[0..2] Layout Note: Place near DM1 107 106 DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 8 DDR_A_MA[0..13] 108 109 113 1 DDR_A_BS0 DDR_A_BS1 8 DDR_A_DQS[0..7] RAS# WE# CAS# A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 2 DDR_A_BS2 8 DDR_A_DM[0..7] 102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 1 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 2 8 DDR_A_D[0..63] D 1 A <Core Design> SCD1U16V2ZY-2GP Wistron Corporation DDR2-200P-20-GP-U 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title DDRII-SODIMM SLOT1 Size Custom Document Number Rev Pamirs-Discrete Date: Wednesday, October 18, 2006 5 4 3 2 Sheet 13 1 SA of 47
- 14. 5 4 3 2 1 8 DDR_B_DQS#[0..7] 8 DDR_B_D[0..63] DM1 8 DDR_B_DM[0..7] DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA0 DDR_B_BS1 SRN56J-4-GP 1 4 2 3 4 3 RN22 DDR_CS2_DIMMB# DDR_B_RAS# SRN56J-4-GP 1 4 2 3 4 3 RN24 DDR_B_WE# DDR_B_CAS# SRN56J-4-GP 1 4 2 3 4 3 RN27 DDR_CS3_DIMMB# M_ODT3 1 2 RN9 DDR_B_MA14 SRN56J-4-GP 4 3 SRN56J-4-GP 1 4 2 3 DDR_B_MA12 DDR_B_MA9 RN7 RN14 198 200 NC#50 NC#69 NC#83 NC#120 NC#163/TEST 50 69 83 120 163 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 81 82 87 88 95 96 103 104 111 112 117 118 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196 RN16 RN25 GND 201 MH1 MH2 MH2 1 2 1 SRN56J-4-GP M_ODT2 1 DDR_B_MA13 2 RN6 SRN56J-4-GP DDR_B_BS2 1 DDR_CKE2_DIMMB 2 DDR_VREF_S3 7 7 M_ODT2 M_ODT3 DDR_VREF_S3 SC2D2U16V5ZY-2GP SCD1U16V2ZY-2GP R420 1 R421 1 2 10KR2J-3-GP 2 10KR2J-3-GP 3D3V_S0 3D3V_S0 C578 PM_EXTTS#1 7 C577 SC2D2U6D3V3KX-GP C 1D8V_S3 B A 1 1 C77 2 C71 2 ICH_SMBDATA 3,13,20 ICH_SMBCLK 3,13,20 1 GND SRN56J-4-GP DDR_B_MA4 1 DDR_B_MA2 2 D 2 VREF VSS SRN56J-4-GP DDR_B_MA7 1 DDR_B_MA6 2 SRN56J-4-GP A SA0 SA1 OTD0 OTD1 SRN56J-4-GP DDR_B_MA5 1 DDR_B_MA8 2 RN12 4 3 VDDSPD 1 2 SRN56J-4-GP DDR_CKE3_DIMMB 1 DDR_B_MA11 2 4 3 ICH_SMBDATA ICH_SMBCLK 114 119 2 1 2 1 2 1 2 1 2 1 2 1 2 195 197 199 DDR_B_RAS# 8 DDR_B_WE# 8 DDR_B_CAS# 8 1 1 2 1 1 2 2 2 1 1 1 2 1 4 3 RN19 DDR_B_MA10 DDR_B_BS0 RN10 4 3 SDA SCL M_ODT2 M_ODT3 SCD1U16V2ZY-2GP SRN56J-4-GP 1 4 2 3 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP RN21 DDR_B_MA3 DDR_B_MA1 10 26 52 67 130 147 170 185 13 31 51 70 131 148 169 188 C225 Layout Note: Place these resistors closely DM2,all trace length Max=1.5" DDR_VREF_S0 SRN56J-4-GP 1 4 2 3 M_CLK_DDR3 7 M_CLK_DDR#3 7 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# C183 B RN18 M_CLK_DDR3 M_CLK_DDR#3 11 29 49 68 129 146 167 186 C215 SCD1U16V2ZY-2GP 2 1 C237 SCD1U16V2ZY-2GP 2 1 C243 SCD1U16V2ZY-2GP 2 1 C235 SCD1U16V2ZY-2GP 2 1 C226 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP 2 C265 164 166 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SCD1U16V2ZY-2GP C234 M_CLK_DDR2 7 M_CLK_DDR#2 7 CK1 CK1# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DY C207 M_CLK_DDR2 M_CLK_DDR#2 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 DY C184 30 32 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 DDR_VREF_S0 C256 DDR_CKE2_DIMMB 7 DDR_CKE3_DIMMB 7 CK0 CK0# BA0 BA1 C C245 CKE0 CKE1 107 106 Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS DY DDR_CS2_DIMMB# 7 DDR_CS3_DIMMB# 7 DDR_CKE2_DIMMB DDR_CKE3_DIMMB DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 C221 SCD1U16V2ZY-2GP 2 1 C170 SCD1U16V2ZY-2GP 2 1 C513 SCD1U16V2ZY-2GP 2 1 C232 SC2D2U16V5ZY-2GP SC2D2U16V5ZY-2GP 2 1 C497 SC2D2U16V5ZY-2GP SC2D2U16V5ZY-2GP SC2D2U16V5ZY-2GP SC2D2U16V5ZY-2GP SC2D2U16V5ZY-2GP 2 C244 DDR_CS2_DIMMB# DDR_CS3_DIMMB# 79 80 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 DY C508 110 115 DDR_B_BS0 DDR_B_BS1 7 DDR_B_MA14 C541 CS0# CS1# C264 1D8V_S3 DY DDR_B_RAS# DDR_B_WE# DDR_B_CAS# DDR_B_BS2 8 DDR_B_BS[0..2] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 2 Layout Note: Place near DM2 108 109 113 DY 8 DDR_B_MA[0..13] D RAS# WE# CAS# 102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 8 DDR_B_DQS[0..7] 202 MH1 <Core Design> Wistron Corporation SCD1U16V2ZY-2GP DDR2-200P-21-GP-U 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title DDRII-SODIMM SLOT2 Size Custom Date: 5 4 3 2 Document Number Rev Pamirs-Discrete Wednesday, October 18, 2006 Sheet 1 14 SA of 47
- 15. A B C D CRT I/F & CONNECTOR E 5V_CRT_S0 5V_S0 F1 42 1 C13 2 FUSE-1D1A6V-8GP SCD01U16V2KX-3GP K L8 1 VGA_RED CRT_R 2 CRT_R CH751H-40PT-1GP D4 5V_CRT1_S0 4 17 1 2 4 1 A 2 Layout Note: Place these resistors close to the CRT-out connector BLM18BB470SN1-GP L2 CRT_B 17 17 13 JVGA_HS 14 JVGA_VS DDC_CLK_CON 15 DY 3 U3 GMCH_HSYNC 1 C15 SC33P50V2JN-3GP DY DY 5 3 SC22P50V2JN-4GP 2 8 C9 CRT_G 4 6 C20 C11 SC33P50V2JN-3GP DY SC22P50V2JN-4GP 1 1 20.20424.015 5V_CRT1_S0 2 2 5V_CRT1_S0 7 3 DDC_DATA_CON 12 1 1 1 1 CRT_B 11 16 2 DDC_DATA_CON 7 2 8 3 9 4 10 5 CRT_G 2 2 2 2 D11 C21 SC10P50V2JN-4GP Layout Note: * Must be a ground return path between this ground and the ground on the VGA connector. Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN. C26 SC10P50V2JN-4GP SC10P50V2JN-4GP SC10P50V2JN-4GP 2 C32 2 BLM18BB470SN1-GP 2 C22 6 1 CRT_R CRT_B 2 1 1 C29 SC10P50V2JN-4GP SC10P50V2JN-4GP SC10P50V2JN-4GP 150R2F-1-GP 150R2F-1-GP 150R2F-1-GP 2 C35 R19 2 R20 1 1 1 1 BLM18BB470SN1-GP L1 R23 SRN2K2J-1-GP CRT1 17 4 3 CRT_G 2 42 VGA_BLUE 1 CRT_G 2 1 1 2 42 VGA_GREEN RN1 1 3 BAV99W-1-GP D12 CRT_R 2 Hsync & Vsync level shift DDC_CLK_CON GMCH_VSYNC DY 3 3D3V_S0 CRT_B PACDN009MR-GP-U 1 4 3 5V_S0 3D3V_S0 RN2 SRN2K2J-1-GP C464 SCD1U16V2ZY-2GP PR_INSERT 17 1 14 1 2 2 1 BAV99W-1-GP 2 5 17,42 GMCH_VSYNC 3 7 4 14 17,42 GMCH_HSYNC U6A HSYNC_5 U1 TSAHCT125PW-GP RN4 VSYNC_5 6 2 1 2 4 3 JVGA_HS JVGA_VS 4 7 SRN33J-5-GP-U U6B TSAHCT125PW-GP DDC_CLK_CON 17 DDC_CLK_CON 3 5 42 VGA_DDCDATA 6 DDC_DATA_CON 2 1 DDC_DATA_CON 17 2 VGA_DDCCLK 42 2N7002DW-1-GP TV OUT CONN L32 C432 C431 BLM18BB470SN1-GP TV_LUMA TV_CRMA TV_COMP 2 2 LUMA CRMA COMP NC#5 2 4 6 7 5 SC10P50V2JN-4GP 1 3 8 9 2 BAV99W-1-GP DY D3 3D3V_S0 2 VGA_TV_LUMA TV_COMP 17 3 SC10P50V2JN-4GP 2 2 1 SC10P50V2JN-4GP 1 3D3V_S0 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. VGA_TV_CRMA C438 C437 BLM18BB470SN1-GP 3 1 Title C2 SCD1U16V2ZY-2GP DY SC10P50V2JN-4GP BAV99W-1-GP 2 SC10P50V2JN-4GP 1 TV_LUMA 17 2 2 2 1 2 Wistron Corporation 2 1 1 42 VGA_TV_LUMA 1 <Core Design> DY D2 R2 150R2F-1-GP C3 SCD1U16V2ZY-2GP DY BAV99W-1-GP L34 Place this 2 resistors close to the TV-out connector C1 SCD1U16V2ZY-2GP DY 1 1 GND GND GND GND 1 2 2 1 NC#2 C434 C433 BLM18BB470SN1-GP 2 1 R3 150R2F-1-GP VGA_TV_COMP 3 MINDIN7-16-GP-U L33 1 1 TV1 1 1 1 TV_CRMA 17 SC10P50V2JN-4GP 42 VGA_TV_COMP 5V @ ext. CRT side 2 2 1 1 42 VGA_TV_CRMA 2 connector R1 150R2F-1-GP 3D3V_S0 D1 B C Document Number Rev Pamirs-Discrete Date: Friday, November 24, 2006 DY A CRT/TV Connector Size A3 D Sheet E 15 SA of 47
- 16. LED / INVERTER INTERFACE I=3.57 mA 5V_S5 R592 LED5 1 2 Q34 2CHG_LED# 1 C LED-B-27-U-GP 255R2F-L-GP R1 E B CHG_LED 31 LCD/INV CONN R2 PDTC124EU-1-GP 5V_S3 I=3.57 mA LED4 C R1 E B LCDVDD_S0 PWR_LED 31 PWR_LED# C453 SC10U10V5ZY-1GP 5V_S0 14 U68C LED1 8 10 CAPS_LED 31 42 42 7 BRIGHTNESS_CONN 3D3V_S0 K 1 5V_S0 2 R489 1 5 1 3 2 BLON_OUT DCBATOUT 1 2 C456 C454 C455 4 255R2F-L-GP SCD1U16V2ZY-2GP TP_LED 31 LED3 2 A LED-O-16-GP 6 31 R231 LED2 U35 LDDC_CLK LDDC_DATA 1 TSAHCT08PWR-1GP SCD1U25V2ZY-U 2 2 LED-B-27-U-GP 1 1 255R2F-L-GP 2 2 9 1 1 42 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 C458 SCD1U16V2ZY-2GP 2 R141 3D3V_S0 LCD1 5V_S0 I=3.57 mA 5V_S0 R2 PDTC124EU-1-GP 1 LED-B-27-U-GP 2 2 255R2F-L-GP 33 Q33 1 1 2 2 R591 1 SCD1U16V2ZY-2GP 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 40 41 VGA_TXACLK- 42 VGA_TXACLK+ 42 VGA_TXAOUT0- 42 VGA_TXAOUT0+ 42 VGA_TXAOUT1- 42 VGA_TXAOUT1+ 42 VGA_TXAOUT2- 42 VGA_TXAOUT2+ 42 VGA_TXBCLK- 42 VGA_TXBCLK+ 42 VGA_TXBOUT0- 42 VGA_TXBOUT0+ 42 VGA_TXBOUT1- 42 VGA_TXBOUT1+ 42 VGA_TXBOUT2- 42 VGA_TXBOUT2+ 42 1 ACES-CONN40C-GP-U LED-B-27-U-GP 255R2F-L-GP 20.F0813.040 2N7002DW-1-GP 3D3V_S0 1 5V_S0 5V_S0 R596 14 R569 10KR2J-3-GP LED6 2 1 1 MEDIA_LED# 2 3 2 0R2J-2-GP R343 4 3 7 TSAHCT08PWR-1GP RN52 SRN2K2J-1-GP 1 2 LDDC_DATA LED7 A 2 BRIGHTNESS 31 DY 1 0R2J-2-GP LBKLT_CRTL 42 R346 100KR2J-1-GP DY LDDC_CLK 4 K 6 5 1 C452 1 C450 MS_LED# 25 LED-B-67-GP-U2 7 255R2F-L-GP 2 1 2 U68B 14 NC I=3.6 mA R545 1 1 5V_S0 5V_S0 BRIGHTNESS_CONN SATA_LED# 19 LED-B-27-U-GP 255R2F-L-GP R344 3D3V_S0 CDROM_LED# 23 2 1 U68A 2 I=3.57 mA TSAHCT08PWR-1GP BLON_OUT 2 SC1000P50V3JN-GP BRIGHTNESS_CONN 2 SCD1U16V2ZY-2GP 3D3V_S0 Layout 40 mil LCDVDD_S0 5V_S3 2 U55 2 R330 100KR2J-1-GP IN#1 OUT EN GND GND IN#8 IN#7 IN#6 IN#5 2 1 BC1 SC1U10V3ZY-6GP SCD1U16V2ZY-2GP 2 1 G5281RC1U-GP EC47 9 8 7 6 5 U56 R329 10KR2J-3-GP DY DY 1 1 2 3 4 LCDVDD_EN 1 42 1 LCDVDD_S0 LCDVDD_EN 1 R347 DY 2 100R2J-2-GP 6 2 5 3 4 <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 2N7002DW-1-GP Title LCD/Inverter Connector Size Custom Document Number Date: Tuesday, December 19, 2006 Rev Pamirs-Discrete Sheet 16 of SA 47
- 17. B C 5V_S0 D30 2 PR_INSERT 2 VOL_UP_DK# 3 DY 3 Docking Connector 5V_S0 D29 2 DY VOL_DWN_DK#3 DOCK1 DY 1 1 BAV99W-1-GP BAV99W-1-GP AD+ 15 CRT_R 15 CRT_G 15 CRT_B 15 DDC_DATA_CON 15 DDC_CLK_CON 1 2 28 RJ45-7 28 28 14 10 HSYNC_5_1 7 13 14 DOCK_IN# 12 15,42 GMCH_VSYNC U6C RJ45-4 RJ45-6 RJ45-3 RJ45-2 RJ45-1 28 28 DOCK_IN# 31 8 DCBATOUT TSAHCT125PW-GP RN3 1 2 VSYNC_5_1 11 1 SA C90 SCD1U16V2ZY-2GP 28 9 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 DOCK_HS DOCK_VS USB_7USB_7+ 5V_S0 15,42 GMCH_HSYNC 43 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 BAV99W-1-GP 4 4 3 AD+ 46 NP2 44 1 Hsync & Vsync level shift E 1 5V_S0 D10 D 42 NP1 45 DOCK_HS DOCK_VS AD+ EC45 SCD1U25V3ZY-1GP 2 A 4 TV_LUMA 15 TV_CRMA 15 TV_COMP 15 CIR_PR PWR_ON EAPD#_1 R78 PWR_BTN# 31 R76 JACK_DETECT# 29 VOL_UP_DK# 31 VOL_DWN_DK# 31 SPDIF_DOCK 1 1 2 EAPD# 32 2 0R2J-2-GP MUTE_LED# 31,32 0R2J-2-GP DY AUD_AGND DK_SPKR_R_1 DK_SPKR_L_1 DK_MIC_R_CN_1 DK_MIC_L_CN_1 AUD_AGND DOCK_PRESENT 1 EC80 1 EC23 1 EC15 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 1 EC26 1 EC18 CIR_PR 1 EC54 PWR_ON 1 EC19 VOL_UP_DK# 1 EC52 VOL_DWN_DK# 1 EC22 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 2 SC100P50V2JN-3GP 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP AUD_AGND 41 EAPD# SRN33J-5-GP-U 7 U6D TSAHCT125PW-GP FOX-CONN40-1-GP-U1 DOCK_PRESENT 20.B0045.040 3 PWR_BTN# R371 1 CIR CIR_PR 1 R369 1D5V_S0 2 0R2J-2-GP 2 0R2J-2-GP CIR_SENSE 31 1 29 1 5V_S0 2 0R0402-PAD R94 USB_7+ USB20_P7 Q24 CH3904PT-GP R389 29,41 1 SPDIF 2 1 R90 2 SPDIF_DOCK 1 2 BLM18PG600SN-2GP EC58 SC470P50V2KX-3GP DY EC59 SC470P50V2KX-3GP 2 0R0402-PAD 2 2N7002DW-1-GP DK_SPKR_R 1 L40 DK_SPKR_R_1 2 0R3-0-U-GP 1 1 EC56 SC100P50V2JN-3GP 2 PR_INSERT 29 DK_MIC_R_CN 2 29 1 1 5V_S0 R53 10KR2J-3-GP 15 E 1 USB_7- USB20_N7 1 L39 DY 2 4 R355 100KR2J-1-GP 20 2 5 2 2 6 2 3 2 33R2J-2-GP 1 1 1 R353 DY R390 220R2J-L2-GP 1 2 L-63UH-GP DOCK_IN# 31 DOCK_PRESENT B 330R2J-3-GP TR1 U9 2 2 R351 10KR2J-3-GP 3 4 1 20 C 2 R387 33R3J-2-GP 3 1 L18 EC24 2 DK_MIC_R_CN_1 0R3-0-U-GP SC100P50V2JN-3GP 3D3V_S5 1 1 1 L19 2 DK_MIC_L_CN_1 0R3-0-U-GP EC25 SC100P50V2JN-3GP E U15 C D Q21 CH3906PT-GP 1 R365 3 2 1KR2J-1-GP Q23 2N7002-11-GP G PWR_ON Place near Dock connector Place near Codec 1 BAS40CW-GP R366 10KR2J-3-GP S0 = 4V S3 = 2.5V S5 = 0V <Core Design> 1 Wistron Corporation 2 PM_SLP_S4# 29 DK_MIC_L_CN EC60 SC100P50V2JN-3GP 2 2 B 22KR2J-GP 1 2 R377 1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. S 20,28,31,36,37,38 DK_SPKR_L_1 2 0R3-0-U-GP 5V_S0 R378 22KR2J-GP 1 1 L41 2 1 DK_SPKR_L 2 29 3D3V_S5 Title Board to board conn/ Docking Size A3 Document Number Rev A B C D SA Pamirs-Discrete Date: Friday, November 24, 2006 Sheet E 17 of 47
- 18. 5 4 3 PCI_AD[0..31] 24 PCI_AD[0..31] PCI_FRAME# PCI_GNT1# PCI_REQ1# PCI_REQ2# 8 7 6 5 SRN8K2J-4-GP RN65 1 2 3 4 PCI_GNT3# PCI_REQ3# PCI_SERR# PCI_PIRQG# 8 7 6 5 SRN8K2J-4-GP RN68 1 2 3 4 PCI_GNT#0 PCI_PIRQA# PCI_PLOCK# PCI_PERR# 8 7 6 5 1 2 3 4 1 2 3 4 SRN8K2J-4-GP RN67 PCI_IRDY# 8 7 PCI_TRDY# 6 PCI_PIRQE# PCI_PIRQD# 5 1 2 3 4 C SRN8K2J-4-GP RN69 8 PCI_PIRQH# PCI_PIRQC# 7 PCI_PIRQB# 6 5 PCI_REQ#0 D20 E19 D19 A20 D17 A21 A19 C19 A18 B16 A12 E16 A14 G16 A15 B6 C11 A9 D11 B12 C12 D10 C7 F13 E11 E13 E12 D8 A6 E8 D6 A3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# RN61 1 2 3 4 F9 B5 C5 A10 PIRQA# PIRQB# PIRQC# PIRQD# SRN8K2J-4-GP RN63 8 PCI_PIRQF# 7 PCI_GNT2# 6 PCI_DEVSEL# 5 PCI_STOP# 24 PCI_PIRQA# 24 1 3 U32C OF 6 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 3D3V_S0 D 2 PCI_PIRQC# REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 GNT3#/GPIO55 REQ3#/GPIO54 A4 D7 E18 C18 B19 F18 C10 A11 C/BE0# C/BE1# C/BE2# C/BE3# C17 E15 F16 E17 IRDY# PAR PCIRST# DEVSEL# PERR# FRAME# PLOCK# SERR# STOP# TRDY# C8 D9 G6 D16 A7 A17 B7 F10 C16 C9 PCI_IRDY# PCI_PAR PCI_PCIRST# PCI_DEVSEL# PCI_PERR# PCI_FRAME# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PLTRST# PCICLK PME# AG24 B10 G7 PCI_PLTRST# CLK_PCI_ICH PCI PCI_REQ1# PCI_GNT1# PCI_REQ2# PCI_GNT2# PCI_GNT3# PCI_REQ3# PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5 F8 G11 F12 B3 TP78 D TP80 TP90 PCI_C/BE#0 PCI_C/BE#1 PCI_C/BE#2 PCI_C/BE#3 R486 1 Interrupt I/F PCI_REQ#0 24 PCI_GNT#0 24 PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# 24 24 24 24 PCI_IRDY# 24 PCI_PAR 24 PCI_DEVSEL# 24 PCI_PERR# 24 PCI_FRAME# 24 PCI_SERR# 24,31 PCI_STOP# 24 PCI_TRDY# 24 CLK_PCI_ICH 3 ICH_PME# 24 8K2R2J-3-GP 2 3D3V_S5 1218 C ICH8-M-1-GP-U 3D3V_S5 U43A 14 SRN8K2J-4-GP PCI_PCIRST# 1 3 PCIRST1# 24,27 1 2 SSLVC08APWR-GP 1 7 PCI_GNT3# R257 100KR2J-1-GP 1KR2J-1-GP 1 R255 0R2J-2-GP DY 2 2 Boot BIOS Strap DY B PCI_GNT0# SPI_CS#1 2 R236 B Boot BIOS Location 3D3V_S5 SPI 1 0 PCI 1 A16 swap override Strap 1 U43B 4 6 Low= A16 swap override Enable High= Default * LPC * 3D3V_S5 PCI_GNT#0 2 R260 1 0R2J-2-GP DY 1KR2J-1-GP DY 1 1 1 DY 2 R465 10KR2J-3-GP 2 DY PCI_PLTRST# 23 2 R237 R235 10R2J-2-GP SC8P250V2CC-GP SSLVC08APWR-GP R264 100KR2J-1-GP 1 CLK_PCI_ICH C357 PLT_RST1# 7,20,26,28,31,33,34,41 1 2 Place closely pin B10 A PLT_RST1# 5 7 PCI_GNT3# PCI_PLTRST# 2 1 14 0 20 SPI_CS1# SPI_CS1# <Core Design> DY A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title ICH8(1/4)-PCI/INT Size A3 Document Number Date: Monday, December 18, 2006 5 4 3 2 Rev SA Pamirs-Discrete Sheet 1 18 of 47
- 19. 5 4 3 2 1 +RTCVCC 3D3V_S0 LAN100_SLP 2 330KR2F-L-GP ICH_INTVRMEN 2 330KR2F-L-GP RN64 +RTCVCC 1 U32A OF 6 LPC_LAD[0..3] INTRUDER# AF25 AD21 INTVRMEN LAN100_SLP ICH_INTVRMEN LAN100_SLP B24 TP77 SC15P50V2JN-2-GP LAN_TXD0 LAN_TXD1 LAN_TXD2 AH21 R451 1 1D5V_S0 RN62 1 2 4 3 GLAN_COMP 2 24D9R2F-L-GP HDA_BITCLK D25 C25 AJ16 AJ15 SRN33J-5-GP-U G9 E6 LPC_DRQ0# 1 2 4 3 R459 H_FERR# TP91 TP92 2 1 56R2J-4-GP SATA_TXN0_C SATA_TXP0_C B SATA2RXN SATA2RXP SATA2TXN SATA2TXP AB7 AC6 1 R499 2 24D9R2F-L-GP IGNNE# AF27 H_IGNNE# H_IGNNE# 4 INIT# INTR RCIN# AE24 AC20 AH14 H_INIT# KBRST# H_INIT# 4 H_INTR 4 KBRST# 31 NMI SMI# AD23 AG28 H_NMI H_SMI# H_NMI 4 H_SMI# 4 AA24 H_STPCLK# H_STPCLK# 4 AE27 THRMTRIP_ICH# TP65 TP8 AA23 1 2 R188 within 2" from R184 C IDE_PDD[0..15] IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15 H_THERMTRIP# 4,7 24R2J-GP V1 U2 V3 T1 V4 T5 AB2 T6 T3 R2 T4 V6 V5 U1 V2 U6 AA4 AA1 AB3 Y6 Y5 placed within 2" from ICH8M IDE_PDCS1# 23 IDE_PDCS3# 23 W4 W3 Y2 Y3 Y1 W5 23 IDE_PDA0 23 IDE_PDA1 23 IDE_PDA2 23 DCS1# DCS3# SATARBIAS# SATARBIAS TP67 R182 56R2J-4-GP DA0 DA1 DA2 Within 500 mils H_DPSLP# 1D05V_S0 DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 SATA_CLKN SATA_CLKP AG1 AG2 3 CLK_PCIE_SATA# 3 CLK_PCIE_SATA H_PWRGOOD 5 H_DPSLP# 5 H_FERR# 4 DIOR# DIOW# DDACK# IDEIRQ IORDY DDREQ SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA SC3900P50V2KX-2GP 2 SC3900P50V2KX-2GP 2 H_PWRGOOD SATA0RXN SATA0RXP SATA0TXN SATA0TXP AF2 AF1 AE4 AE3 C372 1 C373 1 AD24 AG29 SATALED# AF6 AF5 AH5 AH6 SATA_LED# TP64 H_DPRSTP# 5,7 FERR# HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34 AF10 GAP-OPEN TP85 16 HDA_SDOUT AE10 AG14 2 H_DPRSTP# H_DPRSTP# THRMTRIP# HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 G72 1 KBGA20 31 H_A20M# 4 H_A20M# H_DPSLP# H_FERR# HDA_RST# AE13 SRN33J-5-GP-U AF26 AE26 CPUPWRGD/GPIO49 HDA_BIT_CLK HDA_SYNC AG3 AG4 AJ4 AJ3 RN66 AF13 AG26 DPRSTP# DPSLP# GLAN_COMPI GLAN_COMPO AJ17 AH17 AH15 AD13 HDA_SDIN0 23 SATA_RXN0_C 23 SATA_RXP0_C 23 SATA_TXN0 23 SATA_TXP0 LDRQ0# LDRQ1#/GPIO23 1D05V_S0 LPC_FRAME# 31,33,34 STPCLK# GLAN_DOCK#/GPIO13 AE14 29 HDA_RST#_CODEC 29 HDA_SDOUT_CODEC LPC_FRAME# 1 C333 SC15P50V2JN-2-GP 29 C4 SRN10KJ-5-GP 2 1 2 1 2 1031 SA 29 HDA_BITCLK_CODEC 29 HDA_SYNC_CODEC FWH4/LFRAME# A20GATE A20M# LAN_RXD0 LAN_RXD1 LAN_RXD2 4 C 4 3 LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LAN_RSTSYNC D21 E20 C20 X2 X-32D768KHZ-40GPU E5 F5 G8 F6 GLAN_CLK C21 B21 C22 3 LPC 2 RTCRST# AD22 D22 C329 2 1 2 1 SC1U10V3KX-3GP 2 C624 ICH_RTCX2 1 2 R198 10MR2J-L-GP AF23 SM_INTRUDER# G69 GAP-OPEN FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3 RTCX1 RTCX2 CPU ICH_RTCX1 AG25 AF24 ICH_RTCRST# 2 20KR2J-L2-GP 1 1 R466 1 KBGA20 KBRST# 31,33,34 D ICH_RTCX1 ICH_RTCX2 IDE 1 R452 RTC D SM_INTRUDER# 2 1MR2J-1-GP LAN/GLAN 1 R461 IHDA 1 R467 IDE_PDIOR# 23 IDE_PDIOW# 23 IDE_PDDACK# 23 INT_IRQ14 23 IDE_PDIORDY 23 IDE_PDDREQ 23 3D3V_S0 IDE_PDIORDY 1 R507 2 4K7R2J-2-GP INT_IRQ14 1 R491 2 8K2R2J-3-GP B ICH8-M-1-GP-U 20.F0736.003 ETY-CON3-1-GP 3D3V_AUX_S5 4 +RTCVCC U25 BATT1.1 1 2 3 2 W=20mils 1 1 R457 A W=20mils 3 W=20mils 1 CH715FPT-GP 1 R202 2 W=20mils 5 1KR2J-1-GP RTC1 2 C625 SC1U10V3ZY-6GP 2 100R2J-2-GP XOR CHAIN ENTRANCE STRAP : RSVD <Core Design> A 3D3V_S0 Wistron Corporation R484 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 1KR2J-1-GP 1 2 HDA_SDOUT_CODEC Title ICH8(2/4) LAN,HD,IDE,LPC DY Size A3 Document Number Rev Pamirs-Discrete Date: Wednesday, December 13, 2006 5 4 3 2 Sheet 1 19 SA of 47
- 20. 5 4 3 3D3V_S0 2 1 3D3V_S5 Place closely pin G5 Place closely pin AG9 RN48 PM_BMBUSY# AG12 BMBUSY#/GPIO0 OCP# AG22 H_STP_PCI# H_STP_CPU# AE20 AG18 STP_PCI# STP_CPU# AH11 CLKRUN# 26,27,28,31 PCIE_WAKE# 24,31,34 INT_SERIRQ AE17 AF12 AC13 WAKE# SERIRQ THRM# AJ20 VRMPWRGD AJ22 TP7 AJ8 AJ9 AH9 AE16 AC19 AG8 AH12 AE11 AG10 AH25 AD16 AG13 AF9 AJ11 AD10 TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 GPIO12 TACH0/GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 QRT_STATE0/GPIO27 QRT_STATE1/GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 ICH_RI# PM_BATLOW#_R XDP_DBRESET# GPIO26 8 7 6 5 7,35 VGATE_PWRGD DY SRN10KJ-6-GP 3,28 31 31 31 RN35 1 2 3 4 SMB_LINK_ALERT# OCP# ECSMI# 8 7 6 5 VRMPWRGD 2 0R2J-2-GP SST_CTL TP71 1 R473 TP97 1 2 0R2J-2-GP R490 ECSMI# CPPE# ECSCI# ECSMI# EC_SWI# 1016 SA DY GPIO17 NEWCARD_RST# GPIO20 TP88 GPIO22 TP94 28 NEWCARD_RST# SRN10KJ-6-GP TP63 TP82 C R483 R471 1 1 3 DPRSLPVR 100KR2J-1-GP ICH_RSVD 1KR2J-1-GP 2 2 CLKSATAREQ# TP95 TP87 TP89 29 DY GPIO1 CPPE#1 ECSCI# CLKSATAREQ# GPIO38 GPIO39 IDE_RESET# SB_SPKR SB_SPKR AD9 MCH_ICH_SYNC# AJ13 7 MCH_ICH_SYNC# ICH_RSVD 32K suspend clock output AJ21 Low--> default 3D3V_S0 AH27 SPKR MCH_SYNC# TP3 CLK_14M_ICH 3 CLK_48M_ICH 3 AE23 PM_PWROK DPRSLPVR/GPIO16 AJ14 DPRSLPVR AE21 BATLOW# 2 R189 10KR2J-3-GP 1 PWRBTN# C2 LAN_RST# AH20 RSMRST# AG27 1 2 R475 0R2J-2-GP EC_RMRST# CK_PWRGD E1 CK_PWRGD_R CLPWROK E3 VGATE_PWRGD AJ25 SLP_M# CL_CLK0 CL_CLK1 F23 AE18 CL_CLK0 CL_CLK1 CL_DATA0 CL_DATA1 F22 AF19 CL_DATA0 CL_DATA1 CL_VREF0 CL_VREF1 D24 AH23 CL_VREF0_ICH CL_VREF1_ICH CL_RST# AJ23 CLGPIO0/GPIO24 CLGPIO1/GPIO10 CLGPIO2/GPIO14 CLGPIO3/GPIO9 AJ27 AJ24 AF22 AG19 SLP_M# SB_PWR_BTN# 31 PLT_RST1# 7,18,26,28,31,33,34,41 1 R509 2 0R2J-2-GP 1 2 R190 100R2J-2-GP CK_PWRGD 10KR2J-3-GP 2 R186 1 SB_RSMRST# 31 CK_PWRGD 3 VGATE_PWRGD 7,35 TP66 CL_CLK0 7 TP74 CL_DATA0 7 TP73 R470 1 CL_RST# 7 GPIO24 GPIO10 GPIO14 GPIO9 C629 TP62 TP68 TP69 TP75 2 R469 TPM_32K_CLK 34 PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2 26 26 PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3 26 26 PCIE_RXN4 PCIE_RXP4 PCIE_TXN4 PCIE_TXP4 28 28 LAN 3D3V_S0 PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1 27 27 New Card B 27 27 2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP C311 1 C312 1 PCIE_C_TXN1 PCIE_C_TXP1 P27 P26 N29 N28 2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP C309 1 C310 1 PCIE_C_TXN2 PCIE_C_TXP2 M27 M26 L29 L28 PERN2 PERP2 PETN2 PETP2 PERN3 PERP3 PETN3 PETP3 DMI0RXN DMI0RXP DMI0TXN DMI0TXP PERN1 PERP1 PETN1 PETP1 4 3 5V_S0 26 26 C325 1 C324 1 PCIE_C_TXN3 PCIE_C_TXP3 2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP C322 1 C323 1 PCIE_C_TXN4 PCIE_C_TXP4 H27 H26 G29 G28 PERN4 PERP4 PETN4 PETP4 F27 F26 E29 E28 PERN5 PERP5 PETN5 PETP5 PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP C23 B23 E22 SPI_CLK SPI_CS0# SPI_CS1# SPI_MOSI SPI_MISO U26 1 SMB_CLK 26,28 SMB_CLK 6 2 SMB_DATA 5 3 4 SMB_DATA 26,28 18 SPI_CS1# USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#8 USB_OC#9 RN47 A 1 2 3 4 8 7 6 5 SRN10KJ-6-GP RN46 USB_OC#0 1 USB_OC#9 2 USB_OC#8 3 USB_OC#7 4 3D3V_S5 RN38 8 7 6 5 SRN10KJ-6-GP 8 7 6 5 1 2 3 4 SMB_LINK_ALERT# SMLINK0 SMLINK1 PCIE_WAKE# AJ19 AG16 AG15 AE15 AF15 AG17 AD12 AJ18 AD14 AH18 OC0# OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31 OC8# OC9# 1 USB_OC#5 1 2 R477 2 R476 DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 DMI1RXN DMI1RXP DMI1TXN DMI1TXP Y27 Y26 W29 W28 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 7 7 7 7 DMI2RXN DMI2RXP DMI2TXN DMI2TXP AB26 AB25 AA29 AA28 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 7 7 7 7 DMI3RXN DMI3RXP DMI3TXN DMI3TXP AD27 AD26 AC29 AC28 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3 7 7 7 7 T26 T25 CLK_PCIE_ICH# CLK_PCIE_ICH DMI_ZCOMP DMI_IRCOMP Y23 Y24 DMI_IRCOMP USB USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P G3 G2 H5 H4 H2 H1 J3 J2 K5 K4 K2 K1 L3 L2 M5 M4 M2 M1 N3 N2 F2 F3 USBRBIAS CLK_PCIE_ICH# 3 CLK_PCIE_ICH 3 Within 500 mils 1 R462 2 24D9R2F-L-GP USB_PN0 USB_PP0 USB_PN1 USB_PP1 USB_PN2 USB_PP2 USB_PN3 USB_PP3 USB_PN4 USB_PP4 USB_PN5 USB_PP5 USB_PN6 USB_PP6 USB20_N7 USB20_P7 USB20_N8 USB20_P8 TP98 TP99 USB20_N8 USB20_P8 USB20_N9 USB20_P9 1 R244 B 23 23 28 28 23 23 23 23 32 32 32 32 26 26 17 17 17 17 1D5V_S0 3D3V_S0 USB1 New Card USB2 USB3 CAMERA BT 35 MINICARD 1 DOCK R472 330R2J-3-GP DY 2 CK_PWRGD 2 VRMPWRGD Q13 2N7002-11-GP CLK_EN# G A Wistron Corporation 2 22D6R2F-L1-GP Within 500 mils R233 1 0R2J-2-GP R474 1 0R2J-2-GP <Core Design> 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title ICH8(3/4) PM,USB,GPIO 10KR2F-2-GP Size Custom 10KR2F-2-GP Date: 5 1 7 7 7 7 SRN10KJ-6-GP ICH8-M-1-GP-U USB_OC#3 DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 USBRBIAS# USBRBIAS ICH_SMBCLK 3,13,14 2N7002DW-1-GP USB_OC#4 USB_OC#2 USB_OC#1 USB_OC#6 V27 V26 U29 U28 DMI_CLKN DMI_CLKP SPI 1 2 Mini Card 2 2 SCD1U16V2KX-3GP 2 SCD1U16V2KX-3GP D23 F21 26 26 K27 K26 J29 J28 D27 D26 C29 C28 Mini Card 1 RN29 SRN2K2J-1-GP 3,13,14 ICH_SMBDATA 2 U32B 2 OF 6 28 28 2 DY 1 2 10R2J-2-GP R468 453R2F-1-GP D 1 R594 3D3V_S0 S 32KHZ 7 TSLCX08MTCX-GP 2 3K24R2F-GP G792_CLK 22 5 Direct Media Interface 2 10R2J-2-GP SCD1U16V2KX-3GP 2 1 14 1 R593 10KR2J-3-GP SB_SPKR 1 2 R485 DY PCI-Express 1 2 3D3V_S0 32KHZ C R463 453R2F-1-GP ICH8-M-1-GP-U C633 6 3D3V_S0 3K24R2F-GP 1 4 1 2 PM_BATLOW#_R PM_PWROK 7,22 DPRSLPVR 7,35 3D3V_S5 ICH_SUSCLK DY D High--> No boot R595 10KR2J-3-GP U70B C671 SC4D7P50V2CN-1GP GPIO26 PWROK SYSGPIO INT_SERIRQ THERM_SCI# RN31 1 2 3 4 DY PM_SLP_S3# 22,28,31,34,37,38,40 PM_SLP_S4# 17,28,31,36,37,38 S4_STATE#/GPIO26 GPIO H_STP_PCI# H_STP_CPU# MISC 1 2 OCP# SRN10KJ-6-GP DY C371 SC4D7P50V2CN-1GP ICH_SUSCLK AG23 AF21 AD18 SMBALERT#/GPIO11 DY 10KR2J-3-GP 3 3 D3 SLP_S3# SLP_S4# SLP_S5# 7 PM_BMBUSY# 4 2 SUSCLK 1 2 SUS_STAT#/LPCPD# SYS_RESET# 2 F4 AD15 XDP_DBRESET# 24,31,34 PM_CLKRUN# 1 3D3V_S5 GPIO22 34 LPC_PD# 4 XDP_DBRESET# 1 2 3 4 1 RN44 SRN2K2J-1-GP CLK_14M_ICH CLK_48M_ICH CLK14 CLK48 POWER MGT R239 AG9 G5 8 7 6 5 2 4 3 3D3V_S0 GPIO RI# SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36 GPIO37 SATA AF17 ICH_RI# SATA0_R0 SATA0_R1 SATA0_R2 SATA0_R3 AJ12 AJ10 AF11 AG11 SCD1U16V2KX-3GP 2 1 3D3V_S0 D Controller Link R232 SMBCLK SMBDATA LINKALERT# SMLINK0 SMLINK1 SMB 2 AJ26 AD19 AG21 AC17 AE19 CLOCKS SMB_CLK SMB_DATA SMB_LINK_ALERT# SMLINK0 SMLINK1 R493 10R2J-2-GP DY RN50 1 2 1 R245 10R2J-2-GP 3D3V_S0 U32D 4 OF 6 SRN10KJ-6-GP NEWCARD_RST# 10KR2F-2-GP CLK_14M_ICH 1 RN28 SRN2K2J-1-GP 1 CLK_48M_ICH 2 INT_SERIRQ PM_CLKRUN# CLKSATAREQ# THERM_SCI# 8 7 6 5 4 3 1 2 3 4 4 3 2 Document Number Rev Pamirs-Discrete Monday, December 18, 2006 Sheet 1 20 SA of 47
- 21. 5 4 3 2 1 +RTCVCC 20 mils 6 U32F OF 6 C611 1D05V_S0 SC1U10V3ZY-6GP 1D5V_S0_SATAPLL AJ6 1 SCD1U16V2ZY-2GP AC8 AD8 AE8 AF8 3D3V_S0 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 AA3 U7 V7 W1 W6 W7 Y7 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 A8 B15 B18 B4 B9 C15 D13 D5 E10 E7 F11 VCCSATAPLL VCCSUS1_5 AC16 VCCSUS1_5_ICH_1 VCCSUS1_5 J7 VCCSUS1_5_ICH_2 VCC1_5_A VCC1_5_A VCCSUS3_3 C3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 AC18 AG20 AC21 AC22 AH28 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 P6 P7 N7 C1 P1 R1 P2 P3 R3 P4 P5 R5 R6 VCCCL1_05 G22 VCCCL1_5 3D3V_S0 VCCCL3_3 VCCCL3_3 F20 G21 1 2 1 2 SCD1U16V2ZY-2GP 1 2 1 1 K7 L1 L13 L15 L26 L27 L4 L5 M12 M13 M14 M15 M16 M17 M23 M28 M29 M3 N1 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 N4 N5 N6 P12 P13 P14 P15 P16 P17 P23 P28 P29 R11 R12 R13 R14 R15 R16 R17 R18 R28 R4 T12 T13 T14 T15 T16 T17 T2 U12 U13 U14 U15 U16 U17 U23 U26 U27 U3 U5 V13 V15 V28 V29 W2 W26 W27 Y28 Y29 Y4 AB4 AB23 AB5 AB6 AD5 U4 W24 D C 2 2 PCI ATX C616 C635 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP 3D3V_S5 B25 VCCGLAN3_3 2 C637 3D3V_S5 1 VCCGLAN1_5 VCCGLAN1_5 VCCGLAN1_5 VCCGLAN1_5 VCCGLAN1_5 TP93 3D3V_S5 SCD1U16V2ZY-2GP 2 VCCGLANPLL A26 A27 B26 B27 B28 TP79 C677 C599 C665 SCD1U16V2ZY-2GP C674 SC4D7U6D3V3KX-GP VCCPSUS VCCLAN3_3 VCCLAN3_3 VCCPUSB VCCLAN1_05 VCCLAN1_05 TP96 TP72 3D3V_S0 VCCCL1_05_ICH VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF B ICHGND1 A1 R504 A2 A28 A29 ICHGND2 R446 AJ28 AH1 AH29 AJ1 ICHGND3 R503 AJ2 AJ29 ICHGND4 B1 R508 B29 1 DY 2 0R2J-2-GP 1 DY 2 0R2J-2-GP 1 DY 2 0R2J-2-GP 1 DY 2 0R2J-2-GP ICH8-M-1-GP-U TP70 3D3V_S0 C631 A 1 BLM18PG121SN-1GP C317 SC4D7U10V5ZY-3GP 1 2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS <Core Design> ICH8-M-1-GP-U SC1U10V3ZY-6GP 2 SC2D2U10V3KX-GP SC10U6D3V5MX-3GP 2 C618 2 C307 1D5V_S0_GLANPLL L48 1 1D5V_S0 2 2 1 1 BLM18PG121SN-1GP 1 1 L23 VCC1_5_A A24 VCC_LAN1_05_INT_ICH_1 VCC_LAN1_05_INT_ICH_2 F17 G18 F19 G20 TP81 TP76 3D3V_S0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A22 VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A W23 1D5V_S0 1D5V_S0 VCCUSBPLL USB CORE 2 SCD1U16V2ZY-2GP 1 VCC1_5_A VCC1_5_A VCC1_5_A 1 J6 AF20 ARX 1 VCCSUS1_05 VCCSUS1_05 C592 1 1 1 SCD1U16V2ZY-2GP 2 VCC1_5_A VCC1_5_A F1 L6 L7 M6 M7 C666 2 C672 A AD11 D1 1D5V_S0 C678 AC12 VCCSUSHDA AA5 AA6 1D5V_S0 SCD1U16V2ZY-2GP VCCHDA VCC1_5_A VCC1_5_A 2 C668 SC1U10V3ZY-6GP VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A GLAN POWER 2 B SCD1U16V2ZY-2GP 3D3V_S0 AC1 AC2 AC3 AC4 AC5 1D5V_S0 C654 SCD1U16V2ZY-2GP VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A 2 1 1 2 SC10U6D3V5MX-3GP SC1U10V3ZY-6GP (DMI) C667 (SATA) C655 C663 C680 SCD1U16V2ZY-2GP AC10 AC9 C683 3D3V_S0 SC4D7U6D3V3KX-GP 3D3V_S0 AE7 AF7 AG7 AH7 AJ7 1D5V_S0 2 1 2 AD2 VCC3_3 VCC3_3 VCC3_3 VCC3_3 AC7 AD7 C369 2 1 2 VCC3_3 SCD1U16V2ZY-2GP 3D3V_S0 G12 G17 H7 C675 BLM18PG121SN-1GP SCD1U16V2ZY-2GP 1 2 AF29 2 2 VCC3_3 1D05V_S0 C648 1 K L52 1 1D5V_S0 AC23 AC24 1 C676 SCD1U16V2ZY-2GP 2 1 2 20 mils ICH_V5REF_SUS V_CPU_IO V_CPU_IO 2 100R2J-2-GP AE28 AE29 2 D21 CH751H-40PT-1GP C320 SC22U6D3V5MX-2GP R29 VCC_DMI VCC_DMI 1 R247 1D25V_S0 1 A 1 C SCD01U16V2KX-3GP 1D5V_S0 C326 SC10U6D3V5MX-3GP 2 3D3V_S5 C598 2 5V_S5 VCCDMIPLL L22 1 2 IND-1UH-36-GP 1D5V_DMIPLL_S0 1 K ICH_V5REF_RUN C647 SCD1U16V2ZY-2GP 2 1 2 20 mils VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B C664 1 1 2 1 2 1 2 D18 CH751H-40PT-1GP C619 SC2D2U6D3V3MX-1-GP R234 100R2J-2-GP C318 SC10U6D3V5MX-3GP 3D3V_S0 A 1 5V_S0 C321 SC10U6D3V5MX-3GP 1 2 ST220U2VBM-3GP C308 C613 2 AA25 AA26 AA27 AB27 AB28 AB29 D28 D29 E25 E26 E27 F24 F25 G24 H23 H24 J23 J24 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T23 T24 T27 T28 T29 U24 U25 V23 V24 V25 W25 Y25 BLM18PG121SN-1GP CORE 1D5V_A3GP_S0 2 VCCP CORE 1 V5REF_SUS A13 B13 C13 C14 D14 E14 F14 G14 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18 SCD1U16V2ZY-2GP G4 IDE ICH_V5REF_SUS VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 V5REF V5REF 1 T7 A16 VCCA3GP ICH_V5REF_RUN L50 5 OF 6 VCCRTC 2 U32E AD25 D 1D5V_S0 A23 A5 AA2 AA7 A25 AB1 AB24 AC11 AC14 AC25 AC26 AC27 AD17 AD20 AD28 AD29 AD3 AD4 AD6 AE1 AE12 AE2 AE22 AD1 AE25 AE5 AE6 AE9 AF14 AF16 AF18 AF3 AF4 AG5 AG6 AH10 AH13 AH16 AH19 AH2 AF28 AH22 AH24 AH26 AH3 AH4 AH8 AJ5 B11 B14 B17 B2 B20 B22 B8 C24 C26 C27 C6 D12 D15 D18 D2 D4 E21 E24 E4 E9 F15 E23 F28 F29 F7 G1 E2 G10 G13 G19 G23 G25 G26 G27 H25 H28 H29 H3 H6 J1 J25 J26 J27 J4 J5 K23 K28 K29 K3 K6 1 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 1 C622 Wistron Corporation DY 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title ICH8(4/4) POWER&GND Size Custom Document Number Rev Pamirs-Discrete Date: Thursday, October 19, 2006 5 4 3 2 Sheet 1 21 SA of 47
- 22. FAN1_VCC 5V_S0 K 1 D13 C151 SC10U10V5ZY-1GP 1 2 C162 SCD1U16V2ZY-2GP 2 1 *Layout* 15 mil 1N4148W-1-GP A R56 10KR2J-3-GP EAN1 2 5 RN5 3D3V_S0 4 3 G792_SCL G792_SDA 1 2 FAN1_FG1 SRN10KJ-5-GP 3 2 1 1 FAN1_VCC *Layout* 15 mil 2 C145 SC1000P50V3JN-GP 4 ACES-CON3-1-GP 20.F0735.003 5V_S0 2 FAN1 FG1 CLK SDA SCL NC#19 DXP1 DXP2 DXP3 1 VCC DVCC 7 9 11 C163 SCD1U16V2ZY-2GP 1 4 14 16 18 19 DGND DGND 5 17 SGND1 SGND2 SGND3 8 10 12 G792_CLK 20 G792_SDA G792_SCL G792_DXP2 1 2 2 1 1 1 R99 10KR2F-2-GP C154 SC4D7U10V5ZY-3GP 2 C475 SC1U10V3ZY-6GP 6 20 3 5V_G792_S0 2 200R2F-L-GP 15 13 3 2 1 Setting T8 as 100 Degree THRM# HW_THRM_SHDN# V_DEGREE ALERT# THERM# THERM_SET RESET# GTHERMDA 42 1 Q5 PMBS3904-1-GP 1 G792SFUF-GP 3D3V_S5 2 2 V_DEGREE =(((Degree-72)*0.02)+0.34)*VCC G792_DXN2 3 R100 100KR2F-L1-GP Q6 PMBS3904-1-GP 1 C200 SC2200P50V2KX-2GP 2 31R505 THRM# EC_RST# 1 2 0R2J-2-GP 2 R83 1 U17 *Layout* 30 mil C199 SC2200P50V2KX-2GP 2 5V_S0 1 7 SSLVC08APWR-GP R309 DXP1:108 Degree DXP2:H/W Setting DXP3:88 Degree G21 H_THERMDA 4 1 G20 GAP-CLOSE GAP-CLOSE C180 SC2200P50V2KX-2GP H_THERMDC 4 1 G792_RST# 2 PM_SLP_S3# 20,28,31,34,37,38,40 13 1 12 11 7,20 PM_PWROK 2 2 14 GTHERMDC 42 U43D 2 100KR2J-1-GP Place near chip as close as possible KBC_3D3V_AUX R510 100KR2J-1-GP 1N4148W-1-GP U63 5 5 1 1 2 GND G792_SCL EC_RST# 3 EC_RST# 31 1 KBC_SDA1 31,32 2 6 VCC A B 3 34,36 PWR_S5_EN# 4 Y S5_ENABLE 31 C682 SC1U10V3ZY-6GP 2 4 2 3D3V_S0 U51 G792_SDA A 3D3V_S0 31,32 KBC_SCL1 1 D37 K 5V_AUX_S5 74AHCT1G00DCKR-GP 2N7002DW-1-GP <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Thermal/Fan Controllor G792 Size Custom Document Number Date: Monday, October 23, 2006 Rev Pamirs-Discrete Sheet 22 of SA 47
- 23. IDE_PDD[0..15] SATA HD Connector CD-ROM CONNECTOR 3D3V_S0 CDROM_LED# 1 R518 INT_IRQ14 2 8K2R2J-3-GP 1 51 C681 1 4 2SATA_RXN0 5 SATA_RXP0 1 6 SC3900P50V2KX-2GP 7 SC3900P50V2KX-2GP SATA_RXP0_C 19 2 C679 8 9 10 11 12 100 mil 19 IDE_PDDREQ 19 IDE_PDIOR# 13 14 5V_S3 15 5V_USB1_S3 17 18 19 IDE_PDA2 19 IDE_PDCS3# 1 19 20 21 22 1 C684 SC10U10V5ZY-1GP SYN-CONN22A-GP-U2 1 5V_S0 24 20.F0817.022 CD_AUDL 29 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 2 C462 SCD1U16V2ZY-2GP 1 FUSE-2A8V-3GP 2 2 19 IDE_PDDACK# 16 100 mil 2 F2 1 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 IDE_PDA2 34 36 38 40 42 44 DY 46 C685 C686 48 50 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP NP2 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15 CD_AGND 29 RSTDRV#_5 IDE_PDD7 IDE_PDD6 IDE_PDD5 IDE_PDD4 IDE_PDD3 IDE_PDD2 IDE_PDD1 IDE_PDD0 3D3V_S0 1 SATA_TXP0 19 R270 4K7R2J-2-GP 2 2 19 SATA_RXN0_C NP1 2 29 CD_AUDR 3 19 SATA_TXN0 1 R267 CDROM1 HDD1 23 1 1 2 4K7R2J-2-GP 3D3V_S0 C355 SCD1U16V2ZY-2GP 2 C656 SC10U10V5ZY-1GP 2 SCD1U16V2ZY-2GP 2 1 C669 2 C657 SC10U10V5ZY-1GP 5V_S0 1 1 5V_S0 19 IDE_PDIOW# 19 IDE_PDIORDY 19 INT_IRQ14 19 IDE_PDA1 19 IDE_PDA0 19 IDE_PDA1 IDE_PDA0 IDE_PDCS1# 19 CDROM_LED# 16 5V_S0 primary channel:low 52 TYCO-CONN50-4R-GP-U 20.80353.050 USB PORT 3 HDMI_1_TXC 13 2 2 C570 2 C572 3D3V_S0 TC21 SE100U16VM-L1-GP 3 2 D14 2 HDMI_1_TXC# HDMI_TXC# HDMI_HDP 3 DY BAV99PT-GP-U SKT2 20 4 1 5V_USB1_S3 1 HDMI_1_TXD1 HDMI_TXD1 TSAHCT08PWR-1GP 1 1 1 7 PCI_PLTRST# SCD1U16V2ZY-2GP SC1000P50V3JN-GP 43 43 2 FUSE-1D1A6V-8GP HDMI_1_TXD2# HDMI_TXD2# 18 100 mil 4 1 43 1 RSTDRV#_5 11 5V_USB2_S3 F3 L57 ACM2012H-900-GP ACM2012H-900-GP L56 U68D 12 5V_S3 4 HDMI_TXC 1 43 5V_S0 14 HDMI_1_TXD2 HDMI_TXD2 2 43 L54 ACM2012H-900-GP 1 USB_PN0 R181 2 0R0402-PAD USB_1- USB1 22 12 10 9 8 7 6 5 4 3 2 20 43 HDMI_1_TXD2# HDMI_1_TXD1 3 2 HDMI_1_TXD2 HDMI_1_TXD1# HDMI_TXD1# HDMI_1_TXD1# HDMI_1_TXD0 HDMI_1_TXD0# HDMI_1_TXC 42 HDMI_1_TXD0 42 42 TP60 HDMI_SCL HDMI_SDA 5V_S0 HDMI_1_TXC# 1 2 R364 0R2J-2-GP HDMI_SCL HDMI_SDA HDP 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 4A 3A 1 USB_PP0 2 150R2J-L1-GP-U 1 B NUMLK_LED C R1 R2 PDTC124EU-1-GP USB_1- R85 1A 42 11 NUMLK_LED# ACES-CON10-5-GP E HDMI_HDP HDMI_HDP 1 2 L16 1 2 BLM15AG221SN-GP 20.F0735.010 HDP <Core Design> 10KR3F-L-GP R71 100KR3J-L-GP Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 1 SKT-HDMI23P-GP 4 1 R367 Q22 23 1 USB_1+ 5V_USB2_S3 ACM2012H-900-GP L55 HDMI_TXD0# 2 0R0402-PAD USB_1+ 21 43 R180 31 2A USB_PN3 USB_PP3 USB_PN2 USB_PP2 5V_S3 20 2 3 HDMI_TXD0 2 43 HDMI_CEC 20 20 20 20 1 Title HD/CDROM/USB HDMI_1_TXD0# Size A3 Document Number Date: Tuesday, December 12, 2006 Rev Pamirs-Discrete Sheet 23 of SA 47
- 24. 4 3 3D3V_S0 1 PCI_AD25 18 18 2 C723 SCD1U16V2ZY-2GP GBRST# 18,27 PCIRST1# PCLK_PCM 18 ICH_PME# 2 20,31,34 PM_CLKRUN# R584 1 R554 2 2 1 DY 0R2J-2-GP 0R0402-PAD 1 SHIELD GND R553 10KR2J-3-GP AGND1 AGND2 AGND3 AGND4 AGND5 99 102 103 107 111 PCICLK 70 117 R579 4K7R2J-2-GP HWSPND# 69 MSEN 58 XDEN 55 UDIO5 57 UDIO3 UDIO4 8 7 6 5 60 72 DY EC87 SCD1U16V2ZY-2GP 56 UDIO0/SRIRQ# 1 2 3 4 2 3D3V_S0 100KR2J-1-GP 65 59 UDIO2 1 R589 1 RN75 UDIO1 PME# 3D3V_S0 SRN10KJ-6-GP INT_SERIRQ B 20,31,34 INTA# 115 PCI_PIRQA# 18 INTB# 116 PCI_PIRQC# 18 1394 : INTA# 4in1 : INTB# TEST 66 CLKRUN# R555 R585 100KR2J-1-GP A 2 1 2 1 GBRST# PCIRST# C 3D3V_S0 1 71 119 4 13 22 28 54 62 63 68 118 122 1KR2J-1-GP DY R5C833-GP DY 1 REQ# GNT# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 2 124 123 23 24 25 26 29 30 31 PCI_C/BE#3 PCI_C/BE#3 PCI_C/BE#2 PCI_C/BE#2 PCI_C/BE#1 PCI_C/BE#1 PCI_C/BE#0 PCI_C/BE#0 1 2 R5C834_IDSEL R562 10R2J-2-GP PCI_REQ#0 PCI_GNT#0 18 PCI_FRAME# 18 PCI_IRDY# 18 PCI_TRDY# 18 PCI_DEVSEL# 18 PCI_STOP# 18 PCI_PERR# 18,31 PCI_SERR# 1 2 R571 10KR2J-3-GP 18 18 18 18 86 2 PCI_PAR AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 PAR C/BE3# C/BE2# C/BE1# C/BE0# IDSEL 121 18 125 126 127 1 2 3 5 6 9 11 12 14 15 17 18 19 36 37 38 39 40 42 43 44 46 47 48 49 50 51 52 53 33 7 21 35 45 8 C746 SC10U10V5ZY-1GP 2 PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 18 PCI_AD[0..31] 3 VCC_ROUT1 VCC_ROUT2 VCC_ROUT3 VCC_ROUT4 VCC_ROUT5 VCC_MD C B VCC_RIN 16 34 64 114 120 D C714 2 61 VCC_3V PCI / OTHER 1 C747 VCC_PCI1 VCC_PCI2 VCC_PCI3 VCC_PCI4 VCC_PCI5 VCC_PCI6 67 SCD01U16V2KX-3GP 10 20 27 32 41 128 1 2 SCD01U16V2KX-3GP 1 SCD01U16V2KX-3GP C743 SCD01U16V2KX-3GP SCD47U16V3ZY-3GP C744 2 C707 SCD47U16V3ZY-3GP 1 2 2 C717 SCD1U16V2ZY-2GP SCD01U16V2KX-3GP 2 1 1 C705 2 C742 VCC_ROUT 2 C710 SC10U10V5ZY-1GP DY C715 1 1 3D3V_S0 SCD01U16V2KX-3GP 2 1 2 C728 SCD01U16V2KX-3GP 2 1 SCD01U16V2KX-3GP 2 1 1 1 C730 SC10U10V5ZY-1GP 2 D 3D3V_S0 IC1B C734 1 1 3D3V_S0 2 2 5 C706 SC10P50V2JN-4GP <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title R5C832/PCI Size A3 Document Number Rev Pamirs-Discrete Date: Wednesday, December 06, 2006 Sheet 24 of SA 47
- 25. A B C D E IC1A 3D3V_PHY 3D3V_S0 C709 C708 SCD01U16V2KX-3GP 1 96 RICHO_FILO 2 SCD01U16V2KX-3GP 1 C711 1 R550 2RICHO_REXT 10KR2F-2-GP TPBP0 FIL0 101 REXT 105 TPB0P TPAN0 108 TPA0N TPAP0 XO 109 TPA0P 5 6 7 8 VG#5 VG#6 VG#7 VG#8 TPA TPA* TPB TPB* RICHO_VREF 2 SCD01U16V2KX-3GP 100 1 1 CLOSE TO CHIP R556 R557 SCD01U16V2KX-3GP 4 3 2 1 1 TPB0+ 1 SKT-1394-4P-13GP 22.10218.J61 R222 2 0R0402-PAD R226 SCD33U10V3KX-3GP 1 R559 R230 2 1 R558 4 DY 2 1 DLW21HN900SQ2LGP TPB0- TPBIAS0 TPA0P TPA0N TPB0P TPB0N 2 0R0402-PAD L28 3 1 1 C704 C702 C700 2 95 1394 2 TPBN0 SC12P50V2JN-3GP 1394_XO IEEE1394/SD 2 TPB0N 4 DY 2 1 DLW21HN900SQ2LGP TPA0- 2 C712 1 L25 3 TPA0+ 1 SCD1U16V2ZY-2GP XI 104 4 2 0R0402-PAD 1 94 X-24D576MHZ-57GP X7 R220 2 C699 SC10U10V5ZY-1GP 2 TPBIAS0 1 113 SC12P50V2JN-3GP 1394_XI 2 2 2 C713 1 Reserve R547,R548,R550,R551 for co-layout 1 4 1 GUARD GND 2 MLB-160808-18-GP 1 TPBIAS0 1031 SA 3D3V_PHY 1 L53 2 AVCC_PHY1 AVCC_PHY2 AVCC_PHY3 AVCC_PHY4 98 106 110 112 2 1 2 R549 5K11R2F-L1-GP 1394_TPB1_R 1 2 C701 SC270P50V2JN-2GP 2 0R0402-PAD VREF GUARD GND MDIO17 C662 90 SD/XD/MS_DATA3 93 SD/XD/MS_DATA2 MDIO11 81 SD/XD/MS_DATA1 MDIO10 82 SD/XD/MS_DATA0 MDIO05 SRN47J-5-GP 3D3V_CARD 75 XD_WP# 88 SD/XD/MS_CMD MDIO02 78 SD_WP#(XDR/B#) 80 MDIO01 79 MDIO09 84 MDIO04 76 MDIO06 74 MDIO07 XD_ALE_1 XD_CLE_1 SRN33J-5-GP-U XD_CE#_1 3 4SD/XD/MS_CMD_1 73 97 MC_PWR_CTRL_0 MS_LED# RSV 2 26 30 34 37 MS_BS MS_SDIO MS_INS MS_SCLK SD/XD/MS_DATA3_1 SD/XD/MS_DATA2_1 SD_IO 35 32 29 MS_RESERVED#MS_7 MS_RESERVED#MS_5 SD_I/O NP1 NP2 NP3 NP4 NP5 NP6 2 D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 14 15 16 17 18 SD/XD/MS_DATA0_1 SD/XD/MS_DATA1_1 SD/XD/MS_DATA2_1 SD/XD/MS_DATA3_1 XD_DATA4_1 XD_DATA5_1 XD_DATA6_1 XD_DATA7_1 51 50 SD_CD# SD_3P SD_6P SD_7P SD_8P 49 48 47 46 6 MC_PWR_CTRL_1 1 XD_SW# NP1 NP2 NP3 NP4 NP5 NP6 MS_VSS 33 24 GND GND GND GND GND GND GND GND SD/XD/MS_DATA0_1 SD/XD/MS_DATA1_1 25 SD_VSS SD_VSS 2 1 20 40 10 43 52 53 54 SKT-MEMO-15-GP-U4 3D3V_S0 20.I0030.001 1 2 2 2 R529 AAT4610AIGV-GP 15KR2J-1-GP SC1U10V3ZY-6GP For SD Card Power SCD1U16V2ZY-2GP R546 10KR2J-3-GP R565 100KR2J-1-GP U66 2N7002DW-1-GP 1 <Core Design> 2 4 4 ON# C692 1 2 5 1 IN 5 1 OUT GND SET 2 10KR2J-3-GP 3D3V_S0 U65 1 1 C693 1 SD_WP1 SD_WP2 SD/XD/MS_CMD_1 SD/XD/MS_DATA0_1 MS_INS# SD/XD/MS_CLK_1 33R2J-2-GP R563 100KR2J-1-GP 1 1 2 3 2 45 44 TPAD28 20mil SD_WP#(XDR/B#) SD/XD/MS_CLK_1 XD_CE#_1 XD_CLE_1 SD/XD/MS_CMD_1 XD_WP# SD_CD_DETECT SD_WP_PROTECT SD/XD/MS_CLK_1 TP86 3D3V_CARD 2 42 21 R564 1 MS_LED# 16 R5C833-GP D38 MS_INS# 1 6 2 5 XD/MS_CD# 4 SD_CD# 3 1 Wistron Corporation 2 R544 XD_SW# XD_ALE_1 3 4 5 6 8 9 SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3 SD_WP#(XDR/B#) SD/XD/MS_CLK 23 22 41 39 SD_CD# SD_WP#(XDR/B#) XD/MS_CD# 1 SRN33J-5-GP-U 2 7 SD_CMD SD_CLK SD/XD/MS_DATA0_1 SD/XD/MS_DATA1_1 SD/XD/MS_DATA2_1 SD/XD/MS_DATA3_1 RN77 XD_CE# 2 SD/XD/MS_CMD 1 36 27 CD ALE SD_CD# SD/XD/MS_CMD_1 SD/XD/MS_CLK_1 RN76 3 4 VCC XD_CE# 77 MDIO00 2 1 1 1 2 XD_CLE MS_VCC MS_VCC R/B# RE# CE# CLE WE# WP# SD_CO2 SD_CO1 XD_ALE 85 C661 SC2D2U10V3ZY-1GP SD_VCC 28 38 19 83 MDIO03 XD_ALE XD_CLE SCD1U16V2ZY-2GP CARD2 SRN47J-5-GP 2 C660 SCD1U16V2ZY-2GP SD/XD/MS_DATA1_1 MDIO18 1SD/XD/MS_DATA0_1 2SD/XD/MS_DATA1_1 3SD/XD/MS_DATA2_1 4SD/XD/MS_DATA3_1 DY C698 31 MDIO19 RN72 SD/XD/MS_DATA08 SD/XD/MS_DATA17 SD/XD/MS_DATA26 SD/XD/MS_DATA35 1 3 SCD1U16V2ZY-2GP 2 1 2 3 4 DY XD_DATA4 MDIO08 8 7 6 5 XD_DATA5 91 MDIO12 XD_DATA4_1 XD_DATA5_1 XD_DATA6_1 XD_DATA7_1 89 MDIO14 RN74 XD_DATA6 MDIO13 XD_DATA4 XD_DATA5 XD_DATA6 XD_DATA7 XD_DATA7 92 MDIO15 1031 SA 87 MDIO16 3 XD_SW#_13 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title R5C832/IEEE1394/SD RB731U-2-GP Size Custom MC_PWR_CTRL_0 Document Number Rev Pamirs-Discrete Date: Friday, December 15, 2006 A B C D Sheet E 25 of SA 47
- 26. A B C D E Mini Card Connector 2 Mini Card Connector 1 Wireless card WWAN 3D3V_S0 3D3V_MINI1_S0 3D3V_S0 3D3V_MINI_S0 L37 1D5V_S0 1 1.5V 2 3.3V REFCLK+ REFCLKPERN0 PERP0 PETN0 PETP0 USB_DUSB_D+ SMB_CLK SMB_DATA 3 5 8 10 12 14 16 17 19 20 37 39 41 43 45 47 49 51 5V_AUX_S5 TPAD30 TP84 33 1 WLANONLED 1 4 9 15 18 21 26 27 29 34 35 40 50 53 54 LED_WWAN# LED_WLAN# LED_WPAN# CLK_PCIE_MINI1 3 CLK_PCIE_MINI1# 3 1 2 R223 0R2J-2-GP 1 DY 2 R129 0R2J-2-GP PCIE_TXN3 20 PCIE_TXP3 20 SMB_CLK 20,28 SMB_DATA 20,28 1 2 DUMMY-R2 TP61 TPAD30 PCIE_WAKE# 20,27,28,31 28 28 28 28 28 UIM_PWR UIM_DATA UIM_CLK UIM_RST UIM_VPP +3.3V 31 M_WXMIT_OFF# 3D3V_MINI1_S0 DY EC16 SCD1U16V2ZY-2GP WLANONLED RESERVED#3 RESERVED#5 RESERVED#8 RESERVED#10 RESERVED#12 RESERVED#14 RESERVED#16 RESERVED#17 RESERVED#19 RESERVED#20 RESERVED#37 RESERVED#39 RESERVED#41 RESERVED#43 RESERVED#45 RESERVED#47 RESERVED#49 RESERVED#51 LED_WWAN# LED_WLAN# LED_WPAN# 31 33 USB_DUSB_D+ +3.3VAUX 3 5 8 10 12 14 16 17 19 20 37 39 41 43 45 47 49 51 62.10043.341 NP1 NP2 62.10043.341 23 25 PETN0 PETP0 42 44 46 PLT_RST1# 7,18,20,28,31,33,34,41 3D3V_S0 +1.5V +1.5V 3D3V_MINI1_S0_1 24 WL_PRIORITY1 BT_PRIORITY1 UIM_PWR UIM_DATA UIM_CLK UIM_RST UIM_VPP PERN0 PERP0 3.3V 52 3D3V_MINI1_S0 PCIE_RXN3 20 PCIE_RXP3 20 R438 1 2 28 48 3D3V_S5 REFCLK+ REFCLK- NP1 NP2 TPAD30 TP83 1 7 22 GND GND GND GND GND GND GND GND GND GND GND GND GND GND RESERVED#3 RESERVED#5 RESERVED#8 RESERVED#10 RESERVED#12 RESERVED#14 RESERVED#16 RESERVED#17 RESERVED#19 RESERVED#20 RESERVED#37 RESERVED#39 RESERVED#41 RESERVED#43 RESERVED#45 RESERVED#47 RESERVED#49 RESERVED#51 42 44 46 3D3V_MINI_S0 3 30 32 WAKE# CLKREQ# PERST# +3.3VAUX DUMMY-R2 31 E51_RXD 31 E51_TXD WIFI_RF_EN 36 38 +3.3V 24 31 31 33 +1.5V +1.5V 52 2WL_PRIORITY1 2BT_PRIORITY1 13 11 23 25 1.5V 13 11 1218 MINI2 1 MINI2# 1 R602 R605 RXN4_1 1 RXP4_1 1 R606 R609 TXN4_1 1 TXP4_1 1 R610 4 DY DY 0R2J-2-GP 2 0R2J-2-GP 2 DY DY 0R2J-2-GP 2 0R2J-2-GP 2 DY DY 0R2J-2-GP 2 0R2J-2-GP 2 36 38 SMB_CLK SMB_DATA 30 32 WAKE# CLKREQ# PERST# 1 7 22 GND GND GND GND GND GND GND GND GND GND GND GND GND GND 4 9 15 18 21 26 27 29 34 35 40 50 53 54 1 R405 PCIE_RXN4 20 PCIE_RXP4 20 PCIE_TXN4 20 PCIE_TXP4 20 USB_PN6 20 USB_PP6 20 DY R607 SMB_CLK_1 1 SMB_DATA_1 1 R608 DY CLK_PCIE_MINI2 3 CLK_PCIE_MINI2# 3 0R2J-2-GP SMB_CLK 2 0R2J-2-GP SMB_DATA 2 2 PLT_RST1# 0R2J-2-GP DY 3 NP1 NP2 6 28 48 1 R437 1 R436 DUMMY-R2 6 MLB201209-0600P-GP MLB201209-0600P-GP 3D3V_S5 32 WL_PRIORITY 32 BT_PRIORITY R601 1 1 2 MINI1 2 MINI2 NP1 NP2 L51 2 4 SKT-MINI52P-7-GP SKT-MINI52P-7-GP 1 1 2 2 2 C229 SCD1U16V2ZY-2GP 2 1 2 C652 2 C651 2 C653 SC10U10V5ZY-1GP 1 1 C473 SC10U10V5ZY-1GP 1 3D3V_S5 2 1D5V_S0 2 3D3V_MINI_S0 1 SCD01U16V2KX-3GP C60 2 1 3D3V_MINI1_S0 C649 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SC10U10V5ZY-1GP C650 SCD1U16V2ZY-2GP <Core Design> 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title MINI CARD CONN . Size A3 Document Number Rev Pamirs-Discrete Date: Tuesday, December 19, 2006 A B C D Sheet E 26 SA of 47
- 27. A B DY 2D5V_LAN_S5 1 2 R480 0R2J-2-GP 1 2 3D3V_S0 R479 0R2J-2-GP 3D3V_LAN_S5 C D E 3D3V_LAN_S5 1D2V_LAN_S5 LANPWR R199 DY 1 2 10MR2J-L-GP 33 39 44 48 58 2 7 13 VDD VDD VDD VDD VDD VDD VDD VDD 1 1 50 49 PCIE_RXN PCIE_RXP 53 54 PCIE_WAKE# 20,26,28,31 PCIRST1# 18,24 CLK_PCIE_LAN 3 CLK_PCIE_LAN# 3 LAN_RXN1 C659 1 LAN_RXP1 C658 1 C330 SC27P50V2JN-2-GP C334 SC27P50V2JN-2-GP 3D3V_LAN_S5 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP 2 PCIE_RXN2 PCIE_RXP2 3D3V_LAN_S5 20 20 1 1 NC#36 NC#37 6 5 55 56 28 28 LOM_DISABLE# MDI0MDI1- 1 28 28 R647 DUMMY-R2 MDI0+ MDI1+ R482 4K7R2J-2-GP DY R481 4K7R2J-2-GP 0R2J-2-GP ACT_LED# EEWP VPD_CLK VPD_DATA R219 EEWP R229 0R2J-2-GP 2 3 GND Pull up for AT24C08 another pull low MDI0+ 65 MDI03D3V_LAN_S5 MDI1+ MDI1- R478 TPAD30 VPD_CLK VPD_DATA MDI0+ MDI1+ 8 7 6 5 AT24C08AN-1-GP PU_VDDO_TTL#42 PU_VDDO_TTL#43 1 VCC WP SCL SDA LANX1 LANX2 TP27 MDI0MDI1- 28 A0 A1 A2 GND 2 15 14 1 2 3 4 LAN100M_LED# 28 1 63 62 60 59 XTALI XTALO 42 43 18 21 27 31 88E8039-A0-GP TSTPT TESTMODE HSDACP HSDACN Marvell recommend: 2K Ohm 20 20 2 2 LED_LINK# NC#62 LED_SPEED# LED_ACT# 29 46 24 25 PCIE_TXN2 PCIE_TXP2 U31 RXN TXN NC#27 NC#31 3 1LANHP 1LANHN LOM_DISABLE# VAUX_AVLBL SWITCH_VCC VMAIN_AVLBL SWITCH_VAUX RSET CTRL12 CTRL25 VPD_DATA VPD_CLK TPAD30 TP25 TPAD30 TP26 10 12 11 47 9 16 3 4 41 38 1025 1LANSC LANPWR 1LANSV SA TPAD30 TP23 LANRSET 2 1 CTRL12 R209 CTRL25 1K91R2F-1-GP RXP TXP NC#26 NC#30 TPAD30 TP24 17 20 26 30 3D3V_LAN_S5 LOM_DISABLE# 1 64 23 1 8 40 45 61 WAKE# PERST# REFCLKP REFCLKN PCIE_TXN PCIE_TXP 2 1 4K7R2J-2-GP R444 2 LANX1 XTAL-25MHZ-74GP Y41.-1 NC#34 NC#35 36 37 LANX2 1 2 34 35 4 X3 2 3D3V_LAN_S5 VDD25 AVDD AVDDL AVDDL AVDDL AVDDL AVDDL AVDDL AVDDL U30 VDDO_TTL VDDO_TTL VDDO_TTL VDDO_TTL VDDO_TTL 57 52 51 32 28 22 19 4 1 1 R455 1 R458 1 R460 1 R464 MDIS0_LAN 1 2 C610 49D9R2F-GP SCD01U16V2KX-3GP 49D9R2F-GP 2 MDIS1_LAN 1 2 C627 49D9R2F-GP SCD01U16V2KX-3GP 2 49D9R2F-GP 2 2 2 4K7R2J-2-GP 2 2N7002DW-7F-GP PM_LAN_ENABLE 6 1 PM_SLP_S3# 5 2 28 PM_SLP_S3# 3D3V_LAN_S5 2D5V_LAN_S5 1 4 1D2V_LAN_S5 PM_LAN_ENABLE# 3 3D3V_S5 1 3D3V_S5 2 U46 2 9 1 8 AC_IN# AC_IN# 1 C617 1 C607 1 C608 1 C628 1 C636 1 1 1 C634 1 C638 PM_LAN_ENABLE# 10 2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP 2 C623 SC1000P50V2JN-GP 2 C632 SC1000P50V2JN-GP 2 SC1U10V2KX-GP 2 SC1U10V2KX-GP 1 C609 1 C642 1 1 1 1 1 C646 1 SSLVC08APWR-GP 7 28 DY U43C 14 R268 10KR2J-3-GP 2 C641 SC1000P50V2JN-GP 2 C643 SC1000P50V2JN-GP 2 SC1U10V2KX-GP 2 SC1U10V2KX-GP 2 SC1U10V2KX-GP 2 SC1U10V2KX-GP 2 SC1U10V2KX-GP 2 C645 SC1000P50V2JN-GP 2 C606 SC1000P50V2JN-GP 2 C644 SC1U10V2KX-GP 2 C605 SC1000P50V2JN-GP 2 SC1U10V2KX-GP 2 C626 SC1000P50V2JN-GP 2 R645 3D3V_LAN_S5_1 2 3 2 CTRL12 1 1 2 2 SCD1U10V2KX-4GP 2 8053:2.5V. 8055:1.8V. C640 C351 SCD1U10V2KX-4GP SC10U10V5KX-2GP 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title LAN MARVELL Size A3 Document Number Rev Pamirs-Discrete Date: Monday, December 18, 2006 12/4 A <Core Design> 2 C615 1 S SC10U10V5KX-2GP 1 SCD1U10V2KX-4GP Q12 2SB772PT-1-GP 1D2V_LAN_S5 2D5V_LAN_S5 C583 C343 2 1 1 3 Q30 2SB772PT-1-GP 1 C345 R206 4K7R2J-2-GP 2 CTRL25 3D3V_LAN_S5_2 1 2 MLB-201209-8-GP SC4D7U6D3V3KX-GP 1 3D3V_LAN_S5 R430 4K7R2J-2-GP 2 8053:CTRL25. 8055:CTRL18. PLACE PNP TO CHIP ACAP CTRL12 PIN TRACE IS 25MIL L24 1 DY 3D3V_LAN_S5 C347 1 2 G 1 SCD1U10V2KX-4GP 2 1 1 G 2 D Q36 2N7002EPT-GP PM_LAN_ENABLE C604 0R5J-6-GP C306 SC22U6D3V5MX-2GP 1 SC22U6D3V5MX-2GP 2 1 SCD1U10V2KX-4GP 2 1 R643 10KR2J-3-GP DY 2 D G 1 C476 1 D C477 S PLACE PNP TO CHIP ACAP CTRL25 PIN TRACE IS 25MIL 3D3V_LAN_S5 R644 2 Q35 AO3403-GP 3D3V_S5 2 2 DY 0R3-0-U-GP SC4D7U6D3V3KX-GP 1 B C D Sheet E 27 SA of 47
- 28. A B 1 MDI1+ 1.route on bottom as differential pairs. 2.Tx+/Tx- are pairs. Rx+/Rx- are pairs. 3.No vias, No 90 degree bends. 4.pairs must be equal lengths. 5.6mil trace width,12mil separation. 6.36mil between pairs and any other trace. 7.Must not cross ground moat,except RJ-45 moat. RJ45-3 16 1 R404 0R2J-2-GP 1 4 XRF_RDC E PIN09 : GREEN PIN11 : ORANGE PIN13 : YELLOW XF1 27 R397 0R2J-2-GP D 10/100M Lan Transformer 2 2 2D5V_LAN_S5 C 27 2 3 27 MDI0+ 15 14 10 R411 27 LAN100M_LED# 3D3V_LAN_S5 17 RJ45-1 RJ45-6 RJ45-7 RJ45-2 RJ45-3 RJ45-4 R415 2 1 470R2J-2-GP 3D3V_LAN_S5 27 RJ45-4 8 6 4 5 MDI0- 1 C526 2 2 3 DY XFORM-257-GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP C505 14 RJ45-13P-105GP-U2 22.10177.871 RN15 SRN75J-1-GP 5 6 7 8 1 DY 13 ACT_LED# RJ45-2 XFR_CMT 9 11 12 13 4 4 3 2 1 27 15 9 10 11 1 2 3 4 5 6 7 8 12 RJ45-6 RJ45-7 RJ45-7 XRF_TDC 2 RJ45-2 RJ45-3 RJ45-4 17 17 RJ45-1 XFR_RXC RJ1 LAN100M_LED# 1 RJ45-1 17 17 17 RJ45-6 7 MDI1- 470R2J-2-GP Green : Link up Blinking : TX/RX activity LAN_TERMINAL 1 C228 2 SC1500P2KV8KX-3GP 3 NEW1 NEWCARD Connector 28 Place them Near to Connector 3D3V_NEW_S0 3D3V_S5 1D5V_NEW_S0 3D3V_NEW_LAN_S5 SKT1 1D5V_S0 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SC10U10V5ZY-1GP C376 SCD1U16V2ZY-2GP 3 CLK_PCIE_NEW 3 CLK_PCIE_NEW# 3,20 CPPE# 3 NEWCARD_CLKREQ# 3D3V_NEW_S0 2 CARDBUS-SKT78-GP-U2 2 2 C370 2 2 C374 1 1 1 1 1 2 1 C377 2 1 2 C732 DY SCD1U16V2ZY-2GP C384 SC10U10V5ZY-1GP PCIE_RXP1 PCIE_RXN1 20 PCIE_RXP1 20 PCIE_RXN1 1 3 C737 DY SCD1U16V2ZY-2GP 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 20 PCIE_TXP1 20 PCIE_TXN1 Place them Near to Chip NEWCARD_CLKREQ# PERST# 3D3V_NEW_LAN_S5 For Newcard socket 20,26,27,31 PCIE_WAKE# 1D5V_NEW_S0 2 20,26 SMB_DATA 20,26 SMB_CLK 1D5V_NEW_S0 U11 3D3V_S0 SCD01U16V2KX-3GP C731 12 14 SIM-CARD 62.10024.681 1 SC4D7U10V5ZY-3GP C360 C427 2 20 2 NEWCARD_RST# 1 16 R567 1 2 DUMMY-R2 3D3V_S5 3D3V_NEW_LAN_S5 TYCO-CON26-1-GP 3D3V_S0 2 C144 1 C127 PACDN009MR-GP-U 2 NC#16 8 1 1 11 13 1.5VOUT 1.5VOUT 18 17 15 SCD1U16V2ZY-2GP SIM1 26 1D5V_S0 3D3V_S0 1 1 7 21 RCLKEN AUXIN AUXOUT 2 4 G577R9U-GP GND THERMAL_PAD 2 27 SC4D7U10V5ZY-3GP SCD1U16V2ZY-2GP PM_SLP_S4# STBY# SYSRST# PERST# CPUSB# CPPE# OC# SHDN# 3.3VIN 3.3VIN 17,20,31,36,37,38 1 6 8 9 10 19 20 7 2 PERST# CPUSB# 2 SC22P50V2JN-4GP CPPE# TPAD30 TP105 1NEWCARD_OC# R65 100KR2J-1-GP 26 UIM_DATA 9 UIM_PWR UIM_PWR 2 1 C719 2 33R2J-2-GP 3.3VOUT 3.3VOUT R576 1 PLT_RST1# 6 2 20 USB_PP1 20 USB_PN1 5 3 1 2 3 4 5 6 7 8 UIM_RST UIM_CLK UIM_RST UIM_CLK 26 DY 26 26 UIM_VPP UIM_VPP UIM_DATA 1 8,20,26,31,33,34,41 PM_SLP_S3# 1.5VIN 1.5VIN U67 20,22,31,34,37,38,40 3 5 4 1 3D3V_NEW_S0 SMB_DATA SMB_CLK 1CONN_TP2 1CONN_TP3 CPUSB# TPAD30 TP30 TPAD30 TP28 <Core Design> 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 10 Title LAN connector/NEW CARD/SIM ACES-CON8-3-GP 20.F0779.008 Size A3 Document Number Rev Pamirs-Discrete Date: Tuesday, December 12, 2006 A B C D Sheet E SA 28 of 47
- 29. B C D E 5V_S0 MDC1 1 R548 0R3-0-U-GP SCD1U16V2ZY-2GP MICBIAS_R 2 R301 SENSE 13 AUDIO_SENSE VC_REFA VREF_HI VREF_LO 28 26 27 AUDIO_REFA AUDIO_VREF_HI AUDIO_VREF_LO AUD_AGND R537 1 1 2 1 2 C406 SC1U10V3ZY-6GP MICL_AMP 1 2K2R2J-2-GP MICR_AMP 1 2K2R2J-2-GP R535 1 1 R290 2 0R0402-PAD C412 1 C418 C409 C410 CDAUD_GND 2 C403 SC1U10V3ZY-6GP 1 1 5V_AUX_S5 3D3V_AUD_S0 2 5K1R2F-2-GP CIR 3D3V_S0 C413 SCD1U16V2ZY-2GP 1 EC79 1 EC85 1 EC21 DY 1 EC41 DY DY 2 SCD1U16V2ZY-2GP 2 SC100P50V2JN-3GP 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 5V_AUX_S5 ACES-CON15-3-GP AUD_AGND 17 R581 10KR2J-3-GP 17 15 14 13 12 11 10 9 8 7 6 5 4 3 2 CIR CIR 30 MICR_AMP 30 MIC_INT_R 30 MICL_AMP 30 MIC_INT_L 17 DK_SPKR_L R575 330KR2F-L-GP 17 DK_SPKR_R HP_OUT_L DK_SPKR_L HP_OUT_R DK_SPKR_R JACK_DETECT# 3D3V_S0 U71 1 R280 47KR2J-2-GP 3D3V_AUD_S0 1 2 3 2 2 R285 R292 47KR2J-2-GP 47KR2J-2-GP 2 CDAUD_R 2 C404 SC1U10V3ZY-6GP 1 3 JACK_DETECT# CDAUD_L 2 C402 SC1U10V3ZY-6GP 1 CDAUDR CDAGND 2 0R0402-PAD 1 1 R288 23 CD_AGND 1 JACK_DETECT# 17 DK_MIC_IN# 2 10KR2F-2-GP R534 1 1 23 CD_AUDR CDAUDL 2 0R0402-PAD 1 MIC_IN# 2 20KR2F-L-GP 2 1 R282 2 5K1R2F-2-GP R536 1 MICBIAS_L 30 MICBIAS_R 30 MICBIAS_R 23 CD_AUDL 1 2 C411 AUD_AGND 2 1 2 AUD_AGND DK_MICL_C R300 CX20549-12Z-GP-U 2N7002DW-1-GP 1 DK_MICR_C 2 1 AVSS AVSS AVSS AVSS_HP HP_OUT_R 2 SC100P50V2JN-3GP 2 SC100P50V2JN-3GP 2 SC100P50V2JN-3GP 2 SC100P50V2JN-3GP 2 SC100P50V2JN-3GP 2 SC100P50V2JN-3GP 1 AUD_AGND C405 1 SC1U10V3ZY-6GP 12 25 32 40 HP_OUT_L HP_OUT_R DK_MIC_L DK_MIC_R 1 MIC_IN 1 DK_SPKR_L DY C689 SC470P50V2KX-3GP DYEC84 DYEC82 DYEC83 DYEC81 1 MICR_C VDD 4 20 SB_SPKR C395 R274 1 SCD1U16V2ZY-2GP AUD1 MIC_IN 4K7R2J-2-GP 1 AUD_PC_BEEP 2 1 2 AUD_AGND EC86 1 2 AUD_AGND DY 2 MICR_AMP 0R2J-2-GP 1 R577 MICR_C 2 SC1U10V3ZY-6GP 1 MICL 1 1218 G76 R273 C414 20.K0013.015 AUD_AGND G1214TAUF-GP-U SCD1U25V3ZY-1GP AUD_BEEP 2 7K5R2J-GP MICR 2 1 16 5 OUT IN+ VSS IN- AUD_AGND 1025 SA 4 SC1U10V3ZY-6GP 1 VSS_IO VSS_IO DVSS HP_OUT_L 17,41 DK_SPKR_R 2 42 46 6 EC40 SCD1U16V2ZY-2GP DVDD_M MICL MICR CDAUD_L CDAUD_GND CDAUD_R 2 2 6 45 MIC_INT_L SC10U10V5ZY-1GP 1 5 MIC_IN# 2 29 30 DVDD DK_MIC_IN# DK_MIC_IN MICBIAS_L MICBIAS_L MICBIAS_R VDD_IO 2 3 8 3 33 34 14 15 AUD_LOL 30 AUD_LOR 30 1 3D3V_AUD_S0 C688 SCD1U16V2ZY-2GP 38 39 23 24 AVDD AVDD AVDD_HP MIC_INT_R SPDIF AUD_PC_BEEP 2 3 PORT-A_L PORT-A_R PORT-B_L PORT-B_R RESERVED#1 RESERVED#2 RESERVED#16 20 31 2 3D3V_AUD_S0 4 C724 EC39 PORT-A_BIAS_L PORT-A_BIAS_R PORT-B_BIAS_L PORT-B_BIAS_R 1 2 16 DY47KR2J-2-GP AMOM_DIPN 2 0R0402-PAD 48 11 35 36 21 22 17 18 19 EAPD 37 1 R547 1 R293 S/PDIF PCBEEP LINE_OUT_L LINE_OUT_R MIC_L MIC_R CD_L CD_GRD CD_R SYNC BIT_CLK SDATA_OUT SDATA_IN RESET# 47 EAPD U75 4 AUD_AGND AMOM_DIPP 2 0R0402-PAD 44 43 SCD1U16V2ZY-2GP 2 22R2J-2-GP 9 5 HDA_SDOUT_CODEC 4 HDA_SDATAIN0_CODEC 7 10 1 R291 AMOM_DIBP_R AMOM_DIBP_N DIBP DIBN RC_OSC 1 R271 1 41 2 2 240KR2J-1-GP SC10U10V5ZY-1GP 1 R543 19 HDA_SYNC_CODEC 19 HDA_BITCLK_CODEC 3D3V_S5 OUT AUD_AGND U49 30,31,32 5 G913CF-GP 20.E0077.204 3D3V_AUD_S0 19 HDA_SDOUT_CODEC 19 HDA_SDIN0 19 HDA_RST#_CODEC SET SHDN# GND IN 2 C703 2 2 2 SCD1U16V2ZY-2GP 4 C691 SCD1U16V2ZY-2GP C694 SC1U10V3ZY-6GP 2 C697 C716 SC1U10V3ZY-6GP SYN-CONN8E-GPU 1 1 1 DY 4 1 2 1 2 3 1 3D3V_AUD_S0 3D3V_S0 AMOM_DIPP AMOM_DIPN 1 2 3 3D3V_LDO_S0 U69 8 NP1 7 6 NP2 5 2 1 1 R560 0R3-0-U-GP 2 2 3D3V_LDO_S0 SC10U10V5ZY-1GP A 1 CUT MOAT RN73 DK_MIC_R_C DK_MIC_L_C MICR_C 30 1 2 DK_MICR_C DK_MICL_C 4 3 2 GAP-CLOSE-PWR AUD_AGND R588 10KR2J-3-GP AUD_AGND SRN10KJ-5-GP DK_MIC_R_CN SC1U10V3ZY-6GP DK_MIC_R_CN DK_MIC_L_C 1 2 DK_MIC_L_CN SC1U10V3ZY-6GP DK_MIC_L_CN 17 <Core Design> 1 R552 1KR2J-1-GP R590 47KR2J-2-GP Wistron Corporation C745 SCD1U16V2ZY-2GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 2 2 DK_MIC_R_CN 1 1 R551 1KR2J-1-GP C696 DK_MIC_R_C1 2 1 2 MICL_AMP 0R2J-2-GP 1 2 1 R572 DK_MIC_IN MICL_C 30 1 MICL_C SC1U10V3ZY-6GP 2 C415 2 2 1 17 Title AUD_AGND AUD_AGND AUD_AGND AUDIO CODEC CX20549-12Z Size A3 Put near Codec C695 Document Number Date: Monday, December 18, 2006 A B C D Rev SA Pamirs-Discrete Sheet E 29 of 47
- 30. A B C D E 5V_S0 5VA_OP_S0 R570 1 C721 SC1U10V3ZY-6GP 2 EC_BEEP 29 1 AUD_LOL 2 1 47KR2J-2-GP R307 C419 4 G52 1 L_LINE_IN_1 2 GAP-CLOSE-PWR 1 L_LINE_IN 2 1KR2J-1-GP SCD47U16V3ZY-3GP 2 4 1 31 R302 DUMMY-R2 2 1 5V_S0 R580 100KR2J-1-GP AUD_AGND 2 5VA_OP_S0 U53 1 2 R578 0R2J-2-GP 1 2 5VA_OP_S0 1 R566 2 10KR2J-3-GP 2 AUD_AGND DY 1 2 3 5VA_OP_S0 R574 DY 0R2J-2-GP SPKR_L+ 1 2 4 AUD_AGND R573 0R2J-2-GP SPKR_L8 1 C425 RIN+ R_LINE_IN 2 SC1U10V3ZY-6GP 19 10 SHUTDOWN# BYPASS 9 5 LIN+ LINROUT+ ROUT- 1 C428 LIN+ 1 L_LINE_IN C426 KBC_MUTE# 31 2 SC1U10V3ZY-6GP 2 SC1U10V3ZY-6GP SPKR_R+ SPKR_R- Q32 2N7002-11-GP 1 11 13 20 21 LOUT+ LOUTRIN+ RIN- 12 BYPASS 18 14 GND GND GND GND GND GAIN0 GAIN1 7 17 AUD_AGND 3 PVDD PVDD AUD_AGND G S 1 2 SC1U10V3ZY-6GP C422 SC4D7U10V5ZY-3GP VDD 15 6 C421 D 16 NC#12 G1431F2U-GP EAPD 29,31,32 DY 3 AUD_AGND R568 31 2 EC_BEEP 1 C720 SC1U10V3ZY-6GP 1 2 47KR2J-2-GP C420 1 2 AUD_LOR R306 R_LINE_IN_1 1 SCD47U16V3ZY-3GP R_LINE_IN 2 1KR2J-1-GP 1 29 2 R304 DUMMY-R2 AUD_AGND EC68 1 MIC_INT_R 3D3V_AUD_S0 MIC_INT_L MICBIAS_R AUD_AGND 2 AUD_AGND RC1 DY VDD 5 OUT IN+ VSS IN- C741 SCD1U16V2ZY-2GP 4 SPKR_R+ SPKR_RSPKR_L+ SPKR_L- AUD_AGND MICR_C 29 10KR2J-3-GP DY G1214TAUF-GP-U 1 C729 2 AUD_AGND 29 29 2 100KR2J-1-GP 1 2 Speaker DY R583 1 1 SCD22U16V3ZY-GP 2 AUD_AGND 1 2 3 SPKR_R+ DY VDD 5 OUT IN+ VSS IN- C738 SCD1U16V2ZY-2GP 4 SPKR_LSPKR_L+ SPKR_R- 1 2 3 4 AUD_AGND 1 ACES-CON4-1-GP SPKR1 AUD_AGND MICL_C 29 2 <Core Design> 1 Wistron Corporation 20.D0197.104 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 10KR2J-3-GP G1214TAUF-GP-U C725 DY 2 DUMMY-C2 1 C726 AUD_AGND Title 2 SC680P-GP AUDIO AMP/SPEAKER DY 1 R582 A 20.D0197.104 0R2J-2-GP 4 3 2 5 U72 DY 2 1 C733 SC100P50V2JN-3GP 1 MICL_AMP MIC_INT_R MIC_INT_L R439 3D3V_AUD_S0 29 MIC_INT_R MIC_INT_L DY MICBIAS_L C718 1 2 MIC1 ACES-CON4-1-GP 1 2 SC680P-GP DY 1 R587 29 8 7 6 5 SRC100P50V-2-GP C727 DUMMY-C2 1 2 3 4 6 SCD22U16V3ZY-GP DY DY 6 1 2 5 1 2 3 R586 C722 1 2 1 MICR_AMP SC100P50V2JN-3GP 1 U73 2 1 C736 SC100P50V2JN-3GP DY 29 SC100P50V2JN-3GP 2 EC67 2 29 2 1 DY DY 2 Size A3 2 100KR2J-1-GP DY Document Number Rev B C D SA Pamirs-Discrete Date: Monday, November 27, 2006 Sheet E 30 of 47
- 31. 2 GAP-CLOSE-PWR 33 KBCBIOS_RD# 150 KBCBIOS_WE# 151 KBCBIOS_CS# 173 152 KBC_D[0..7] KBC_D0 138 KBC_D1 139 KBC_D2 140 KBC_D3 141 KBC_D4 144 KBC_D5 145 KBC_D6 146 KBC_D7 147 Add Label "VCC" G70 E51_TXD 2 GAP-CLOSE-PWR Add Label "TXD" 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 G71 E51_RXD 2 GAP-CLOSE-PWR 1 Add Label "RXD" 5V_S0 0126 G73 1 2 GAP-CLOSE-PWR 32 5V_S0 RN51 32 TDATA_5 TCLK_5 4 3 2 1 B A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 5 6 7 8 SRN10KJ-6-GP 1 2 2 X-bus ROM KB3910 PS/2 D 2 2 2 XCLKO XCLKI D0 D1 D2 D3 D4 D5 D6 D7 41 28 27 25 24 23 DOCK_IN# 17 ECSMI# 20 WIFI_RF_EN 26 PM_CLKRUN# 20,24,34 BLON_OUT 16 NUMLK_LED 23 98 97 94 93 92 91 BLUETOOTH_EN 32 GPIOI2D GPIO2F GPIO2E GPIO2C GPIO2B GPIO2A RD# WR# MEMCS# IOCS# PSDAT3 PSCLK3 PSDAT2 PSCLK2 PSDAT1 PSCLK1 R492 10KR2J-3-GP KBC_3D3V_AUX KBC_MATRIX1 KBC_MATRIX0 155 149 148 119 118 109 108 107 106 105 86 85 75 70 69 63 62 55 54 48 22 21 20 12 11 8 6 5 4 3 GPIO1F GPIO1E GPIO1D GPIO1C GPIO1B GPIO1A LPC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 1 1 2 1 160 158 163 164 169 170 SCL1 SDA1 SCL2 SDA2 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 R498 DUMMY-R2 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO09 GPIO08 GPIO07 GPIO06 GPIO05 GPIO04 GPIO03 GPIO02 GPIO01 GPIO00 KB Matrix LFRAME# LCLK SERIRQ 117 116 115 114 111 110 R494 10KR2J-3-GP GPIO0F GPIO0E GPIO0D GPIO0C GPIO0B GPIO0A LAD0 LAD1 LAD2 LAD3 124 125 126 127 128 131 132 133 143 142 135 134 130 129 121 120 113 112 104 103 1 2 4 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7 KROW8 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 49 50 51 52 53 56 57 58 59 60 61 64 65 66 67 68 153 154 U42 168 175 171 165 162 156 TP102 TP104 GPIO13 E51_TXD E51_RXD E51CS# 2 10KR2J-3-GP E51CS# TP_BTN# 32 CHG_ON# 39 AD_OFF 46 EAPD 29,30,32 E51_TXD 26 E51_RXD 26 1 R500 1 R512 2 10KR2J-3-GP BT_TH 1 2 R528 DUMMY-R2 TP101 Pull-up by devided-resistor to MAX8725_LDO TP_LED 16 PWR_LED 16 3D3V_S5 VOL_DWN_DK# 17 VOL_UP_DK# 17 SB_PWR_BTN# 2 1 PM_SLP_S4# 17,20,28,36,37,38 R242 DY 10KR2J-3-GP GPIO13 ICH8 integrated pull-up CAPS_LED 16 CAP_ACK 32 CAP_XPRES 32 CAP_DAT 32 R243 S5_ENABLE 1 2 10KR2J-3-GP C FAN3FB FAN3PWM KBC_3D3V_AUX WIRELESS_BTN# 33 KBRST# 19 KBGA20 19 BT_DET# 32 BT_TH 39,46 RN71 4 KBC_SCL0 3 KBC_SDA0 1 2 KBC_3D3V_AUX SRN4K7J-8-GP RN70 1 2 4 KBC_SCL1 3 KBC_SDA1 SRN10KJ-5-GP 3D3V_S5 1 33 KBCBIOS_RD# 33 KBCBIOS_WE# 33 KBCBIOS_CS# TP103 G74 C SC15P50V2JN-2-GP R296 100KR2J-1-GP.Normal MUTE_LED# 17,32 WLANONLED_KBC CHG_LED 16 TP29 2 5V_AUX_S5 PCB_VER0 PCB_VER1 PCB_VER2 SB_RSMPWR 1 2 R278 0R2J-2-GP PCI_SERR# 18,24 KBC_MUTE# 30 PLT_RST1# 7,18,20,26,28,33,34,41 THRM#_R 1 R538 2 0R2J-2-GP 1 9 18 7 19,33,34 LPC_FRAME# 3 PCLK_KBC 20,24,34 INT_SERIRQ 1 C398 1 2 Planar ID(2,1,0) SA: 0,0,0 SB: 0,0,1 SC: 0,1,0 SD: 0,1,1 SE: 1,0,0 -1: 1,0,1 R496 DUMMY-R2 R497 10KR2J-3-GP BLON_IN 42 C407 SC1U10V3ZY-6GP 2 LPC_LAD0 15 LPC_LAD1 14 LPC_LAD2 13 LPC_LAD3 10 R495 DUMMY-R2 0110 1 19,33,34 LPC_LAD[0..3] VCCBAT VCC VCC VCC VCC VCC VCC VCC VCCA GAP-CLOSE-PWR 1 SC15P50V2JN-2-GP 2 1 KBC_3D3V_AUX X4 X-32D768KHZ-40GPU KBC_XI 161 3D3V_AUX_S5 G75 1 1 C366 C367 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP 2 KBC_3D3V_AUX D 1 SCD1U16V2ZY-2GP KBC_XO 23D3V_KBC_AUX_S5 2 16 34 45 123 136 157 166 95 SCD1U16V2ZY-2GP 1 BLM11P600S SCD01U16V2KX-3GP 2 SC10U10V5ZY-1GP L29 C390 2 2 C386 2 C673 1 1 1 1 KBC_3D3V_AUX DY C687 2 1031 SA C399 1 2 KBC_SDA1 KBC_SCL1 KBC_SDA0 KBC_SCL0 3 22,32 22,32 46 46 1 3 KCOL[1..16] 32 KROW[1..8] 32 1 4 71 72 73 74 77 78 79 80 5 KBC_3D3V_AUX R297 100KR2J-1-GP THRM# 22 B 2 EC_SWI# 20 SB_PWR_BTN# 20 SB_RSMRST# 22 S5_ENABLE 16 BRIGHTNESS 1 R241 TP100 GND GND GND GND GND GND AGND BATGND ECRST# ECSCI# AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 2 4 3 PCB_VER2 PCB_VER1 PCB_VER0 BT_SENSE AIRLINE_VOLT 1 R646 2 0R2J-2-GP 1 1218 R248 PWR_BTN# 2 10KR2J-3-GP R253 CHG_ON# 2 10KR2J-3-GP 1 R251 KBRST# 2 10KR2J-3-GP 2 PM_CLKRUN# 10KR2J-3-GP 1 R511 2 SB_RSMRST# 10KR2J-3-GP DY 3D3V_S5 Intel checklist suggest no external resistor needed 5V_AUX_S5 1 BT+ R238 CIR_SENSE 2 10KR2J-3-GP 1 AIRLINE_VOLT 39 R276 BT_DET# 2 10KR2J-3-GP 3D3V_S5 1 R246 R501 560KR2F-GP 1218 ECSMI# 1 R506 <Core Design> 2 100KR2J-1-GP 2 100KR2J-1-GP EC_SWI# A Wistron Corporation BT_SENSE 1 R502 AD_IA 1 C364 2 SCD1U16V2ZY-2GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 2 100KR2F-L1-GP A4 for DMRP==>High=Disable,Low=Enable Title A5 for EMWB==>High=Enable,Low=Disable GPIO05 for Clock test mode==>High=test Mode,Low=32KHz clock in normal running(Recommended) GPIO06 for DPLL test mode==>High=Test Mode,Low=Normal operation(Recommended) 1 R265 3D3V_S5 KBC_3D3V_AUX 1 CHG_I_PRE_SEL 39 CHG_I_SEL 39 CHG_4CELL 39 4CELL# 39 PM_LAN_ENABLE M_WXMIT_OFF# 26 CHG_I_SEL VOL_DWN_DK# VOL_UP_DK# SRN10KJ-5-GP K A ECSCI# 20 EC_RST# 1N4148W-1-GP EC_RST# 22 AD_IA AD_IA 39 1 2 RN49 1 2 D20 2 0R0402-PAD 20,22,28,34,37,38,40 PM_SLP_S3# 17 PWR_BTN# 33 KBC_PWR_BTN# 39 AC_IN# R261 33 LID_CLOSE# 10KR2J-3-GP R254 17 CIR_SENSE 10KR2J-3-GP 32 INSTANT_ON_BTN# 20,26,27,28 PCIE_WAKE# KB3910SF-2-GP 1 1 EC_BEEP 2 2 2 DUMMY-R2 DUMMY-R2 R519 R525 A R256 DUMMY-R2 2 1 1 1 FAN3PWM FAN3FB DUMMY-R2 2 A5 A4 19 R516 R258 10KR2J-3-GP 2 R521 10KR2J-3-GP 1 1 1 30 ECSCI# 2 R240 100KR2J-1-GP KBGA20 1 R522 2 10KR2J-3-GP 1 3D3V_S0 3D3V_S0 2 3D3V_AUX_S5 PM_LAN_ENABLE1 DY 17 35 46 122 137 167 EXT_FWH# 33 96 159 2 1KR2J-1-GP 19 31 1 81 82 83 84 87 88 89 90 A5 BRIGHTNESS_PWM 2 43 40 39 38 37 36 33 32 1 100KR2J-1-GP 99 100 101 102 1 42 47 174 R530 R531 GPWU0 GPWU1 GPWU2 GPWU3 GPWU4 GPWU5 GPWU6 GPWU7 3D3V_AUX_S5 2 26 29 30 44 76 172 176 PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 DY KBC_ENE K3910SF Size A3 Document Number Rev SA Pamirs-Discrete Date: Tuesday, December 19, 2006 Sheet 31 of 47
- 32. CAMERA 5V_S0 Blue thumb 3D3V_S0 MATRIXID2# 0 0 1 2 C749 BT_PRIORITY WL_PRIORITY BT_LED 20.D0197.105 1 20 2 0R0402-PAD R137 EC92 SCD1U16V2ZY-2GP DY USB_4- USB_PN4 4 ACES-CON24-2-GP EC91 DY SCD1U16V2ZY-2GP 5V_S3 1 2 DY D36 2 20 USB_4+ USB_PP4 1 DY 1 R138 2 0R0402-PAD 3D3V_BT_S0 C740 SC1U10V3ZY-6GP MAX 150mA 2 1 U74 4 1 C587 SC1U10V3ZY-6GP G913CF-GP TR4 20 5 1 2 2 TPAD1 1 2 3 4 6 CAPACITY BUTTON BAV99W-1-GP 2 0R0402-PAD R310 3D3V_AUX_S5 3D3V_S0 D19 3D3V_AUX_S5 D6 2 2 FOX-CON4-12-GP TP_BTN_1# 1 C586 SC33P50V2JN-3GP DY 1 3D3V_AUX_S5 2 2 C588 SC33P50V2JN-3GP 1 TDATA_5 TCLK_5 1 31 31 CAP_ACK 3 USB_5+ USB_PP5 SA 1011 DY 3 R43 10KR2J-3-GP 1 EC5 SCD1U16V2ZY-2GP DY 1 KCOL3 KCOL5 KCOL8 KCOL9 2 KROW2 KROW8 KROW7 KCOL10 BAV99W-1-GP EAPD# 17 5V_S0 3D3V_S0 D KROW4 KCOL6 KCOL2 KROW1 EAPD# 8 7 6 5 29,30,31 G EAPD 17,31 MUTE_LED# 3D3V_AUX_S5 D5 2 1 INSTANT_ON_BTN# 3 2 1 3 1 <Core Design> 2 100R2J-2-GP R487 6 1 2 3 4 62.40009.451 3D3V_AUX_S5 D9 2 TP_BTN# 31 1 8 7 6 5 8 7 6 5 1 2 3 4 ACES-CON12-4-GP 2 SCD1U16V2ZY-2GP 20.K0228.012 2 SC100P50V2JN-3GP 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP BAV99W-1-GP SW1 SW-TACT-68-GP-U 2 RC6 SRC100P50V-2-GP 1 TP_BTN_1# 4 RC7 SRC100P50V-2-GP 1 DY EC44 CAP_ACK 1 CAP_DAT DY EC7 1 INSTANT_ON_BTN# DY EC8 1 EAPD# DY EC9 1 DY EC12 DY R488 10KR2J-3-GP TOUCH-PAD SWITCH 5 KCOL7 KCOL4 KCOL13 KCOL14 2 for EMI KCOL15 KCOL12 KCOL11 KCOL16 14 5V_S0 3D3V_S0 for EMI 2 2 31 CAP_XPRES DY 1 0R2J-2-GP R327 2 3 DY 1 0R2J-2-GP 22,31 KBC_SCL1 R326 2 4 DY 1 0R2J-2-GP 22,31 KBC_SDA1 R325 5 31 CAP_ACK 6 31 CAP_DAT 7 31 INSTANT_ON_BTN# R345 DY 1 2 8 R342 0R2J-2-GP MUTE_LED_1# 1 2 9 0R2J-2-GP 10 EAPD# 1 2 11 R81 1 0R2J-2-GP 2 12 R80 DY 0R2J-2-GP S RC2 SRC100P50V-2-GP 1 2 3 4 RC5 SRC100P50V-2-GP 1 2 3 4 RC4 SRC100P50V-2-GP 1 2 3 4 1 2 3 4 8 7 6 5 8 7 6 5 8 7 6 5 Q3 2N7002-11-GP RC3 SRC100P50V-2-GP CAP1 13 CAP_DAT 3 1 BAV99W-1-GP KROW3 KROW6 KCOL1 KROW5 C735 SCD1U16V2ZY-2GP 2 2 R424 10KR2J-3-GP 10KR2J-3-GP 1 R428 C739 SC4D7U10V5ZY-3GP D7 DY 1 1 1 4 3D3V_AUX_S5 L-63UH-GP BAV99W-1-GP SET OUT SHDN# GND IN 1 C585 SCD1U16V2ZY-2GP DY 3 31 BLUETOOTH_EN 2 2 5V_S3 2 1 2 USB_5- USB_PN5 5 1 20 1 2 3 2 5V_S3 D35 3D3V_AUX_S5 2 0R0402-PAD R311 1 1 2 TouchPad Connector 3 BAV99W-1-GP TCLK_5 EC93 DY SCD1U16V2ZY-2GP Close to CN8 L-63UH-GP 20.K0220.024 EC90 DY SCD1U16V2ZY-2GP TR2 3D3V_AUX_S5 20.F0772.008 3D3V_BT_S0 1 CAM1 10 ACES-CON8-4-GP 2 2 R600=31K6R2 1 31K6R2F-GP (3.93V) 33 BT_LED 26 WL_PRIORITY 26 BT_PRIORITY 31 BT_DET# DY R600 2 1 4 G913CF-GP USB_4+ 1 6 OUT 2 3 4 5 6 7 8 USB_5+ USB_5- 5 2 C478 SC4D7U10V5ZY-3GP 2 USB_4- SET 1 1 C493 26 TDATA_5 3 SC1U10V3ZY-6GP 2 1 SCD1U16V2ZY-2GP 1 7 5 4 3 2 SHDN# GND IN 1 0 1 2 3 DY 2 1 ACES-CON5-1GP 1 3D3V_BT_S0 U77 C748 DY 1 0 Jap 0R5J-6-GP DY 2 MATRIXID1# Eur 9 SC10U10V5ZY-1GP US BT1 R599 68KR2F-GP 3D3V_CAM_S0 3 Keyboard matrix ( from vendor ) R386 5V_S0 0R5J-6-GP 1 31 KCOL[1..16] KROW8 KROW7 KCOL10 KROW5 KROW6 KCOL1 KROW3 KROW4 KCOL6 KCOL2 KROW1 KCOL3 KCOL5 KCOL8 KCOL9 KCOL7 KCOL4 KCOL13 KCOL14 KCOL15 KCOL12 KCOL11 KCOL16 R381 2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 31 KROW[1..8] KROW2 1 1 2 25 Internal KeyBoard Connector 2 1 KB1 3D3V_CAM_S0 (3.3V) C670 SC1000P50V3JN-GP DY EAPD# 3 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. DY 1 Title KeyBoard-CONN BAV99W-1-GP Size A3 Document Number for EMI Date: Monday, December 18, 2006 Rev Pamirs-Discrete Sheet 32 of SA 47
- 33. A B C D E GOLDEN FINGER FOR DEBUG BOARD TOP VIEW 5V_S0_LPC 5V_S0_LPC U76 3D3V_AUX_S5 A14 U64 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 16 17 48 1 2 3 4 5 6 7 8 18 19 20 21 22 23 24 25 31 KBCBIOS_CS# 31 KBCBIOS_RD# 31 KBCBIOS_WE# R533 10KR2J-3-GP 1 3D3V_AUX_S5 3 R515 1 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 26 28 11 47 12 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 VCC CE# OE# WE# BYTE# RESET# 2 2 10KR2J-3-GP Q15/A-1 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 45 43 41 39 36 34 32 30 44 42 40 38 35 33 31 29 RY/BY# (B2) PLT_RST1#_1 LPC_LFRAME#_1 LPC_GND PCLK_FWH_1 A2 KBC_D[0..7] KBC_D7 KBC_D6 KBC_D5 KBC_D4 KBC_D3 KBC_D2 KBC_D1 KBC_D0 (B14) A1 31 (B15) LPC_LAD3_1 LPC_LAD2_1 LPC_LAD1_1 LPC_LAD0_1 EXT_FWH#_1 3D3V_S0_LPC A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 (BOTTOM VIEW) A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 46 27 G81 LPC_LAD[0..3] 19,31,34 7,18,20,26,28,31,34,41 PLT_RST1# PLT_RST1# R2 LPC_FRAME# E KBC_3D3V_AUX 1 R28 2 200R2J-L1-GP 1 2 100R2J-2-GP EC1 4 ACES-CON3-1-GP 20.F0735.003 2 3D3V_S0 LPC_LAD3 KBC_PWR_BTN# 31 1 1 R6 1 C441 SCD22U16V3ZY-GP C8 SC1000P50V3JN-GP DY 1 LPC_LAD1_1 2 1 R431 100KR2J-1-GP D 1 LPC_LAD0_1 2 GAP-OPEN-PWR 1 2 G49 LPC_LAD0 G50 31 EXT_FWH# EXT_FWH# 1 EXT_FWH#_1 2 2 GAP-OPEN-PWR 3D3V_S0 WLANONLED 26 3D3V_S0_LPC G51 1 2 GAP-OPEN-PWR 1 G80 1 R435 1KR2J-1-GP LPC_GND 2 GAP-OPEN-PWR Put near board edge 2 1 2 3 4 2 G48 LPC_LAD1 3D3V_S0 1 LPC_LAD2_1 2 GAP-OPEN-PWR S 1 G47 1 LPC_LAD2 BT_LED 32 2 5 WLAN1 ACES-CON4-1-GP LPC_LAD3_1 2 GAP-OPEN-PWR G EC31 DY SCD1U16V2ZY-2GP 1 SCD1U16V2ZY-2GP 3D3V_S0 Q31 2N7002-11-GP 5V_S0 PCLK_FWH_1 2 GAP-OPEN-PWR R425 100KR2J-1-GP WIRELESS SWITCH 1 GAP-OPEN-PWR R5 10KR2J-3-GP G46 3 2 1 2 20.D0197.102 SCD1U16V2ZY-2GP 2 2 SC1000P50V3JN-GP DY 2 2 LID_CLOSE# 31 C445 SCD1U16V2ZY-2GP LPC_LFRAME#_1 2 EC3 5 2 100R2J-2-GP 3 2 POWER SWITCH 2 PDTA124EU-1-GP 1 PCLK_FWH 3 PCLK_FWH EC6 1 C 1 1 2 ACES-CON2-1-GP-U 1 PLT_RST1#_1 2 GAP-OPEN-PWR G79 1 B PWR_LED# 1 16 R1 COVER_SW 1 GAP-OPEN-PWR G78 PWR1 2 4 5V_S0_LPC 2 GAP-OPEN-PWR G77 5V_S3 R319 10KR2J-3-GP R320 3D3V_S0_LPC 1 MX29LV800CBTC-GP KBC_3D3V_AUX 3 1 4 LPC_LAD3_1 LPC_LAD2_1 LPC_LAD1_1 LPC_LAD0_1 EXT_FWH#_1 5V_S0 19,31,34 LPC_FRAME# LID1 PLT_RST1#_1 LPC_LFRAME#_1 LPC_GND PCLK_FWH_1 Boot Device must have ID[3:0] = 0000 Has internal pull-down resistors All may be left floated FPET7 Elec. P3-46 Q1 COVER SWITCH B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 FOX-GF30 ZZ.GF030.XXX 14 13 10 9 GND GND 31 15 NC#14 NC#13 NC#10 NC#9 A0 .... 37 4 (B1) .... A15 R442 10KR2J-3-GP <Core Design> 1 6 2 1 2 100R2J-2-GP Wistron Corporation WIRELESS_BTN# 31 2 1 1 R443 20.D0197.104 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. C593 SC1000P50V3JN-GP DY Title FWH and Debug Size A3 Document Number Date: Thursday, November 02, 2006 A B C D Rev Pamirs-Discrete Sheet E 33 of SA 47
- 34. 3D3V_S0 DY R299 PP TPM 1.2 5V_AUX_S5 TO 5V_S5 1 2 2 4K7R2J-2-GP 3D3V_S0 2 PWR_S5_EN_2 2 1 1 1 2 2 2 26 23 20 17 3 20 19,31,33 7,18,20,26,28,31,33,41 C430 1 LAD0 LAD1 LAD2 LAD3 TPM_XTALI TPM_XTALO PP CLKRUN# SERIRQ 7 15 27 NC#1 NC#3 NC#12 2 0R2J-2-GP R305 4K7R2J-2-GP 1 3 12 GND GND GND GND DY 2 LCLK LPCPD# LFRAME# LRESET# LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 TESTB1 TEST1_1 1 R303 PP R308 4K7R2J-2-GP TP34 TP33 1 SCD1U16V2KX-3GP 1 21 28 22 16 9 8 XTALI/32K_IN XTALO CLK_PCI_TCG LPC_PD# LPC_FRAME# PLT_RST1# 9636GPIO 1 9636GPIO21 TPM_XTALO 1 DY SC10P50V2JN-4GP 19,31,33 19,31,33 19,31,33 19,31,33 1 C387 SCD1U16V2KX-3GP 2 13 14 6 2 TESTBI/BADD TESTI VSB VDD VDD VDD 4 11 18 25 DY PM_CLKRUN# 20,24,31 INT_SERIRQ 20,24,31 DY 2 1 2 SC4D7U10V5KX-1GP 2 1 C381 GPIO GPIO2 5 10 19 24 RESO-32D768KHZ-GP C375 2 SCD1U16V2KX-3GP 1 R252 1 C378 SCD1U16V2KX-3GP 2 2 DY 2 G 1 SC1U10V3KX-3GP 2 R313 10MR2J-L-GP DY 47KR2J-2-GP 22,36 PWR_S5_EN# X5 3 SCD1U16V2KX-3GP D R249 100KR2J-1-GP 1 2 TPM_XTALI 1 DY SCD1U16V2KX-3GP 2 3D3V_S0 U52 4 C380 DY C416 SCD1U16V2KX-3GP C429 5V_S5 1 S R298 0R2J-2-GP DY C423 C424 DY SC10P50V2JN-4GP SI2301BDS-T1-GP Q14 5V_AUX_S5 DY C417 1 1 DY 3D3V_S5 D22 1N4148W-1-GP A 20 TPM_32K_CLK 1218 R312 DY 1 2 TPM_XTALI 0R2J-2-GP SLB9635TT1D1-GP DY 3D3V_S0 Q16 TP0610K-T1-GP R294 1KR2J-1-GP 1 D D D D 8 7 6 5 3D3V_S5 1 1 2 3 4 U47 S S S G D D D D 2 R603 R604 0R2J-2-GP 0R2J-2-GP FOX-CON4-12-GP 6 4 3 2 AO4422-1-GP D23 RLZ12B-1-GP 3D3V_S0 DY PM_SLP_S3#_Z12V DY Finger PWR USB_8USB_8+ 1031 SA 1 5 8 7 6 5 CN1 1D8V_S0 PM_SLP_S3#_Z12V E U50 2N7002DW-1-GP 1 2 3D3V_S0 3 R286 100R5J-3-GP 1D8V_S3 1 2 3 4 U20 S S S G D D D D 8 7 6 5 1 17 USB20_N8 R427 USB_82 0R0402-PAD AO4422-1-GP 1 17 USB20_P8 R426 2 0R0402-PAD USB_8+ 2 R2 PDTC124EU-1-GP C 5 R1 Finger Printer U48 S S S G AO4422-1-GP 4 B 2 Q17 PM_SLP_S3# 2 2 1 2 330KR2J-L1-GP SCD1U25V3KX-GP G 1 R287 20,22,28,31,37,38,40 DY R295 330KR2J-L1-GP 1 20KR2J-L2-GP C408 2 RUN_PWR_CTLR 1 3 D 2 1 2 3 4 1 Z_12V 2 S R289 1 6 DCBATOUT 1218 2 5V_S0 1 Run Power 3D3V_S5 5V_S3 1 K <Core Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title PWRPLANE&RESETLOGIC Size A3 Document Number Date: Monday, December 18, 2006 Rev Pamirs-Discrete Sheet 34 of SA 47
- 35. 5 4 3 2 1 5V_S0 2 SC4D7U25V5MX-1GP SC4D7U25V5MX-1GP 2 1 SC4D7U25V5MX-1GP 2 1 4 3 2 1 4 3 2 1 ST330U2D5VDM-9GP C171 1 2 C161 SC1000P50V2JN-GP ST330U2D5VDM-9GP ST330U2D5VDM-9GP GND 20 VPS 13 MAX8736_VPS FBS 12 MAX8736_FBS ST330U2D5VDM-9GP 1 2 ST330U2D5VDM-9GP 1 2 1 2 1 1 ST330U2D5VDM-9GP 2 2 2 1 2 4 3 2 1 4 3 2 1 3K3R3F-GP 2 1 2 1 5 6 7 8 5 6 7 8 11 TC19 NTC-10K-9-GP C 2 Panasonic , 330uF/2V ESR = 9m ohm 7.3*4.3*1.9 SCD22U10V3KX-2GP 9 GNDS TC6 10 CSN3 C289 DY 2 CSP3 5 VCC_SENSE 5 DCBATOUT C304 D16 1 4 3 2 1 4 3 2 1 1 C164 MAX8552ETB-1-GP 2 NTC-10K-9-GP SCD01U16V2KX-3GP 1 2 1 R160 2 1 3K3R3F-GP DY 2 1 2 R161 4 3 2 1 C331 SC1000P50V2JN-GP G30 GAP-CLOSE-PWR 1 AO4430-1-GP DY C294 2 L-D36UH-1-GP R159 2KR3F-L-GP 5 6 7 8 5 6 7 8 AO4430-1-GP 4 3 2 1 PWM 1 6 2 EN PWM2 MAX8552_DL Q28 S S S S G 7 2 Q9 S S S S G DRSKP# MAX8552_LX 3 L45 1 MAX8552_DH 8 1 1 1 VCC 2 2 MAX8552_AGND 9 AO4422-1-GP MAX8552_BST DH C335 SCD22U16V3KX-2-GP D D D D D DLY B SCD1U50V3KX-GP Q29 AO4422-1-GP D D D D D 5 10 PGND GND BST DL 4 2 2 1 U27 LX A C755 S S S S G R187 0R3-0-U-GP R_ILIMPK=402K ohm , Iocp=28/phase 1 1KR2F-3-GP C754 2 SSM5818SLPT-GP C319 SC2D2U10V3ZY-1GP R_OSC=143K ohm , Fsw=300K Hz 2 C582 SC4D7U25V5MX-1GP 2 1 Q11 1 D D D D D 5V_S0 2 EC53 2 C581 SCD1U50V3KX-GP 5 6 7 8 C119 SC1000P50V3JN-GP 5 6 7 8 GND MAX8736AGTL-GP-U R204 C584 SC4D7U25V5MX-1GP 2 1 2 SC4D7U25V5MX-1GP 2 1 1 SC4D7U25V5MX-1GP 2 1 2 9K53R3F-2-GP 10R2J-2-GP GAP-CLOSE-PWR C305 R69 1 R68 THRM VSS_SENSE C153 SC1000P50V3JN-GP SC4D7U25V5MX-1GP 2 1 VRHOT# R72 1 2 10R2J-2-GP 1 CLKEN# MAX8736_GNDS SC4D7U25V5MX-1GP 2 1 IMVPOK C160 SC1000P50V2JN-GP DY G57 1 SC4D7U25V5MX-1GP 2 1 SC4D7U25V5MX-1GP 2 1 1 1 5 6 7 8 5 6 7 8 2 1 2 1 29 41 1 2 1 S S S S G SCD1U10V2MX-3GP 1 2 R140 1 D D D D D DY 8 5V_S0 PSI# G24 GAP-CLOSE-PWR 1 2 R136 AO4430-1-GP 2 2 C279 MAX8736_CSN2 MAX8736_CSP2 CSP2 GAP-CLOSE-PWR R92 1KR2J-1-GP 1 2MAX8736_IMVPOK 24 1 2 7,20 VGATE_PWRGD G15 GAP-CLOSE-PWR R384 2MAX8736_CLKEN# 1 1 3D3V_S0 10KR2J-3-GP 1 2 22 20 CLK_EN# G58 GAP-CLOSE-PWR 23 1 2 MAX8736_PWR 4 CPU_PROCHOT# R82 10R2J-2-GP C159 DY R79 10KR2J-3-GP DY 7 DPRSLPVR GAP-CLOSE-PWR C273 PWM2 28 PWM3 3 AO4430-1-GP 5 PWM2 SHDN# R139 2KR3F-L-GP Q26 DRSKP# 1 3D3V_S0 B 2 CSN1 C258 1 1 PSI# MAX8736_CSP1 DY C201 SC1000P50V2JN-GP 2 5 33 6 CSN2 4 2 1 2 30 VDD DRSKP# CSP1 D0 D1 D2 D3 D4 D5 D6 2 L-D36UH-1-GP 1 34 35 36 37 38 39 40 TRC 1102 SA 1 Q8 2 G17 31 AO4422-1-GP L42 MAX8736_DL1 REF G16 1 32 AO4422-1-GP MAX8736_LX1 DL1 36A/44A ILIMPK GAP-CLOSE-PWR 7,20 DPRSLPVR 2 1 2 1 2 1 21 2 26 C753 D S S S S S G G14 1 36,37,38,40 CPUCORE_ON LX1 16 C750 C222 SCD1U50V3KX-GP D D D D D D CPU_VID[0..6] C MAX8736_DH1 C496 VCC_CORE_S0 S S S S G 5 CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 DH1 27 CCV MAX8736_REF 2 19 SCD22U10V2KX-1GP 1 2MAX8736_TRC 18 R77 1K47R2F-GP 1 C149 25 TIME 17 2 1 1 MAX8736_BST1 BST1 OSC Q25 D D D D D R66 1 15 Q7 R98 0R3-0-U-GP U16 C504 S S S S S G VCC C178 PGND 1025 SA 14 C182 SC2D2U10V3ZY-1GP S S S G G MAX8736_OSC 2 140KR3F-GP MAX8736_TIME 2 100KR2F-L1-GP 1 2 MAX8736_CCV C150 SC680P50V2KX-2GP 2 360KR3F-GP MAX8736_ILIMPK EC46 SCD1U50V3KX-GP SCD22U16V3KX-2-GP 2 C152 SC1U10V3ZY-6GP 1 R48 1 R67 D31 SSM5818SLPT-GP R70 C211 SC4D7U25V5MX-1GP 2 1 1 1 R101 100KR2J-1-GP CPU_VID6 2 1 R103 100KR2J-1-GP CPU_VID5 2 1 1 100KR2J-1-GP CPU_VID4 2 1 100KR2J-1-GP 2 CPU_VID2 100KR2J-1-GP CPU_VID3 2 1 R106 C210 D D D D D D 100KR2J-1-GP CPU_VID1 2 D R111 D D D D D CPU_VID0 R126 R122 R119 DCBATOUT 10R3J-3-GP 100KR2J-1-GP 2 5V_S0 MAX8736_CSN2 2 SCD22U10V3KX-2GP MAX8736_CSP2 <Core Design> A G31 1 2 Wistron Corporation GAP-CLOSE-PWR 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. MAX8552_AGND Title DC-DC VCCCPUCORE Size A3 Document Number Rev 5 4 3 2 SA Pamirs-Discrete Date: Wednesday, December 13, 2006 Sheet 1 35 of 47
- 36. A 51120_V5FILT DCBATOUT C392 SC3900P50V3KX-GP 1 2 4 3 2 1 SKIPSEL TONSEL R523 0R2J-2-GP 2 DY Iomax=11A Qg=9.8nC, Rdson=20~25mohm 51120_DRVH2 51120_LL2 L30 1 1 DY R275 N/A N/A CURRENT MODE D-Cap MODE TONSEL 380k/CH1 590k/CH2 290k/CH1 440k/CH2 220k/CH1 330k/CH2 180k/CH1 280k/CH2 VFB1 N/A not use ADJ. 2 DY COMP DY not use ADJ. not use Swithchr ON EN3,EN5 not use LDO ON Switcher ON 2 51120_COMP2 1 R279 22KR2J-GP C397 SC390P50V3JN-GP DY DY 2 EN1,EN2 Switcher OFF LDO OFF VREG3 on 1 1 C391 SC1000P50V3JN-GP 1 1 N/A G45 1 2 GAP-CLOSE-PWR 51120_AGND DY 2 VFB2 DY Vout=1V*(R1+R2)/R2 51120_AGND 51120_AGND 5V Fixed Output 3.3V Fixed Output R283 13K3R2F-L1-GP 2 C394 SC390P50V3JN-GP 1 2 PWM NEC 220uF ,V size ESR=25mohm Iripple=2.2A 1 DY 1 PWM GAP-CLOSE-PWR 2 DY R272 22KR2J-GP 1 AUTOSKIP /FAULTS OFF GAP-CLOSE-PWR G40 1 2 R281 TC12 30K9R3F-GP ST220U6D3VDM-15GP 0R2J-2-GP 51120_DRVL2 51120_VFB2 AUTOSKIP 2 2 GAP-CLOSE-PWR G43 1 2 2 2 51120_AGND V5FILT GAP-CLOSE-PWR G44 1 2 2 C396 SC33P50V2JN-3GP 1 GAP-CLOSE-PWR G38 1 2 GS 10*10*4 4D7uH 3D3V_PWR DCR=25mohm, Isat=6A 1 U41 AO4422-1-GP 3D3V_S5 GAP-CLOSE-PWR G37 1 2 C365 SCD1U25V3ZY-1GP SC10U25V6KX-1GP 1 2 51120_AGND 2 SKIPSEL GAP-CLOSE-PWR G41 1 2 3D3V_PWR 5 6 7 8 51120_AGND C362 2 2 U40 AO4468-GP 4 3 2 1 1 51120_VREF2 2 0R2J-2-GP SC10U25V6KX-1GP 1 5 6 7 8 R526 Iomax=11A Qg=9.8nC, Rdson=19.6~24mohm FLOAT 1 3D3V Iomax=4A OCP>8A C368 51120_TONSEL 1 2 GAP-CLOSE-PWR G39 1 2 51120_COMP1 VREF2 2 1 2 G42 1 51120_AGND GND 1 1 51120_AGND 2 2N7002DW-1-GP 35,37,38,40 DCBATOUT 4 PM_SLP_S4_1 CPUCORE_ON 74.51120.073 1 1 2 0R0402-PAD 2 0R0402-PAD 4 3 2 1 1 5 3 2 C393 SC3900P50V3KX-GP 2 R541 7K5R3F-GP S S S G G PM_SLP_S4_1# DY D D D D D PM_SLP_S4# 51120_PGOOD1 1 R517 51120_PGOOD2 1 R532 R262 100KR2J-1-GP 6 51120_VFB1 51120_DRVH1 51120_DRVH2 R266 0R2J-2-GP 5V_AUX_S5 U45 51120_DRVL1 S S S G G 51120_CS2 2 16KR3F-GP NEC 220uF ,V size ESR=25mohm Iripple=2.2A DY 2 51120_SKIPSEL 32 31 CS1 CS2 23 18 24 17 5 33 2 PGND1 PGND2 GND GND 1 2 18KR3F-GP 51120_AGND 51120_CS1 R540 0R2J-2-GP D D D D D 1 R513 17,20,28,31,37,38 27 14 TC13 ST220U6D3VDM-15GP 51120_DRVL1 51120_DRVL2 VREF2 8/10 51120_AGND 25 16 DRVH1 DRVH2 51120_V5FILT 1 30 11 DRVL1 DRVL2 51120_AGND DY 2 PGOOD1 PGOOD2 C400 SC1000P50V3JN-GP TPS51120RHBR-GPU1 1 R514 51120_LL2 51120_LL1 15 26 VO1 VO2 4 R539 30KR2F-GP R520 100KR2J-1-GP LL2 LL1 VFB2 VFB1 1 8 DY U44 COMP2 COMP1 V5FILT VIN 7 2 20 22 28 13 VBST1 VBST2 19 21 VREG3 VREG5 6 3 51120_VREF2 1 3D3V_S0 EN1 EN2 EN3 EN5 51120_VFB2 51120_VFB1 Iomax=11A Qg=9.8nC, Rdson=19.6~24mohm 2 0R3-0-U-GP 1 1 29 12 10 9 5V_S3 3D3V_PWR 51120_V5FILT 0R3-0-U-GP 1 R284 2 1 2 R542 0R3-0-U-GP 51120_COMP1 1 R269 2 1 2 2 0R0402-PAD 51120_EN1 2 0R0402-PAD 51120_EN2 TP31 TPAD28 1 TP32 TPAD28 1 C690 SC33P50V2JN-3GP 2 S S S S G 1 R524 1 R527 SC10U10V5ZY-1GP PWR_S5_EN_1 DY 0R3-0-U-GP L31 IND-3D3UH-42-GP-U D D D D D SC10U10V5ZY-1GP PM_SLP_S4_1# R277 51120_COMP2 1 U38 AO4422-1-GP 5V Iomax=5A OCP>10A 2 1 51120_V5FILT C382 C385 3D3V_AUX_S5 0707 Change 5V_S5 to 5V_S3 0718 Change 3D3V_AUX_S5 to 3D3V_S5 1 5 6 7 8 2 51120_VBST1 0R3-0-U-GP 5V_AUX_S5 C383 SCD1U25V3ZY-1GP 2 51120_VBST1_1 1 2 SCD1U25V3ZY-1GP 51120_DRVH1 51120_LL1 2 2 1 51120_AGND R259 GS 10*10*4 4D7uH 5V_S3 DCR=25mohm, Isat=6A 4 3 2 1 DCBATOUT C363 SCD1U25V3ZY-1GP S S S S G 51120_AGND 2 51120_VBST2_1 R263 1 2 51120_VBST2 0R3-0-U-GP SCD1U25V3ZY-1GP C389 51120_LL1 1 Iomax=11A Qg=9.8nC, Rdson=20~25mohm S 8/10 C388 51120_LL2 1 C361 SC10U25V6KX-1GP 2 U39 AO4468-GP 2 5 6 7 8 51120_AGND G 22,34 PWR_S5_EN# D D D D D SC1U10V3ZY-6GP 1 1 C379 1 Q15 2N7002-11-GP 1 2 5D1R3F-GP 2 R250 5V_AUX_S5 D 1 PWR_S5_EN_1 C401 SC1000P50V3JN-GP For TPS51120, Vout=5V 1. If you use 2. If you use 3. If you use Vout=3.3V 1. If you use 2. If you use 3. If you use a 6.8uH inductor, the minimum ESR is 70m ohm. a 4.7uH inductor, the minimum ESR is 48m ohm. a 3.3uH inductor, the minimum ESR is 34m ohm. <Core Design> Wistron Corporation a 4.7uH inductor, the minimum ESR is 51m ohm. a 3.3uH inductor, the minimum ESR is 36m ohm. a 2.5uH inductor, the minimum ESR is 27m ohm. 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title DY 51120_AGND 5V_S3/3D3V_S5 Size A3 Document Number Date: Friday, December 08, 2006 Rev SA Pamirs-Discrete Sheet 36 of 47
- 37. Iocp=7.0* 2 = 14A Rds,on=17m ohm Vcs1=Iocp*Rds,on=238mV VILIM=Vcs1/0.1=2.38V Iocp=7.0*2 = 14A Rds,on=17m ohm Vcs2=Iocp*Rds,on=28mV VILIM2=Vcs2/0.1=2.38V 5V_MAX8743_VCC 5V_S5 R215 1 DUMMY-R2 2 5V_S3 R217 1 2 0R3-0-U-GP 5V_MAX8743_VCC 1 L26 1 2 1 18 17 20 CS1 CS2 OUT2 15 1 2 2 SC10U25V6KX-1GP GAP-CLOSE-PWR L27 1 2 7 OVP 8 MAX8743EEI-1-GP 74.08743.A79 Panasonic 220uF/2V ESR=15m ohm Iripple=2.7 A 10KR2F-2-GP R205 Iomax=11A Qg=9.8nC, Rdson=19.6~24mohm 23 1 C589 SCD47U10V3KX-3GP MAX8743_PGOOD 1 C590 SKIP# 1 D D D D 1 2 3 4 6 SCD1U25V3ZY-1GP 1 PGOOD MAX8743_ON2 C336 2 TON REF SCD1U25V3ZY-1GP R207 100KR3F-GP MAX8743_FB2 2 2 1 5V_MAX8743_VCC 1 Vout=Vfb*(1+(R1/R2)) Where Vfb=1.0V,R2=10Kohm 1 460 355 255 170 CPUCORE_ON 35,36,38,40 R211 PM_SLP_S3#1 2 220KR2J-L2-GP DY R214 PM_SLP_S4#1 2 MAX8743_SKIP# 220KR2J-L2-GP <Core Design> 1 Frequency (Out2)KHz 2 0R0402-PAD R441 Wistron Corporation R216 C344 0R2J-2-GP SC1000P50V3JN-GP 2 Frequency (Out1)KHz C591 DY SCD1U10V2MX-3GP 2 2 DY SCD1U10V2MX-3GP C346 1 1 5K1R2-GP 1 0205 R440 DUMMY-R2 1 MAX8743_ON2 5K1R2-GP DY Voutsetting=1.0511V DUMMY-R2 2 2 2 R433 1 R434 0R2J-2-GP 2 1 R210 MAX8743_ON1 2 PM_SLP_S3# 2 2 1 5 10 1 MAX8743_TON MAX8743_VREF 2 12 2 G35 DY TC10 SE220U2VDM-8GP 2 ON2 2 G36 1 5 6 7 8 ON1 U36 AO4712-GP 14 11 2 G33 GAP-CLOSE-PWR 4 3 2 1 FB2 GND FB1 S S S G OUT1 MAX8743_ON1 Iomax=11A Qg=9.8nC, Rdson=19.6~24mohm 2 20,22,28,31,34,38,40 345 235 2 MAX8743_DH2 MAX8743_LX2 MAX8743_DL2 2 G32 1 16 2 SCD1U25V3ZY-1GP DY MAX8743_VREF 1 R213 OPEN VCC 5 6 7 8 1 2 4 3 2 1 DH2 LX2 DL2 SCD1U25V3ZY-1GP 1 1 2 MAX8743_ILIM2 21 4 VDD V+ VCC 22 2 SC1U10V3ZY-6GP 1 2 1 DH1 LX1 DL1 G34 1 NEC GAP-CLOSE-PWR Irms=7.5A(Isat=10.4A) 1 DCR=13mohm GAP-CLOSE-PWR 12*12*5.5 1 BST1 26 27 24 1D05V_S0 GAP-CLOSE-PWR MAX8743_FB1 PM_SLP_S4# 620 485 C338 SCD1U25V3ZY-1GP 1D05V_S0/5A OCP>=10A C356 SC10U25V6KX-1GP 1D05V_PWR 8 7 6 5 25 28 220uF/2D5V ESR=15m ohm Iripple=2.7 A 17,20,28,31,36,38 AGND REF U37 AO4468-GP MAX8743_BST2R DY Ton 1 1 1 1 2 8 7 6 5 D D D D S S S G 2 19 MAX8743_BST1R U34 AO4712-GP 1 2 2 1 SCD1U16V2ZY-2GP SE220U2D5VDM-3GP 2 1 BST2 R456 0R3-0-U-GP 13 1 R225 9K53R2F-GP Voutsetting=1.820V EC77 S S S G 1 ILIM1 ILIM2 MAX8743_DH1 MAX8743_LX1 MAX8743_DL1 C339 R224 8K2R3F-GP Panasonic 2 3 MAX8743_ILIM1 UVP R208 90K9R3F-GP D D D D GAP-CLOSE-PWR U29 9 2 EC113 TC11 C352 SCD1U25V3ZY-1GP Iomax=11A Qg=9.8nC, Rdson=20~25mohm 2 GAP-CLOSE-PWR G68 1 2 R432 90K9R3F-GP 2 0R3-0-U-GP Iomax=11A Qg=9.8nC, Rdson=20~25mohm S S S G NEC Irms=7.5A(Isat=10.4A) DCR=13mohm 12*12*5.5 1102 SA GAP-CLOSE-PWR G61 1 2 R221 1 1 2 3 4 GAP-CLOSE-PWR G64 1 2 U33 AO4468-GP C358 R212 C350 D D D D SCD1U25V3ZY-1GP 2 SC10U25V6KX-1GP GAP-CLOSE-PWR G65 1 2 R429 1 EC72 2 1 C359 GAP-CLOSE-PWR G67 1 2 MAX8743_BST1 GAP-CLOSE-PWR G66 1 2 2 MAX8743_BST2 MAX8743_VCC BAW56-3-GP 2 1 DCBATOUT 2 1 1 GAP-CLOSE-PWR G62 1 2 C349 SC1U25V5ZY-4GP DCBATOUT 2 G63 C353 SCD1U10V2MX-3GP 1D8V_PWR 2 1D8V_S3 2 3 1 D17 SC1U10V3ZY-6GP R218 2 2 SCD1U10V2MX-3GP C341 5V_MAX8743_VCC 1D8V / 7.0A OCP>=14A 1 1 DCBATOUT C340 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. DY Title 1D8V_S3/1D05V_S0 Size A3 Document Number Rev SA Pamirs-Discrete Date: Monday, December 18, 2006 Sheet 37 of 47
- 38. B C D 1 2 1D8V_S3 1 5V_S3 E 1 A C248 SC10U10V5ZY-1GP 4 4 C250 SC10U10V5ZY-1GP 2 2 C260 SC1U10V3ZY-6GP DY VOUT VOUT 3 4 SA 1010 C268 GND 9K1R3F-1-GP 2 2 FB R130 5912_FB_1 2 1 APL5912-KAC-GP 74.05912.A71 1 1 SO-8-P OCP=6A 2 GAP-CLOSE-PWR G23 1 2 1D5V_LDO 1D5V_S0 GAP-CLOSE-PWR 1 EN 5 9 TC18 ST100U4VBM-L-GP C218 SC22U10V6ZY-2GP 2 R104 G22 Vo(cal.)=1.5V VIN VIN SCD01U16V2KX-3GP 2 1 2 8 0R0402-PAD POK 1 1 0R2J-2-GP 1 PM_SLP_S3# DY 7 VCNTL 35,36,37,40 CPUCORE_ON 1 6 U18 R97 2 DY Trace Length=3cm Trace Width=5mils KEMET NTD:5.615 Trace Resistance>80mohm 100uF, 4V, B2 Size Iripple=1.1A, ESR=70mohm 2 R123 10KR3F-L-GP Vo=0.8*(1+(R1/R2)) 3 1 C172 SC1U10V3ZY-6GP 1 2 2 1D8V_S3 1 5V_S3 C205 SC10U10V5ZY-1GP C179 SC10U10V5ZY-1GP 2 3 1D25V_S0 Iomax=2A R152 0R2J-2-GP 2 8 0R0402-PAD POK VOUT VOUT EN VIN VIN 3 4 FB 2 DDR_VREF_S0 2 1 1 1 1 PM_SLP_S3# R418 R419 2 0R0402-PAD 2 0R0402-PAD 10 9 8 7 6 VIN VDDQSNS S5 VLDOIN GND VTT S3 PGND VTTREF VTTSNS 2 2 GAP-CLOSE-PWR G28 1 2 GAP-CLOSE-PWR C254 SC22U10V6ZY-2GP DY Trace Length=3cm Trace Width=5mils KEMET NTD:5.615 Trace Resistance>80mohm 100uF, 4V, B2 Size Iripple=1.1A, ESR=70mohm Vo=0.8*(1+(R1/R2)) 1 2 3 4 5 GAP-CLOSE-PWR <Core Design> 1 TPS51100DGQR-GP Wistron Corporation C283 SC10U10V5ZY-1GP SC10U10V5ZY-1GP 1 2 74.51100.079 2 1 11 DY 1 C285 2 1 C280 SCD1U16V2ZY-2GP 2 DDR_VREF_S3 TC16 ST100U4VBM-L-GP 1D25V_S0 GAP-CLOSE-PWR G27 1 2 GND 20,22,27,28,31,34,37,40 1 1 PM_SLP_S4# R153 10KR3F-L-GP G29 2 2 C564 SC1U10V3ZY-6GP C554 SC10U10V5ZY-1GP U24 17,20,28,31,36,37 R151 5K76R3F-GP SO-8-P 1 0D9V_PWR APL5912-KAC-GP 74.05912.A71 5912_FB 2 OCP=6A 2 GAP-CLOSE-PWR G25 1 2 1D25V_LDO C223 2 1D8V_S3 1 5V_S3 GND 0D9V Iomax=1A 1 1 1 G26 Vo(cal.)=1.26V 5 9 1 PM_SLP_S3# 7 2 35,36,37,40 CPUCORE_ON 1 1 DY 2 SCD01U16V2KX-3GP 2 1 U22 R150 VCNTL 2 6 DY 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. C282 SC10U10V5ZY-1GP Title 0D9V_LDO/1D25V_LDO/1D5V Size A3 Document Number Pamirs-Discrete Date: Tuesday, November 07, 2006 A B C D Sheet E 38 of Rev SA 47
- 39. A B C D24 C457 1 2 2 SCD1U25V3ZY-1GP 1 2 R349 15K4R2F-GP 3D3V_AUX_S5 1 1 BAV99W-1-GP DCBATOUT Rx1 2 AD+ 31 AD<=17V, disable charger function R350 100KR2F-L1-GP R45 U4 1 8 7 6 5 R394 100KR2F-L1-GP S S S G AD+_TO_SYS 1 2 3 4 1 2 1 2 3 4 D01R2512F-4-GP MAX1909_PDL AO4407-1-GP U5 S S S G D D D D 8 7 6 5 BT+ 4 AO4407-1-GP 1 4 D D D D E DY 3 AIRLINE_VOLT D 1214 AD+ > 13V ACOK is H G6 2 2 G5 GAP-CLOSE-PWR GAP-CLOSE-PWR MAX1909_DLO PGND S 17 16 15 2 1 C466 SC10U25V0KX-3GP 1 2 1 2 2 2 G19 GAP-CLOSE-PWR G18 GAP-CLOSE-PWR 18 CSIN BATT GND 3 29 CSIP 5 2 D01R2512F-4-GP 4 3 2 1 BT_TH 1 1 19 PGND ACOK R121 49K9R2F-L-GP BT+ R88 2 CHG_PWR-3 1 6 U12 SI4800BDY-T1 1 DY L38 1 AC_OK 2 CLS SCD1U25V3ZY-1GP D 1 2 31K6R2F-GP 5 6 7 8 IINP MAX1909_IINP R382 1 IND-15UH-50-GP EC112 ACIN 8 CHG_PWR-2 C177 SC10U25V0KX-3GP 2 PKPRES EC4 1 20 Rx2 1102 SA C220 SC1U10V3ZY-6GP D D D D 3 MAX1909_CLS 9 MAX1909_DLOV SCD1U25V3ZY-1GP 2 DLO VCTL ICTL MODE C470 SC10U25V0KX-3GP 1 2 MAX1909_DHI Near MAX1909 Pin 21 C165 SC10U25V0KX-3GP 2 1 23 5 6 7 8 21 2 DLOV 11 10 7 C113 SCD1U25V3ZY-1GP 4 3 2 1 U13 SI4431BDY-E3-GP G S S S 2 2 MAX1909_ACIN MAX1909_LDO G 4CELL# R134 33R2J-2-GP 1 1 1 R109 49K9R2F-L-GP DY Q4 2N7002-11-GP 31 2 SC1U10V3ZY-6GP 2 MAX1909_VCTL MAX1909_ICTL MAX1909_MODE 3 DY C230 1 1 1 2 22 28 2 DHI 2 DHIV PDL LDO PDS SRC DCIN 1122 R118 0R2J-2-GP SCD1U25V3ZY-1GP 1 25 CSSN CSSP 1 2 1 1 2 MAX1909_PDS 27 AD+_TO_SYS 24 MAX1909_DC_IN 1 Near MAX8725 Pin 2 C236 D D D D D R383 100KR2F-L1-GP DY U21 MAX1909_LDO S S S G G R110 0R2J-2-GP C510 SCD1U25V3ZY-1GP MAX1909_LDO DCBATOUT AD+_TO_SYS MAX1909_DHIV 2/24 Close to MAX1909 pin 24 K RB521S-30-2-GP 26 A 2 2 SCD1U25V3ZY-1GP D32 AD+ C239 1 2 C233 C240 SCD1U25V3ZY-1GP SCD1U25V3ZY-1GP 1 2 R393 19K1R2F-GP 1 AC_IN Threshold 2.089V Max. AC_IN > 2.089V --> AC DETECT 1 1 2 2 DY C443 SCD1U25V3ZY-1GP MAX8725_CSIP MAX8725_CSIN REF BT+SENSE 46 4 C214 SCD01U16V2KX-3GP MAX8725ETI-GP-U 3D3V_AUX_S5 1 1 ISOURCE_MAX = (0.075/Rx1)*(VCLS/VREF) = 4.32A So,Constant Power=18.5*4.32=80W (90%) 2 R125 100KR2J-1-GP 2 2 MAX1909_CLS 1 2 C219 SC1U10V3ZY-6GP V_REF :4.2235V (<500uA) R133 49K9R2F-L-GP 1 1 2 1 2 2 C208 C206 SCD01U16V2KX-3GP 2 1 2 1 CCV CCI CCS MAX1909_REF 2 1 R108 15KR2F-GP SCD1U25V3ZY-1GP 2 C181 13 12 14 R124 10KR2J-3-GP SA 1003 GAP-CLOSE-PWR Detect adaptor input current MAX1909_CCV MAX1909_CCI MAX1909_CCS 2 SCD1U25V3ZY-1GP 1 AD_IA 1 G59 31 R135 64K9R2F-1-GP BT_TH 2 31,46 G60 1 2 GAP-CLOSE-PWR 1 KBC_3D3V_AUX R396 100KR2J-1-GP 2 MAX1909_REF 1 31 AC_IN# D R392 100KR2F-L1-GP 2 Q27 2N7002-11-GP 3 U61 2 1 3 2 1 AC_OK S 1 R385 86K6R3F-GP R388 43K2R2F-L-GP U60 2N7002DW-1-GP 2 2 1 R102 100KR2F-L1-GP 31 CHG_4CELL DY 2 DY 2 CHG_ON# 1 R391 3K65R3F-GP SET CHG OFF : BAT_CHG_I = (0.075/Rx2)*(VICTL/3.6) LI BAT : CHG_I_SET = H(6cell), Charge current = 3.0A CHG_I_SET = L(12cell), Charge current = 5.0A 1 <Core Design> 4 5 4 5 6 2N7002DW-1-GP 6 31 G 1 1 MAX1909_ICTL Wistron Corporation Pre-Charge : MAX8725 : CHG_I_PRE_SEL = H, Pre-Charge current = 300mA 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CHARGER MAX8725ETI 31 CHG_I_PRE_SEL 31 Size C CHG_I_SEL Date: A B C D Document Number Rev SA Pamirs-Discrete Sheet Tuesday, December 19, 2006 E 39 of 47
- 40. A B C D E DCBATOUT_SC411 VGA_CORE_PWR VGA_CORE_S0 5V_S5 1 G4 1 1 2 2 DY SCD1U50V3ZY-GP 2 SE220U2D5VDM-3GP 2 2 SE220U2D5VDM-3GP 1 2 D 1 2 GAP-CLOSE-PWR VGA_CORE_PWR 1 Q2 R357 2N7002-9-GP 1 1 2 10KR2F-2-GP G GPIO_PWRCNTL 42 G82 1 1 2 GAP-CLOSE-PWR R54 200KR2F-L-GP G85 1 2 2 SCD01U16V2KX-3GP 2 C471 3 2 GAP-CLOSE-PWR 1 S Low(0V)=>Vo=1.01V High(3.3V)=>Vo=1.11V VGA_CORE_S0 G83 3 15KR3F-GP Vout Setting: 0.5V/Rlow=(Vout-0.5V)/Rhigh 2 GAP-CLOSE-PWR C468 G7 R44 75KR3F-GP R41 TC1 1 R356 15K4R3-GP 1 1 1 C87 TC2 2 GND VSSA DL 2 GAP-CLOSE-PWR G9 SC411_VFB SC411_DL 1 1 1 7 U10 C64 SC1U10V3ZY-6GP 17 2 SC411MLTRT-GP 3 PGND FB 8 2 GAP-CLOSE-PWR VGA_CORE_PWR 1 2 IND-1D5UH-23-GP R39 2 SC411_LX 16K2R2F-GP SC411_LX_L 1 VGA_CORE_PWR SC411_DL 6 3 SC411_LX AO4430-1-GP 10 ILIM 4 G2 G1 SC411_LX TON VGA_CORE_PWR 1 VOUT SC411_VFB 11 2 1 2 LX 2 2 1 16 12 1 GAP-CLOSE-PWR Vosetting=1.1 S S S G SC411_TON DH NC#5 NC#14 G3 SC4D7U25V5MX-1GP L36 SCD1U16V2KX-3GP D D D D SCD1U25V3ZY-1GP DCBATOUT_SC411 R51 1 2 C109 1MR2F-GP SC1KP50V2KX-1GP 5 14 SC411_DH 2 GAP-CLOSE-PWR C124 SC411_DH SC10P50V2JN-4GP 2 1 9 VDDP C467 SC4D7U25V5MX-1GP 5 6 7 8 4 3 2 1 5V_S5 13 BST C125 5 6 7 8 2 EN/PSV R49 C105 2SC411_LX 4 3 2 1 15 PGD 2SC411_BST 1 0R2J-2-GP 1 21,23,34 PM_SLP_S3# 4 1KR2F-3-GP SC411_PSV 2 1 R358 1 SC411_BST_L 1 VCCA U8 1 2 S S S G AO4468-GP 2 1 D8 CH521S-30-GP-U1 C463 SC1U10V3ZY-6GP 2 U14 1218 D D D D 1 2 C123 SC_VCC 4 1 5V_S5 SCD1U25V3ZY-1GP R354 10R2F-L-GP 2 GAP-CLOSE-PWR G84 1 2 GAP-CLOSE-PWR G87 1 2 GAP-CLOSE-PWR G86 1 2 GAP-CLOSE-PWR 2 2 DCBATOUT_SC411 DCBATOUT G13 1 1D2V_S0 Iomax=3A 2D5V_S0 Iomax=300mA G56 1 2 R314 0R0402-PAD 8 2 1 1 GND R316 1K91R2F-1-GP Vout=1.8V*R2/(R1+R2) GAP-CLOSE-PWR VOUT C449 SC1U10V3ZY-6GP SCD033U16V2KX-GP SO-8-P 1 1 VIN 1 1D2V_S0 2 GND 3 GAP-CLOSE-PWR G53 1 2 2 1KR2F-3-GP U57 GAP-CLOSE-PWR G54 1 2 APL5308-25AC-1GPU GAP-CLOSE-PWR C448 SC10U10V5ZY-1GP <Core Design> 1 TC14 ST220U2D5VBM-LGP Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. C439 1 2 2 1 1D2V_PWR 1 R317 1 APL5913-KAC-1-GP Vo(cal.)=1.200V 3 4 FB 1 6 5 9 VOUT VOUT EN VIN VIN C435 SC10U10V5ZY-1GP GAP-CLOSE-PWR G10 1 2 2D5V_S0 3D3V_S0 2 POK C436 SC1U10V3ZY-6GP GAP-CLOSE-PWR G11 1 2 2 2 7 1D8V_S0 2 2 0R2J-2-GP 1 GAP-CLOSE-PWR G55 1 2 2 PM_SLP_S3# 1 R315 VCNTL DY 35,36,37,38 CPUCORE_ON 2 1 5V_S5 U54 Title Trace Length=1cm (500mils) KEMET NTD:5.615 Trace Width=8mils 100uF, 4V, B2 Size Trace Resistance>25mohm Iripple=1.1A, ESR=70mohm Size A3 VGA CORE 1V Document Number Rev B C D SA Pamirs-Discrete Date: Monday, December 18, 2006 A 2 GAP-CLOSE-PWR G12 1 2 Sheet E 40 of 47
- 41. PEG_RXP12 PEG_RXN12 9 9 PEG_RXP13 PEG_RXN13 9 9 A 9 9 PEG_TXN13 PEG_TXP13 PEG_RXP14 PEG_RXN14 9 9 9 9 PEG_TXP14 PEG_TXN14 PEG_RXP15 PEG_RXN15 9 9 PEG_TXP15 PEG_TXN15 C169 1 1 C168 C175 1 1 C174 C167 1 1 C166 NV_PLLAVDD PEX_TX12 PEX_TX12# C59 PEX_PLLGND C30 NB8M-GS-GP 1 SCD1U10V2KX-5GP 2 1 SCD1U10V2KX-5GP 2 SC1U10V2KX-GP 1 SC1U6D3V2ZY-GP 1 2 C68 3D3V_S0 C15 DY R362 1 2 1 R395 A16 17,29 SPDIF SPDIF C209 1 2 2 2KR2-GP R127 SCD01U16V2KX-3GP 75R2J-1-GP DY DY SC1U10V2KX-GP 1 SC4D7U6D3V3KX-GP 1 1 SCD1U16V2ZY-2GP 2 2 1D2V_S0 NB8M-GS-GP R93 18KR2J-GP L15 C472 1 2 BLM15AG221SN-GP C107 SC4D7U6D3V3KX-GP reserve for NB86 1D2V_S0 L14 1 2 BLM15AG221SN-GP C96 FB_VREF C101 place near GPU A <Core Design> 3D3V_S0 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. D39 HDMI_SPDIF R86 9K09R2F-GP SCD1U16V2ZY-2GP 2 For NB86 FBA_PLLAVDD 3D3V_S0 For NB86 SCD1U16V2ZY-2GP 1 2 1 TPAD30 place near balls 0R2J-2-GP DY HDMI_SPDIF SCD1U16V2ZY-2GP 1 2 1 2 1 D13 FBA_PLLGND TPAD30 TP38 1 2 C54 C446 COIL-10NH-GP SC4D7U6D3V3KX-GP SCD01U16V2KX-3GP 44,45 VRAM_VREF SCD1U10V2KX-5GP AA6 D12 E12 F12 C13 SCD1U16V2ZY-2GP 2 SC1U6D3V2ZY-GP 2 SC1U10V3KX-3GP 2 1 SC1U10V2KX-GP 2 1 SC1U6D3V2ZY-GP FBA_PLLAVDD PEX_RX14 PEX_RX14# NC#D12 NC#E12 NC#F12 NC#C13 TP2 D14 L7 PEX_TX14 PEX_TX14# PEX_RX15 PEX_RX15# M23 M24 FBA_PLLVDD 1D2V_S0 PEX_PLLADVDD 1 SC1U10V3ZY-6GP 2 40D2R2F-GP C74 SCD01U16V2KX-3GP Y6 AA5 SCD1U16V2ZY-2GP 1 1 SCD1U10V2KX-5GP SCD1U10V2KX-5GP 2 1 1 2 1 2 SC1U10V3KX-3GP 2 1 2 2 1 2 FBA_REFCLK FBA_REFCLK# SCD1U10V2KX-5GP PEX_PLLAVDD PEX_PLLDVDD R84 1 1 place near GPU PEX_RX12 PEX_RX12# PEX_TX15 PEX_TX15# K22 VGA_CORE_S0 place near balls PEX_RX11 PEX_RX11# PEX_RX13 PEX_RX13# FBA_DEBUG R50 1 E13 H22 SCD01U16V2KX-3GP N9 PEX_TX11 PEX_TX11# PEX_TX13 PEX_TX13# FBCAL_PU_GND FBCAL_TERM_GND B 1D8V_S0 2 40D2R2F-GP R359 2 30R2J-1-GP 1 PEX_RX10 PEX_RX10# 45 45 45 45 C114 SC10U10V5KX-2GP 9 9 PEG_TXP12 PEG_TXN12 C158 1 1 C157 PEX_TX10 PEX_TX10# C80 1 1 9 9 PEG_TXN11 PEG_TXP11 D15 C751 44 44 45 45 2 9 9 C156 1 1 C155 FBCAL_PD_VDDQ FBADQS_RN0 FBADQS_RN1 FBADQS_RN2 FBADQS_RN3 FBADQS_RN4 FBADQS_RN5 FBADQS_RN6 FBADQS_RN7 2 PEG_RXP11 PEG_RXN11 C70 44 44 44 44 1 9 9 PEG_TXP10 PEG_TXN10 FBA_CLKP0 FBA_CLKN0 FBA_CLKP1 FBA_CLKN1 2 9 9 PEX_RX9 PEX_RX9# A22 E22 F21 B21 V26 W23 V23 W27 L24 K23 M22 N22 SCD01U16V2KX-3GP PEG_RXP10 PEG_RXN10 C142 1 1 C146 FBADQSN0 FBADQSN1 FBADQSN2 FBADQSN3 FBADQSN4 FBADQSN5 FBADQSN6 FBADQSN7 FBA_CLK0 FBA_CLK0# FBA_CLK1 FBA_CLK1# 1 9 9 PEG_TXP9 PEG_TXN9 PEX_TX9 PEX_TX9# J12 F13 J13 F14 J15 J16 C99 D FBA_RST 44,45 FBA_A7 44,45 FBA_A10 44,45 FBA_CKE 44,45 FBA_A0 44,45 FBA_A9 44,45 FBA_A6 44,45 FBA_A2 45 FBA_A8 44,45 FBA_A3 45 FBA_A1 44,45 place near balls VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 C131 C140 C 2 9 9 C128 1 1 C141 PEX_RX8 PEX_RX8# VDD_LP VDD_LP VDD_LP VDD_LP 1 PEG_RXP9 PEG_RXN9 PEX_TX8 PEX_TX8# C752 FBA_A4 45 FBA_RAS# 44,45 FBA_A5 45 FBA_BA1 44,45 FBB_A2 44 FBB_A4 44 FBB_A3 44 FBA_CS1#/BA2 44,45 FBA_CS0# 44,45 FBA_A11 44,45 FBA_CAS# 44,45 FBA_WE# 44,45 FBA_BA0 44,45 FBB_A5 44 FBADQS_WP0 FBADQS_WP1 FBADQS_WP2 FBADQS_WP3 FBADQS_WP4 FBADQS_WP5 FBADQS_WP6 FBADQS_WP7 2 9 9 PEG_TXP8 PEG_TXN8 PEX_RX7 PEX_RX7# B22 D22 E21 C21 V25 W24 U24 W26 C106 C118 G27 D25 F26 F25 G25 J25 J27 M26 C27 C25 D24 N27 G24 J26 M27 C26 M25 D26 D27 K26 K25 K24 F27 K27 G26 B27 N24 FBADQM0 FBADQM1 FBADQM2 FBADQM3 FBADQM4 FBADQM5 FBADQM6 FBADQM7 FBADQSP0 FBADQSP1 FBADQSP2 FBADQSP3 FBADQSP4 FBADQSP5 FBADQSP6 FBADQSP7 44 44 44 44 45 45 45 3D3V_S0 45 C130 FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 2 1 9 9 C117 1 1 C122 W9 W10 W11 W12 D21 F22 F20 A21 V27 W22 V22 V24 FBADQM0 FBADQM1 FBADQM2 FBADQM3 FBADQM4 FBADQM5 FBADQM6 FBADQM7 2 PEG_RXP8 PEG_RXN8 PEX_TX7 PEX_TX7# C212 2 B 9 9 PEG_TXP7 PEG_TXN7 PEX_RX6 PEX_RX6# 1 9 9 C102 1 1 C108 PEX_TX6 PEX_TX6# C95 44 44 44 44 45 45 45 45 SC1U10V2KX-GP PEG_RXP7 PEG_RXN7 1 1 W13 M14 T14 L15 M15 T15 U15 W15 L16 M16 T16 U16 W16 M17 N17 R17 T17 1 9 9 PEG_TXP6 PEG_TXN6 C97 PEX_RX5 PEX_RX5# VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD C104 2 9 9 C92 PEX_TX5 PEX_TX5# 1214 1 PEG_RXP6 PEG_RXN6 C89 PEX_RX4 PEX_RX4# 45 FBAD[48..63] 1214 C148 F17 F19 J19 M19 T19 J22 L22 P22 U22 Y22 2 9 9 PEG_TXP5 PEG_TXN5 1 1 C83 SCD1U10V2KX-5GP 9 9 C85 C88 SC1U10V2KX-GP 2 PEG_RXP5 PEG_RXN5 C81 PEX_TX4 PEX_TX4# C79 C94 C100 1 9 9 PEG_TXP4 PEG_TXN4 1 1 FBAD[32..47] 1D8V_S0 place below GPU FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ 2 9 9 C72 PEX_RX3 PEX_RX3# R9 T9 J10 J11 M11 N11 R11 T11 L12 M12 T12 U12 L13 M13 T13 U13 C56 1 PEG_RXP4 PEG_RXN4 C67 PEX_TX3 PEX_TX3# VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD C111 SC10U10V5KX-2GP 9 9 PEG_TXP3 PEG_TXN3 1 1 PEX_RX2 PEX_RX2# J9 M9 2 9 9 C63 PEX_TX2 PEX_TX2# 45 C115 VDD VDD SCD1U10V2KX-5GP PEG_RXP3 PEG_RXN3 C62 PEX_RX1 PEX_RX1# C84 VGA_CORE_S0 1 9 9 PEG_TXP2 PEG_TXN2 1 1 C91 place near balls 2 9 9 C55 PEX_TX1 PEX_TX1# SCD1U16V2ZY-2GP C PEG_RXP2 PEG_RXN2 C51 PEX_RX0 PEX_RX0# 1 9 9 PEG_TXP1 PEG_TXN1 1 1 SC10U10V5KX-2GP 9 9 C45 C75 2 PEG_RXP1 PEG_RXN1 C41 PEX_TX0 PEX_TX0# AB13 AB16 AC16 AB17 AC17 AB18 AB19 AC19 AC20 1 9 9 PEG_TXP0 PEG_TXN0 1 1 PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ C129 2 9 9 C39 PEX_REFCLK PEX_REFCLK# 1 PEG_RXP0 PEG_RXN0 PEX_TSTCLK_OUT PEX_TSTCLK_OUT# 2 9 9 AE3 AE4 SCD1U10V2KX-5GP RXP0 2 AD5 RXN0 2 AD6 SCD1U10V2KX-5GP AF1 AG2 SCD1U10V2KX-5GP 2 RXP1 AE6 2 RXN1 AE7 SCD1U10V2KX-5GP AG3 AG4 SCD1U10V2KX-5GP 2 RXP2 AD7 2 RXN2 AC7 SCD1U10V2KX-5GP AF4 AF5 SCD1U10V2KX-5GP 2 RXP3 AE9 2 RXN3 AE10 SCD1U10V2KX-5GP AG6 AG7 SCD1U10V2KX-5GP 2 RXP4 AD10 RXN4 2 AC10 SCD1U10V2KX-5GP AF7 AF8 SCD1U10V2KX-5GP 2 RXP5 AE12 2 RXN5 AE13 SCD1U10V2KX-5GP AG9 AG10 SCD1U10V2KX-5GP 2 RXP6 AD13 2 RXN6 AC13 SCD1U10V2KX-5GP AF10 AF11 SCD1U10V2KX-5GP 2 RXP7 AC15 2 RXN7 AD15 SCD1U10V2KX-5GP AG12 AG13 SCD1U10V2KX-5GP 2 RXP8 AE15 2 RXN8 AE16 SCD1U10V2KX-5GP AG15 AG16 SCD1U10V2KX-5GP 2 RXP9 AC18 2 RXN9 AD18 SCD1U10V2KX-5GP AF16 AF17 SCD1U10V2KX-5GP 2 RXP10 AE18 2 RXN10 AE19 SCD1U10V2KX-5GP AG18 AG19 SCD1U10V2KX-5GP 2 RXP11 AC21 2 RXN11 AD21 SCD1U10V2KX-5GP AF19 AF20 SCD1U10V2KX-5GP 2 RXP12 AE21 2 RXN12 AE22 SCD1U10V2KX-5GP AG21 AG22 SCD1U10V2KX-5GP 2 RXP13 AD22 2 RXN13 AD23 SCD1U10V2KX-5GP AF22 AF23 SCD1U10V2KX-5GP 2 RXP14 AF25 2 RXN14 AE25 SCD1U10V2KX-5GP AG24 AG25 SCD1U10V2KX-5GP AE24 2 RXP15 2 RXN15 AD24 SCD1U10V2KX-5GP AG26 AF27 PEX_RST# 1 3 PEG_REFCLKP 3 PEG_REFCLKN AC6 AF13 AF14 2 K 1N4148W-1-GP 1 A PLT_RST1# 2 8,31,33,34 1 D25 2 2 10KR2J-3-GP C23 SC10U10V5KX-2GP SC10U10V5KX-2GP 1 R348 PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ 1 E15 F15 F16 J17 J18 L19 N19 R19 U19 W19 FBVTT FBVTT FBVTT FBVTT FBVTT FBVTT FBVTT FBVTT FBVTT FBVTT SCD1U16V2ZY-2GP FBAD[16..31] place near balls AA4 AB5 AB6 AB7 AB8 AB9 AC9 AC11 AB12 AC12 2 FBAD0 FBAD1 FBAD2 FBAD3 FBAD4 FBAD5 FBAD6 FBAD7 FBAD8 FBAD9 FBAD10 FBAD11 FBAD12 FBAD13 FBAD14 FBAD15 FBAD16 FBAD17 FBAD18 FBAD19 FBAD20 FBAD21 FBAD22 FBAD23 FBAD24 FBAD25 FBAD26 FBAD27 FBAD28 FBAD29 FBAD30 FBAD31 FBAD32 FBAD33 FBAD34 FBAD35 FBAD36 FBAD37 FBAD38 FBAD39 FBAD40 FBAD41 FBAD42 FBAD43 FBAD44 FBAD45 FBAD46 FBAD47 FBAD48 FBAD49 FBAD50 FBAD51 FBAD52 FBAD53 FBAD54 FBAD55 FBAD56 FBAD57 FBAD58 FBAD59 FBAD60 FBAD61 FBAD62 FBAD63 1 1 1 2 44 1D2V_S0 C28 A26 C24 B24 A24 C22 A25 B25 D23 G22 J23 E24 F23 J24 F24 G23 H24 D16 E16 D17 F18 E19 E18 D20 D19 A18 B18 A19 B19 D18 C19 C16 C18 N26 N25 R25 R26 R27 T25 T27 T26 AB23 Y24 AB24 AB22 AC24 AC22 AA23 AA22 T24 T23 R24 R23 R22 T22 N23 P24 AA24 AA27 AA26 AB25 AB26 AB27 AA25 W25 2 FBAD0 FBAD1 FBAD2 FBAD3 FBAD4 FBAD5 FBAD6 FBAD7 FBAD8 FBAD9 FBAD10 FBAD11 FBAD12 FBAD13 FBAD14 FBAD15 FBAD16 FBAD17 FBAD18 FBAD19 FBAD20 FBAD21 FBAD22 FBAD23 FBAD24 FBAD25 FBAD26 FBAD27 FBAD28 FBAD29 FBAD30 FBAD31 FBAD32 FBAD33 FBAD34 FBAD35 FBAD36 FBAD37 FBAD38 FBAD39 FBAD40 FBAD41 FBAD42 FBAD43 FBAD44 FBAD45 FBAD46 FBAD47 FBAD48 FBAD49 FBAD50 FBAD51 FBAD52 FBAD53 FBAD54 FBAD55 FBAD56 FBAD57 FBAD58 FBAD59 FBAD60 FBAD61 FBAD62 FBAD63 1 D C135 2 1 C116 SCD1U10V2KX-5GP 1 C126 2 C103 SC1U10V2KX-GP 2 AB10 AB11 AB14 AB15 W17 W18 AB20 AB21 SC10U10V5KX-2GP SC10U10V5KX-2GP PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD U59B 2/12 FBAD[0..15] place near GPU 2 3 44 1214 SC1U10V3KX-3GP 1D2V_S0 place near balls SCD1U10V2KX-5GP 4 1 U59A 1/12 2 5 Title 3 1 BAV99W-1-GP NB8M-GS (1 of 3) Size Custom Date: Document Number Rev SC Pamirs-Discrete Tuesday, December 19, 2006 Sheet 41 of 47
- 42. 5 4 3D3V_S0 3 2 U59C 3/12 L10 1 2 BLM15AG221SN-GP GDACA_VDD AD4 AC4 GMCH_HSYNC 15,17 GMCH_VSYNC 15,17 R331 124R2F-U-GP DACA_RED AE1 DACA_GREEN VGA_GREEN 15 DACA_BLUE AD2 1 TPAD30 TP1 IFPAB_PLLVDD DACA_IDUMP IFPA_TXD0# IFPA_TXD0 N5 N4 1 R332 1 R333 1 R334 U9 2 2 150R2F-1-GP 150R2F-1-GP 150R2F-1-GP VGA_TXAOUT2- 16 VGA_TXAOUT2+ 16 P6 R6 W2 W3 VGA_TXBOUT0- 16 VGA_TXBOUT0+ 16 AA3 AA2 VGA_TXBOUT1- 16 VGA_TXBOUT1+ 16 CH751H-40PT-1GP D34 K 1 T6 T5 1 2 NB8M-GS-GP SRN2K2J-1-GP IFPB_TXC# IFPB_TXC U4 T4 1 1 2 DACB_VREF DACB_RSET DACB_HSYNC DACB_VSYNC R370 124R2F-U-GP VGA_TXBCLK- 16 VGA_TXBCLK+ 16 DACB_RED 1 E9 D8 LDDC_CLK 16 LDDC_DATA 16 R96 10KR2J-3-GP 2 2 150R2F-1-GP 150R2F-1-GP 150R2F-1-GP B C173 SCD01U16V2KX-3GP U19 U59G GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 A9 D9 A10 B10 C10 C12 B12 A12 A13 B13 B15 A15 B16 HDMI_HDP HDMI_HDP 23 LBKLT_CRTL 16 LCDVDD_EN 16 BLON_IN 31 GPIO_PWRCNTL 40 GPU_THRM# GPU_ALERT# 1 3D3V_S0 7/12 ROMCS# D1 ROM_SI ROM_SO ROM_SCLK R361 10KR2J-3-GP F3 D3 D2 TP37 TPAD30 HDCP_SDA 8 7 6 5 VCC NC#7 SCL SDA NC#1 NC#2 NC#3 GND 1 2 3 4 HDCP_SCL AT88SC0808C-SU-GP I2CH_SCL I2CH_SDA F7 D7 R95 10KR2J-3-GP 2 A7 TESTMODE HDCP_SCL HDCP_SDA A6 SWAPRDY MEM_VREF 45 HDMI_CEC 23 C7 B7 STEREO 2 2 2 I2CC_SCL I2CC_SDA BUFRST# 2 VGA_TV_COMP 15 1 R32 1 R35 1 R33 1 R380 10KR2J-3-GP L9 D11 1 JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST# VGA_TV_LUMA 15 D5 3D3V_S0 THERMDP AE27 AD26 AD27 AE26 AD25 VGA_TV_CRMA 15 3D3V_S0 2 2 B9 F4 E4 DACB_BLUE 1 1 THERMDN HDMI_SDA 23 SC12P50V2JN-3GP 2 1 1 R379 10KR2J-3-GP C9 C561 SC12P50V2JN-3GP NB8M-GS-GP CLAMP C469 SC2200P50V2KX-2GP DY GTHERMDA E6 F5 HDMI_SCL 23 DACB_GREEN U59F 6/12 GTHERMDC F10 BLM15AG221SN-GP L44 HDMI_SCL_1 1 2HDMI_SCL BLM15AG221SN-GP L43 HDMI_SDA_11 2HDMI_SDA C562 2 D6 GDACB_RSET NB8M-GS-GP B I2CB_SDA E7 C78 F9 DACB_VDD DACB_IDUMP VGA_TXACLK- 16 VGA_TXACLK+ 16 W6 W5 C86 SCD01U16V2KX-3GP 2 1 IFPA_TXC# IFPA_TXC 1 AB2 AB3 IFPB_IOVDD C69 I2CB_SCL F8 GDACB_VREF VGA_TXBOUT2- 16 VGA_TXBOUT2+ 16 SC4700P25V2KX-LGP 2 AA1 AB1 2 SC1U10V3ZY-6GP Y4 IFPB_TXD6# IFPB_TXD6 IFPB_TXD7# IFPB_TXD7 IFPA_IOVDD 1 W4 GDACB_VDD 1 2 BLM15AG221SN-GP SC1U10V3ZY-6GP 2 IFPAB_IOVDD C40 U59D 4/12 L13 1 3D3V_S0 L5 1 2 BLM15AG221SN-GP C RN60 2 IFPAB_PLLGND 1 SC4700P25V2KX-LGP SC1U10V3ZY-6GP 2 IFPA_TXD2# IFPA_TXD2 IFPB_TXD5# IFPB_TXD5 R38 1KR2F-3-GP DY 1D8V_S0 2 SLOT_CLOCK_CFG 43 VGA_TXAOUT1- 16 VGA_TXAOUT1+ 16 IFPA_TXD3# IFPA_TXD3 IFPAB_PLLVDD IFPAB_RSET R4 R5 IFPB_TXD4# IFPB_TXD4 2 2 VGA_TXAOUT0- 16 VGA_TXAOUT0+ 16 IFPA_TXD1# IFPA_TXD1 V5 IFPAB_RSET U6 V6 22 D MIOA_D8 43 MIOA_D9 43 A C57 C 22 C4 MIOA_D6 43 4 3 C33 IFPAB_VPROBE MIOA_D0 43 MIOA_D1 43 5V_S0 1 1 For NB86 N6 A2 B3 A3 D4 A4 B4 B6 P4 C6 G5 V4 VGA_BLUE 15 U59E 5/12 1 2 BLM15AG221SN-GP NC#F6 NC#G6 NC#J6 VGA_RED 15 AD1 NB8M-GS-GP L4 F6 G6 J6 NC#A2 NC#B3 NC#A3 NC#D4 NC#A4 NC#B4 NC#B6 NC#P4 NC#C6 NC#G5 NC#V4 NC#C4 VGA_DDCCLK 15 VGA_DDCDATA 15 DACA_HSYNC DACA_VSYNC DACA_RSET D10 E10 DACA_VREF AD3 GDACA_RSET SCD01U16V2KX-3GP 2 1 1 1 AB4 C52 SC4700P25V2KX-LGP 2 1D8V_S0 SC1U10V3ZY-6GP 2 1 2 D C42 I2CA_SCL I2CA_SDA DACA_VDD GDACA_VREF C37 U59H 8/12 3D3V_S0 AE2 1 NB8M-GS-GP <Core Design> A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 1 A GND R368 10KR2J-3-GP AC8 Title 2 NB8M-GS-GP Size A3 NB8M-GS (2 of 3) Document Number Rev SC Pamirs-Discrete Date: Monday, December 18, 2006 Sheet 42 of 47
- 43. U59I 9/12 MIOB_D11 C1 J5 2 MIOB_VREF F1 G4 G1 F2 2 3 1 VGA_27MHZ 2 MIOB_HSYNC R318 150R2F-1-GP DY 0R2J-2-GP MIOB_CTL3 Put near GPU MIOB_CLKOUT MIOB_CLKOUT# MIOB_CLKIN K2 K3 R2 reserve for NB86 1 Vram : Samsung M5 1 2 BLM15AG221SN-GP M4 J3 1 1 C444 C48 R1 T1 T2 T3 DY HDMI_TXD0# HDMI_TXD0 HDMI_TXD1# HDMI_TXD1 IFPCD_PLLVDD IFPCD_RSET IFPC_TXD2# IFPC_TXD2 R31 2 For NB86 IFPC_TXD0# IFPC_TXD0 IFPC_TXD1# IFPC_TXD1 IFPCD_VPROBE SCD1U16V2ZY-2GP L6 1 2 R33810KR2J-3-GP U59L 12/12 2 1 2 HDMI_TXD0# 23 HDMI_TXD0 23 R341 DY 10KR2J-3-GP 1 2 HDMI_TXD1# 23 R335 DY 10KR2J-3-GP HDMI_TXD1 23 1 2 R336 10KR2J-3-GP HDMI_TXD2# 23 HDMI_TXD2# HDMI_TXD2 V3 V2 MIOB_D0: 1 R340 2 10KR2J-3-GP MIOB_D9 1 49D9R2F-GP R9 1 R10 1 49D9R2F-GP 49D9R2F-GP R7 1 R11 1 49D9R2F-GP R8 1 49D9R2F-GP 0101 0110 0111 R25 DY RAM_CFG_3 MIOB_D4: PCI_DEVID_1 MIOB_D3: 2 2KR2-GP PCI_DEVID_0 MIOB_D5: 2 2KR2-GP PCI_DEVID_2 G72M G72M-V G72M-Z 1000 0111 0110 MIOB_D11: PCI_DEVID_3 MIOB_CTL3: PCI_DEVID_4 MIOA_D1: SUB_VENDOR MIOA_D0: PEX_PLL_EN_TERM100 MIOA_D6: 1 R375 Infineon Hynix Samsung 1 -->8M*32 0-->16M*32 2 2KR2-GP 3GIO_PADCFG_LUT_ADDR[0] MIOA_D8: 3GIO_PADCFG_LUT_ADDR[1] 1 2 DY 2KR2-GP R22 MIOB_CTL3 1 2 R27 DY 2KR2-GP 1 R376 2 10KR2J-3-GP 0 SYSTEM BIOS 1 ADAPTER BIOS 0 ENABLED 1 DISABLED (DEFAULT) (DEFAULT) MIOA_D1 42 2 SLOT_CLOCK_CFG 42 DY 10KR2J-3-GP MIOA_D9: 42 MIOA_D0 MIOA_D0 1 R372 2 DY 2KR2-GP MIOA_D6 MIOA_D6 1 R373 42 MIOA_D8 MIOA_D8 1 R374 DY MIOA_D9 1 DY 2 2KR2-GP MIOB_HSYNC 1 R37 DY 3GIO_PADCFG_LUT_ADDR[2] 2 2KR2-GP 42 0 DESKTOP 1 MOBILE (DEFAULT) 2 2KR2-GP 2 2KR2-GP 2 2 2 2 2 2 SCD01U16V2KX-3GP 2 1 2 2 DY RAM_CFG_2 2 10KR2J-3-GP R26 42 DY RAM_CFG_1 MIOB_D9: MIOB_D8 1 MIOB_D11 HDMI_TXC# 23 HDMI_TXC 23 DY DY DY DY DY DY DY DY C17 2 SC1U10V3ZY-6GP SC4700P25V2KX-LGP 2 3D3V_S0 R12 1 49D9R2F-GP NB8M-GS-GP R14 1 49D9R2F-GP R13 1 49D9R2F-GP IFPC_IOVDD SCD01U16V2KX-3GP C16 2 1 1 1 C47 L4 HDMI_TXC# HDMI_TXC GDDR3 8Mx32 64bit MIOB_D8: 2 10KR2J-3-GP 1 R321 W1 V1 RAM_CFG_0 MIOB_D1: MIOB_D1 MIOB_D5 IFPCD_PLLGND IFPC_TXC# IFPC_TXC Values MIOA_D9 R36 MIOB_HSYNC: 3GIO_PADCFG_LUT_ADDR[3] <Core Design> R16 AD16 B17 E17 L17 P17 U17 AD17 AF18 K19 P19 V19 AD19 B20 E20 AD20 AF21 B23 E23 H23 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Bit Signal 2 10KR2J-3-GP 1 R323 C38 A 1 R339 1 R322 1 2 SC4700P25V2KX-LGP 2 SC1U10V3ZY-6GP B 3D3V_S0 MIOB_D3 L9 1 2 BLM15AG221SN-GP 64.25505.6DL N13 P13 R13 B14 E14 J14 L14 N14 P14 R14 U14 W14 AC14 AD14 N15 P15 R15 AF15 N16 P16 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND C440 DY SC27P50V2JN-2-GP B8 E8 AD8 K9 P9 V9 AD9 AF9 B11 E11 F11 L11 P11 U11 AD11 N12 P12 R12 AD12 AF12 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 27MHZ_XOUT For NB86 HDMI_TXD2 23 1KR2J-1-GP 3D3V_S0 XTAL-27MHZ-29-GP C447 DY SC22P50V2JN-4GP MIOB_D0 MIOB_D4 M6 DY 2 2 NB8M-GS-GP C66 C2 R21 1 10KR2J-3-GP C TPAD30 G72 : R324=255ohm , R318=150ohm G86 : R324=0ohm , R318=DY 2 MIOB_VSYNC MIOB_HSYNC MIOB_DE MIOB_CTL3 R324 1 J4 R337 2KR2-GP DY X6 TP36 1 1 MIOBCAL_PU_GND NC 1D8V_S0 1 MIOBCAL_PD_VDDQ M3 C3 XTALOUT NB8M-GS-GP 27MHZ_XIN 3 VGA_27MHZSS XTALOUTBUFF XTALIN 1 1 XTALSSIN B1 3D3V_S0 TPAD30 TP35 PLLGND B2 E2 H2 L2 P2 U2 Y2 AC2 AF2 AF3 B5 E5 L5 P5 U5 Y5 AC5 H6 AF6 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PLLVDD H5 1 1 H4 C58 SCD1U16V2ZY-2GP MIOB_D8 MIOB_D9 C46 2 MIOB_D3 MIOB_D4 MIOB_D5 C50 SC4700P25V2KX-LGP 2 1 PLL_VDD C49 SC1U10V3ZY-6GP 2 D SCD1U16V2ZY-2GP C98 MIOB_VDDQ MIOB_VDDQ MIOB_VDDQ L11 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND U59J 10/12 For NB86 reserve for NB86 MIOB_D0 MIOB_D1 G2 G3 J2 J1 K4 K1 M2 M1 N1 N2 N3 R3 2 1 K5 K6 L6 MIOBD0 MIOBD1 MIOBD2 MIOBD3 MIOBD4 MIOBD5 MIOBD6 MIOBD7 MIOBD8 MIOBD9 MIOBD10 MIOBD11 SC4D7U6D3V3KX-GP 2 1 3D3V_S0 1 2 BLM15AG221SN-GP 1 1D2V_S0 11/12 1 2 L23 P23 U23 Y23 AC23 AF24 B26 E26 H26 L26 P26 U26 Y26 AC26 AF26 D 3D3V_S0 2 3 R561 2KR2-GP 1 4 2 5 C B A NB8M-GS-GP Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 NB8M-GS (3 of 3) Document Number Rev SC Pamirs-Discrete Date: Monday, December 18, 2006 Sheet 43 of 47
- 45. 4 3 U7 1 1 WE# 41,44 FBA_RAS# H3 RAS# 41,44 FBA_CAS# F4 CAS# FBA_CKE H4 CKE CK# CK 2 R46 60D4R2F-GP B1 B4 B9 B12 D1 D4 D9 D12 G2 G11 L2 L11 P1 P4 P9 P12 T1 T4 T9 T12 A3 A10 G1 G12 L1 L12 V3 V10 VDDA VDDA K1 K12 VSSA VSSA SCD1U16V2ZY-2GP J12 J1 RDQS3 RDQS2 RDQS1 RDQS0 1103 SA 1 2 1 CS# H9 J10 J11 2 41 41 F9 FBA_WE# 41,44 R47 60D4R2F-GP B FBA_CS0# 41,44 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSS VSS VSS VSS VSS VSS VSS VSS FBA_CLKN1 FBA_CLKP1 FBADQSN7 FBADQSN6 FBADQSN5 FBADQSN4 41 41 41 41 FBADQSP7 FBADQSP6 FBADQSP5 FBADQSP4 P2 P11 D11 D2 WDQS3 WDQS2 WDQS1 WDQS0 41 41 41 41 FBADQM7 FBADQM6 FBADQM5 FBADQM4 N3 N10 E10 E3 DM3 DM2 DM1 DM0 1D8V_S0 V9 FBA_RST 1 1 2 A4 240R2F-1-GP SC1U6D3V2ZY-GP 1 2 2 2 2 1 1 1 1 2 SC4D7U10V5ZY-3GP 1 2 SC1U6D3V2ZY-GP 1 2 SC1U6D3V2ZY-GP 1 2 1 2 SC1U6D3V2ZY-GP SC1U6D3V2ZY-GP 1 2 1 2 SC1U6D3V2ZY-GP C44 C B C7 SCD1U16V2ZY-2GP V4 R30 0R2J-2-GP ZQ H1 VREF VREF A9 2 MF 1 R73 0R2J-2-GP HY5RS573225AFP-GP VRAM_VREF SCD1U16V2ZY-2GP <Core Design> A 2 41,44 Wistron Corporation 2 C18 2 1 C73 SCD1U16V2ZY-2GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 2 G C31 2 VRAM_VREF 2 910R2F-1-GP 1 D MEM_VREF S 42 C43 1D8V_S0 RES H12 R40 Q20 1K33R2F-GP 2N7002-11-GP C134 1 R15 510R2F-L-GP A SC1U6D3V2ZY-GP C276 C10 R62 R363 1 C143 1 41,44 1D8V_S0 C5 J2 RFU C133 J3 RFU C27 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP 1D8V_S0 C12 PAR C139 C36 2 41 41 41 41 P3 P10 D10 D3 C6 1 41,44 SCD01U16V2KX-3GP C112 FBA_A11 FBA_A10 FBA_A9 FBA_A8 FBA_A7 FBA_A6 FBB_A5 FBB_A4 FBB_A3 FBB_A2 FBA_A1 FBA_A0 A2 A11 F1 F12 M1 M12 V2 V11 1D8V_S0 SC1U6D3V2ZY-GP A11 A10 A9 A8/AP A7 A6 A5 A4 A3 A2 A1 A0 41,44 41,44 41,44 41,44 41,44 41,44 41 41 41 41 41,44 41,44 R52 0R2J-2-GP VDD VDD VDD VDD VDD VDD VDD VDD D 1 L4 K2 M9 K11 L9 K10 H11 K9 M4 K3 H2 K4 2 41,44 FBA_CS1#/BA2 41,44 FBA_BA1 41,44 FBA_BA0 A1 A12 C1 C4 C9 C12 E1 E4 E9 E12 J4 J9 N1 N4 N9 N12 R1 R4 R9 R12 V1 V12 2 BA2 BA1 BA0 1D8V_S0 C 1D8V_S0 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 1 41 FBAD[32..47] DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 H10 G9 G4 D T3 T2 R3 R2 M3 N2 L3 M2 T10 T11 R10 R11 M10 N11 L10 M11 G10 F11 F10 E11 C10 C11 B10 B11 G3 F2 F3 E2 C3 C2 B3 B2 2 FBAD63 FBAD62 FBAD61 FBAD60 FBAD59 FBAD58 FBAD57 FBAD56 FBAD55 FBAD54 FBAD53 FBAD52 FBAD51 FBAD50 FBAD49 FBAD48 FBAD47 FBAD46 FBAD45 FBAD44 FBAD43 FBAD42 FBAD41 FBAD40 FBAD39 FBAD38 FBAD37 FBAD36 FBAD35 FBAD34 FBAD33 FBAD32 1 1 41 FBAD[48..63] 2 2 5 Title Size A3 VRAM2 Document Number Rev SC Pamirs-Discrete Date: Monday, December 18, 2006 Sheet 45 of 47
- 46. 5 4 3 2 1 Adaptor in to generate DCBATOUT 1 2 3 4 5 AD+ 2 4K7R2J-2-GP AD_JK 1 EC50 U58 S S S G R1 R1 R1 2 IN AD_OFF 1 1 C451 SCD1U25V3ZY-1GP 2 SCD1U25V3ZY-1GP 1 R2 E R352 100KR2J-1-GP C Q19 2 Q18 31 D C461 PDTA124EU-1-GP B 8 7 6 5 C442 SCD1U25V3ZY-1GP 1 AD_OFF# D D D D AO4407-1-GP 2 R328 200KR2J-L1-GP 2 1 1 C459 SC1000P50V3JN-GP 2 1 SCD1U25V3ZY-1GP 2 1 DY DY EC48 EC10 C460 SCD1U25V3ZY-1GP SCD1U25V3ZY-1GP 2 2 20.80354.005 AD+_2 SCD1U25V3ZY-1GP 2 1 ACES-CON5-4-GP-U1 1 2 3 4 2 D AD+ R360 DCIN1 1 3 OUT 1 GND R2 DTC114EUA-1-GP C C BATTERY CONNECTOR 3D3V_AUX_S5 KBC_SDA0 3 2 BT_TH 3 BT+ 3 1 1 BAV99W-1-GP BAV99W-1-GP BAV99W-1-GP G8 39 B BT+SENSE 1 1 1 2 GAP-CLOSE 2 3 4 5 6 8 31 KBC_SCL0 31 KBC_SDA0 31,39 BT_TH 20.80345.006 1 2 2 KBC_SCL0 7 1 D26 C34 SCD1U25V3ZY-1GP 2 2 BAT1 3D3V_AUX_S5 3D3V_AUX_S5 D27 D28 B C465 SC1000P50V3JN-GP <Core Design> A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title AD/BATT CONN Size A3 Document Number Date: Monday, December 18, 2006 5 4 3 2 Rev SC Pamirs-Discrete Sheet 1 46 of 47
- 47. A 2 1 1 SPR2 SPRING-18-U SPR3 SPRING-18-U SPRING-24-GP SPR7 SPRING-13-GP SPRING-18-U DY SPR9 SPR4 SPRING-18-U SPR8 SPRING-13-GP B 1D8V_S3 SPR5 SPRING-18-U 1 1 1 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 2 1102 SA 1 1 SCD1U16V2ZY-2GP 2 C 1 1 1 1 1 1 1 1 1 1 1 1 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 2 DY DY DY DY DY DY EC32 EC28 EC29 EC62 EC71 EC63 H29 For SKT2 1 D 1 1 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 2 DY DY DY DY EC51 EC88 EC42 EC2 Size A3 1 3D3V_S0 Date: Monday, December 18, 2006 1 Sheet E 47 SCD1U25V3ZY-1GP SCD1U25V3ZY-1GP 2 SCD1U25V3ZY-1GP 2 EC49 EC110 EC111 1 1 1 1 1 1 1 1 1 1 1 1 DCBATOUT SCD1U25V3ZY-1GP 1 SCD1U25V3ZY-1GP 2 SCD1U25V3ZY-1GP 2 SCD1U25V3ZY-1GP 2 SCD1U25V3ZY-1GP 2 SCD1U25V3ZY-1GP 2 SCD1U25V3ZY-1GP 2 SCD1U25V3ZY-1GP 2 SCD1U25V3ZY-1GP 2 SCD1U25V3ZY-1GP 2 SCD1U25V3ZY-1GP 2 SCD1U25V3ZY-1GP 2 1 1 1 EC11 EC14 1 1 1 D SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP 2 1 1 EC120 EC121 SCD1U25V3ZY-1GP 2 2 1 DY EC27 EC37 SCD1U16V2ZY-2GP 2 2 1 SCD1U25V3ZY-1GP 2 SCD1U25V3ZY-1GP 2 2 SCD1U25V3ZY-1GP SCD1U25V3ZY-1GP 2 2 DY EC61 EC57 EC17 EC55 EC30 EC65 EC13 EC75 EC76 EC34 EC20 1 SCD1U16V2ZY-2GP 2 1 SCD1U16V2ZY-2GP 2 1D05V_S0 1 2 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP 3 SCD1U16V2ZY-2GP 2 2 1 1 SCD1U16V2ZY-2GP 2 SCD1U16V2ZY-2GP 1 SCD1U16V2ZY-2GP 2 HOLE SCD1U25V3ZY-1GP 2 C SCD1U16V2ZY-2GP 1 SCD1U16V2ZY-2GP 2 DY DY DY EC36 EC74 EC64 EC89 EC73 EC38 EC78 EC69 EC66 EC35 1 87.66383.251 SCD1U16V2ZY-2GP 2 H30 1 DY SCD1U16V2ZY-2GP 2 1 87.66293.211 87.66383.251 1 2 H26 H16 SCD1U16V2ZY-2GP 2 HOLE H6 1 1 HOLE 4 HOLE HOLE EC43 SCD1U16V2ZY-2GP 2 1 1 1 1 HOLE HOLE B SCD1U16V2ZY-2GP 1 2 EC94 EC95 EC96 EC97 EC98 EC99 EC107 EC108 SCD1U16V2ZY-2GP 2 HOLE H5 1 H27 1 1 H17 SCD1U16V2ZY-2GP 2 1 H24 H22 1 H25 H15 HOLE H23 HOLE 1 1 HOLE H9 SCD1U16V2ZY-2GP 2 SPR10 1 1 1 H20 1 1 H3 HOLE H19 H8 HOLE HOLE HOLE H21 1 H12 1 H11 HOLE 1 1 HOLE HOLE H4 HOLE HOLE 1 1 H28 1 1 1 H7 HOLE H18 HOLE HOLE HOLE H10 1 1 1 1 H2 1 SPR6 HOLE HOLE H13 1 SPRING-24-GP 1 1 H14 1 1 H1 1 1 1 2 1 1 A E AD+ 1102 SA EC109 4 1D5V_S0 DCBATOUT EC122 3 5V_S0 DY DY EC33 EC70 87.66383.251 SPR1 1102 SA EC100 EC102 EC101 EC104 EC105 EC103 EC106 2 34.4F622.001 SPRING-18-U <Core Design> 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Document Number MISC Pamirs-Discrete of Rev 47 SC