The document discusses the challenges and improvements in a VHDL and Verilog formatting tool at EclipseCon France 2017, focusing on the transition from Formatter 1.0 to Formatter 2.0. It highlights issues with the existing formatter, such as bugs and limitations in adding new features, and introduces the new API that facilitates context-aware and customizable formatting. A structured plan for implementing the updates is presented, including test compatibility and performance enhancements.