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© 2019 Hailo
Introducing Hailo-8™: The Most
Efficient Deep Learning Processor
for Edge Devices
Orr Danon
Hailo
May 2019
© 2019 Hailo
Presenting the Hailo-8™
The world’s most powerful and efficient edge AI processor
High Performance
26 TOPS
High Efficiency
3 TOPS/W
Automotive
ASIL-B(D)
AEC-Q100 Grade 2
Flexible
Fully programmable
Comprehensive SDK
Self Contained
No external DRAM
Deployment
Stand alone mode
Co-processor mode
© 2019 Hailo 3
Power Efficiency
0 1 2 3 4
Hailo-8
Google Edge TPU (*,**)
Nvidia Xavier
Intel Movidius Myriad X (*)
TOPS/Watt
Image classification inference task, batch = 1
Based on public benchmarks (see ref below)
(*) Excluding host and/or memory
(**) Estimated
© 2019 Hailo
Product Overview
4
Hailo Centric System Hailo as Co-Processor
© 2019 Hailo
Current AI Processor Architectures
Von-Neumann Architecture
Symmetric Dataflow Architecture
• Temporal resource allocation
• Common memory space
• Spatial resource allocation
• Segregated memory spaces
Fixed Function Accelerator
• Theoretically optimal at a specific workload
• Minimal flexibility
System Bus
Control Compute
Memory
Inter-element Bus
Control Compute
D-MemI-Mem
© 2019 Hailo 6
Structure Defined Dataflow Architecture (1)
• Model structure
defines connectivity
• Resources
• Heterogeneous
• Asymmetric
• Variable
Control
Memory Memory Memory
Control
Data Interconnect
Control
Memory
Compute Compute ComputeCompute
ControlInterconnect
© 2019 Hailo
Structure Defined Dataflow Architecture (2)
7
© 2019 Hailo
Structure Defined Dataflow Architecture (3)
8
© 2019 Hailo
Comprehensive SDK
9
• Full-Stack solution from
trained model to deployment
• Automatic numerical
conversion and emulation
• Accurate profiling
• Continuous delivery of
features and optimizations
Numeric Translator
Compiler
Hailo Devices
Emulator
Profiler
Resource Allocator
Model Translator
© 2019 Hailo 10
Power Efficiency
0
0.5
1
1.5
2
2.5
3
3.5
CLASSIFICATION DETECTION (720p) SEGMENTATION (1080p)
PowerEfficiency[TOP/W/s] NVIDIA AGX XAVIER*
Google Edge TPU*
HAILO Hailo-8
* References:
- NVIDIA AGX Xavier: : https://developer.nvidia.com/embedded/jetson-agx-xavier-dl-inference-benchmarks
- Google Edge TPU: https://coral.withgoogle.com/docs/edgetpu/benchmarks
** Edge TPU performance is measured for 224x224; Linearly extrapolated to 720p
Frame per second (FPS) 656 37 672 8.4* 40 4064
© 2019 Hailo
Hailo-8™ Fast-Track Program
• Early access to developer suite for the Hailo-8™ device
• Register at our website: hailo.ai
11
© 2019 Hailo
Presenting the Hailo-8™
The world’s most powerful and efficient edge AI processor
High Performance
26 TOPS
High Efficiency
3 TOPS/W
Automotive
ASIL-B(D)
AEC-Q100 Grade 2
Flexible
Fully programmable
Comprehensive SDK
Self Contained
No external DRAM
Deployment
Stand alone mode
Co-processor mode
© 2019 Hailo
Thank You!
13
contact@hailotech.com

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"Emerging Processor Architectures for Deep Learning: Options and Trade-offs," a Presentation from Hailo

  • 1. © 2019 Hailo Introducing Hailo-8™: The Most Efficient Deep Learning Processor for Edge Devices Orr Danon Hailo May 2019
  • 2. © 2019 Hailo Presenting the Hailo-8™ The world’s most powerful and efficient edge AI processor High Performance 26 TOPS High Efficiency 3 TOPS/W Automotive ASIL-B(D) AEC-Q100 Grade 2 Flexible Fully programmable Comprehensive SDK Self Contained No external DRAM Deployment Stand alone mode Co-processor mode
  • 3. © 2019 Hailo 3 Power Efficiency 0 1 2 3 4 Hailo-8 Google Edge TPU (*,**) Nvidia Xavier Intel Movidius Myriad X (*) TOPS/Watt Image classification inference task, batch = 1 Based on public benchmarks (see ref below) (*) Excluding host and/or memory (**) Estimated
  • 4. © 2019 Hailo Product Overview 4 Hailo Centric System Hailo as Co-Processor
  • 5. © 2019 Hailo Current AI Processor Architectures Von-Neumann Architecture Symmetric Dataflow Architecture • Temporal resource allocation • Common memory space • Spatial resource allocation • Segregated memory spaces Fixed Function Accelerator • Theoretically optimal at a specific workload • Minimal flexibility System Bus Control Compute Memory Inter-element Bus Control Compute D-MemI-Mem
  • 6. © 2019 Hailo 6 Structure Defined Dataflow Architecture (1) • Model structure defines connectivity • Resources • Heterogeneous • Asymmetric • Variable Control Memory Memory Memory Control Data Interconnect Control Memory Compute Compute ComputeCompute ControlInterconnect
  • 7. © 2019 Hailo Structure Defined Dataflow Architecture (2) 7
  • 8. © 2019 Hailo Structure Defined Dataflow Architecture (3) 8
  • 9. © 2019 Hailo Comprehensive SDK 9 • Full-Stack solution from trained model to deployment • Automatic numerical conversion and emulation • Accurate profiling • Continuous delivery of features and optimizations Numeric Translator Compiler Hailo Devices Emulator Profiler Resource Allocator Model Translator
  • 10. © 2019 Hailo 10 Power Efficiency 0 0.5 1 1.5 2 2.5 3 3.5 CLASSIFICATION DETECTION (720p) SEGMENTATION (1080p) PowerEfficiency[TOP/W/s] NVIDIA AGX XAVIER* Google Edge TPU* HAILO Hailo-8 * References: - NVIDIA AGX Xavier: : https://developer.nvidia.com/embedded/jetson-agx-xavier-dl-inference-benchmarks - Google Edge TPU: https://coral.withgoogle.com/docs/edgetpu/benchmarks ** Edge TPU performance is measured for 224x224; Linearly extrapolated to 720p Frame per second (FPS) 656 37 672 8.4* 40 4064
  • 11. © 2019 Hailo Hailo-8™ Fast-Track Program • Early access to developer suite for the Hailo-8™ device • Register at our website: hailo.ai 11
  • 12. © 2019 Hailo Presenting the Hailo-8™ The world’s most powerful and efficient edge AI processor High Performance 26 TOPS High Efficiency 3 TOPS/W Automotive ASIL-B(D) AEC-Q100 Grade 2 Flexible Fully programmable Comprehensive SDK Self Contained No external DRAM Deployment Stand alone mode Co-processor mode