Research Inventy : International Journal of Engineering and Science is published by the group of young academic and industrial researchers with 12 Issues per year.

RESEARCH INVENTY: International Journal of Engineering and Science
ISSN: 2278-4721, Vol. 1, Issue 7 (November 2012), PP 36-41
www.researchinventy.com

Design of LDPC Decoder Using FPGA: Review of Flexibility
1
Asisa Kumar Panigrahi, 2Ajit Kumar Panda
1, 2
(Department of Electronics & Communication Engg
National Institute of Science & Technology
Brahmapur, India)

Abstract - Low Density Parity Check (LDPC) codes have become very popular now-a-days because of their
shannon limit approaching error correcting capability and hence have been used in many applications. This
paper demonstrates a flexible Low Density Parity Check (LDPC) decoder which is an improve ment over other
existing work on a general LDPC decoder. In this paper we have presented a fully flexible LDPC decoder design
in FPGA which supports different codes and data rates. This decoder finds application in many communication
standards such as Wireless LAN (IEEE 802.lln), WIMAX (IEEE 801.16e) and DVB-S2, on a single hardware
platform which makes the transition from theory to practice a much easier one. Finally, this paper proposes a
method of designing of fully flexible LDPC Decoder in Spartan6 - xc6slx16-3 FPGA hardware.
Keywords - Error-correcting code, FPGA hardware, LDPC, ROM Configuration Shannon capacity

I. INTRODUCTION
Error correction coding is a means which deals with detection and correction of errors which are
introduced into a communication system by the receiver. Shannon published a paper in 1948 that revolutionized
communicat ions. He found that there is a fundamental limit to how much in formation can be reliably sent over a
channel (its capacity) with respect to the noise present in the system [1]. Although he defined a limit, it only
showed how good the best possible code would perform, hence the proof was non-constructive. Low Density
Parity Check (LDPC) Codes are a class of block code that satisfies both randomness and increased length. These
codes are found to have the best performance till date, by achieving a capacity within 0.00 45 dB of the Shannon
limit [2].A (n, k) block code takes k bits (message bits) at a time and produces n bits (code bits). Normally,
Block codes introduce redundancy for error correct ion. Let u be the collection of k message bits which is
denoted as message word, and c be the collection of n encoded bits which is denoted as a codeword.

An important parameter of a block code is its code rate (r). It is a measure of the amount of informat ion
(message) bits sent per codeword. The more the informat ion sent, the lesser the redundancy and fewer the error
correction by the code. Conversely if the amount of redundancy introduced is high the transmitter will spend
less time sending informat ion.
The code words are encoded through a generator matrix G as given by the follo wing identity:
c=u * G
Where G is a (n, k) binary matrix.
For every generator matrix G, there exists many parity check matrices (H) that satisfy the equation:
G * HT = 0
The parity check matrix has the follo wing important property i.e. c is a codeword if and only if it satisfies:
C * HT = 0
i.e. all the code words lie in the null space of H.
Low Density Parity Check (LDPC) Codes are a form of forward erro r correction codes and was first
discovered by Gallager in 1962 [3]. These are nothing but block codes whose parity -check matrix (H) contains
very few non zero entities.

H=

(a)
36

Design Of LDPC Decoder Using FPGA: Review of Flexibility

(b)
Fig 1. LDPC code examp le. (a) Parity check matrix (b) Tanner graph

The Tanner graph shown above is a graphical form of representing the parity check matrix. A Tanner
graph consists of two sets of vertices i.e. n vertices for the codeword bits (bit nodes), and m vertices for the
parity-check equations (check nodes). A bit node gets joined to a check node by an edge, if that bit is included in
the corresponding parity-check equation. The number of edges in the tanner graph is equal to the number of
ones in the parity check mat rix. Fig 1(b) shows a Tanner graph representation of the parity check matrix H as
shown in Fig 1(a).

1.1 DECO DING -MESSAGE PASSING :
The most typical decoding procedure implemented in several designs is the message passing algorithm, also
known as “sum-product” or “belief propagation” (BP) Algorithm [4]. This algorith m imp lements the iterative
exchange of node-generated messages along the edges of the graph. Most of the implementation challenges
come fro m the communication structure to support message exchange among Variab le Nodes (VNs) and Check
Nodes (CNs) even if the nodes require additional computational capabilities. In addition, modern applications
often need adaptation capabilities in a number of system parameters as block size and code rate impose tight
flexib ility requirements on hardware imp lementation of some designs.

II. LITERATURE REVIEW ON FLEXIBLE LDPC DECODER
Several researches have been conducted on the LDPC decoder till date, but there is very less reported
work on flexible LDPC decoders. Some of the literature surveys done are summarized as follows:

2.1 S ERIAL D ECODER
It consists of a single check node, a single variable node and memory. The variable nodes can be
updated once at a time and then the check nodes are updated in the serial manner. Serial i mplementation has a
added advantage that it is very flexib le thereby supporting different block sizes and code rates with only a new
parity matrix being loaded into the memo ry. Unfortunately, this approach is too slow for any operation except
simu lations [5]. The number of clock cycles required for each iteration of the serial decoder is approximately
twice the nu mber of edges present.

2.2 ANALO G IMPLEMENTATIO N
While majority of the papers presented the use of digital signals to implement the decoder architect ure,
a number of papers have also used analog methods for implementation of their proposed designs. While it is not
feasible to imp lement an analog decoder on an FPGA (FPGA devices can only process digital signals), it is
nonetheless interesting to see analog methods being applied to solve a purely dig ital problem especially when
their perfo rmance is co mparable to their digital counterparts. There were two approaches of imp lementing the
sum product algorithm. One of the two approaches was to use the non -linearities of charging a Field Effect
Transistor (FET) [6, 7], while the other approach was to use a combination of resistors and capacitors, thereby
resulting in RC differential equations [8]. The main d isadvantage of these two approaches is that they provide
more delay during decoding and are not feasible to imp lement on FPGA.

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2.3 PARALLEL DECODER
A fully-parallel decoder completes the update check message step in one clock cycle and then in the
next cycle completes the update bit message step. This allows a marked increase in decoding speed as compared
to the serial decoder. The main disadvantage of using the decoder is that none of the reviewed parallel decoder
implementations [9, 10, 11, and 12] have any flexib ility in view of code design. The routing between check and
bit nodes need redesigning for another code realizat ion, wh ile a d ifferent code rate or degree d istribution may
not be possible without a complete redesign.

2.4 PARTIALLY PARALLEL DECODER
In a partially parallel decoder design, some check and bit nodes are realized in hardware which
involves sharing as in the serial decoder case. There is a trade-off between speed and complexity wh ich results
in increase in the number of check and bit nodes when realized in hardware wh ich in turn increases the speed of
each decoder iteration. This in turn increases the complexity of the design. Serial and parallel architectures
could be considered subclasses of the partially parallel decoder (serial imp lementation has only one bit and
check node realized in hardware while parallel imp lementation would have all b it and check nodes realized in
hardware). The major d isadvantage in this case is memory collision. If two nodes try to access the same memo ry
during the same clock cycle a collision occurs and one of the nodes has to stall for a cycle which in turn
decreases the throughput of the decoder.

III. VARIOUS PROPOS ED M ETHODS FOR FLEXIBLE LDPC DECODER IMPLEMENTATION
A number of authors have recommended the use of partially parallel method for designing a fully
flexib le LDPC Decoder.Masera et al., (2007) proposed flexible LDPC decoder with the help of Low-Traffic BP
(LTBP) algorith m [5]. The LTBP algorith m is of real help in the imp lementation of LDPC decoders only if a
communicat ion network supports parallel Multicast. A simple structure to implement such a network consists of
a crossbar switch known as „Bens Network‟ and a multip lexer bank. The memory collision problem wh ich
occurs due to the usage of partially parallel decoder is somehow reduced by this architecture. Unfortunately, the
design is highly complex and not so mature as far as speed is concerned. In another research, Lee et al., (2008)
have also used the Benes network in their partially parallel LDPC decoder design [13]. In the proposed
architecture, Benes network is used to implement the interconnection network that can be configured according
to a parity-check matrix. Co mpared to the previous flexib le architecture, the proposed decoder shows a better
Throughput-to-Area Ratio (TAR). Unfortunately the design being highly comp lex and deeply pipelined is
suitable for no application other than Application Specific Integrated Circu it (ASIC) imp lementation. Chuan
Zhang et al. (2010) proposed a flexible LDPC decoder design for mbps applications [14]. The Benes network is
emp loyed to implement the configurable interconnections between the Variab le Node Processing Unit (VNPU)
and Check Node Processing Unit (CNPU) arrays which in turn brings sufficient flexib ility for mult iple code
rates and code lengths. Compared to the previous flexible arch itecture, the proposed decoder shows better TAR.
By adopting better optimized p ipelining scheme higher throughput can be achieved in this architecture.

IV. FULLY F LEXIBLE DECODER ARCHITECTURE
The design is based on scheduling as described in [15] by Masera et al. The proposed design
implementation is based on both partially parallel imp lementation and unicast messages while the design
proposed by Masera et al is based on multicast messages. In this design, the interleaver is more co mplex wh ile
the bit and check node processors as well as the scheduling are simpler.
The main design goal is universality i.e. the decoder should be capable of imp lementing any given code (up to
maximu m design constraints) without changing the design of th e decoder. The architecture consists of a number
of Processors (P), a Message Permutation Block (M PB) and a Control Logic Block (CLB), as shown in Fig 2.

Fig 2. Top block d iagram for decoder

38

The decoding process follows four distinct steps as shown in Fig. 3.

4.1. INITIALIZATIO N
During init ialization, channel measurements are loaded into the bit processor blocks.

4.2. BIT TO CHECK
During the bit to check half iterat ion, the bit node processor performs the bit node function as described
in the equation below [16].

In the first half iteration there are no incoming messages and the processor outputs the channel measurement.
The messages flow fro m the bit node processors through the message permuting block and then to the
corresponding check node processor in order.

4.3. CHECK TO BIT
During the bit to check half iteration, the check node processor performs the check node function as
described in the equation below [16].

The messages flow fro m the check node processors through the message permuting block and then to the
corresponding bit node processor in order.

4.4. OUTPUT
After a number of iterations of bit to check and check to bit cycles the decoder moves to the output
stage.

Fig 3. State machine fo r decoder

The MPB decides the flexibility of the decoder. Its purpose is to connect the bit node processor to the
check node processor (and vice versa), so that the check node processor receives the incoming messages in a
order as depicted in the Tanner graph. The control unit is responsible for imp lementing the state machine. The
configuration for the code is stored in a ROM b lock within the control unit wh ich contains information about the
time vary ing settings for the Benes network and the interleaver banks in the mes sage permutation unit. It also
assigns the appropriate bit and check nodes to the respective processors.

V. DES IGN APPROACH
System generator is very flexib le in integrating different design approaches namely Simu link models
and VHDL codes. Simulink provide a much higher level of abstraction than VHDL. Therefore, our design
approach utilizes Simu lin k library blocks to design various modules of the proposed decoder architecture and
the VHDL code for the same is generated automatically using system generator. The auto-generated VHDL
code can also be used in Xilin x ISE (Integrated Software Environ ment) for synthesis and imp lementation on
desired FPGA (Field Programmab le Gate Array). Automatic VHDL code generation reduces design efforts
hence increases design productivity.

VI. DECODER D ES IGN
Our decoder design architecture mainly consists of two Processors i.e. Check Node Unit Processor and
Variable Node Unit Processor. A generic Simulink model was first developed for the variable node and check
node.
6.1. VARIABLE NODE D ESIGN USING S IMULINK
The variable node, shown in Fig 4, has been designed in Simu lin k using the basic addsub and mu x
Xilin x blocks fro m the Simu lin k library. As shown in Fig 4, the total sum is computed from three messages
coming in fro m different check nodes as well as the channel input data. Three different outgoing messages are
formed where each outgoing message has each corresponding message from the check node subtracted from it.
39

These outgoing messages are sent to the appropriate node connection as designated by the parity check mat rix.
At the start of the first iteration, the variable nodes will simp ly bypass the sum operation and send the input
noisy channel data directly to the check nodes as there are no return messages fro m the check node in the
beginning.

Fig 4. Variable node design in Simu lin k

6.2. CHECK NO DE D ESIGN USING S IMULINK
The Simu link model of the check node is as shown in Fig 5

.
Fig 5. Check node design in Simulink
It uses blocks from Simulink library (absolute and bitwis e XOR Xilin x blocks). The check node finds
the minimu m of all the inputs and performs the parity checks. Finally, the fully flexib le LDPC decoder design
using Variable node and Check node is shown in Fig 6 below.

Fig 6. LDPC Decoder design in Simu link

Once the Simulink models are developed for the LDPC Decoder, the VHDL code can be generated
automatically using the system generator.

40


VII. FPGA IMPLEMENTATION AND SIMULATION RES ULTS
We implement this LDPC decoder in Xilin x Hardware Description Language and synthesize it using ISE (Ver.
13.4). The code is downloaded onto the xc6slx16 device of Spartan 6 family using csg324 package. The b oard
was NEXYS 3 fro m DIGILENT s partan6. The table below summarizes the design statistic results of FPGA for
the desired LDPC decoder.

Logic Components(Resources) Used

Slices 765

Flip flops 646

Block RAMs 19

Maximum Frequency of Operation 89.29MHz

VIII. CONCLUS ION
This paper has undergone an extensive review of the existing research works on flexible LDPC d ecoder
and flexible LDPC decoders. We have designed a fully flexib le LDPC decoder by using partially parallel
implementation and the decoder is found to run at a clock speed of 11.2ns (Maximu m frequency of operation
being 89.29M Hz). Based on these results, we conclude that the proposed architecture provides better solution
for high speed decoding and also takes lesser area. Hence TA R increases which is better than the previous
architectures.
IX. ACKNOWLEDGMENT
The authors acknowledge TIFAC-CORE for 3G/4G Co mmunication Technologies at National Institute
of Science & Technology, Brah mapur, Odisha.

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