![ACEEE Int. J. on Information Technology, Vol. 01, No. 01, Mar 2011
FIR Filter Implementation by
Systolization using DA-based Decomposition
Shreeharsha K G, Rekha Bhandarkar
Department of Electronics and Communication Engineering Alva’s Institute of Engineering and Technology,
Mijar – 574 225, Moodbidri, INDIA
shreeharshakg01@gmail.com
Rekha Bhandarkar
Department of Electronics and Communication Engineering
NMAM Institute of Technology, Nitte – 574 110
Karkala, INDIA
rekhabhandarkar@rediffmail.com
Abstract– In this paper we present 1D and 2D systolic architecture, array in particular, is replacing a single
Distributed Arithmetic (DA) based structures that are designed Processing Element (PE) with an array of PEs or cells. Being
for the implementation of Finite Impulse Response (FIR) filters. able to use each input data item a number of times (and thus
The paper compares the 1D DA based systolic structure with achieving high computation throughput with only modest
1D systolic DA based decomposition method. The filters are memory bandwidth) is one of the advantages of the systolic
implemented on a Xilinx Virtex II Pro (XC2VP30) FPGA using
approach. They have several attractive features such as
HDL and system metrics like Area, Gate Count, Maximum
Usable Frequency and Power consumption are estimated for
simplicity, regularity and modularity of structure [2]. In
different filter orders and address lengths. The 1D systolic addition, they also possess significant potential to yield high-
decomposition structure is also compared with the existing throughput rate by exploiting high-level of concurrency using
system generator implementation of DA FIR.. Results for an pipelining or parallel processing or both.
exemplary implementation are presented.
II.DISTRIBUTED ARITHMETIC
Keywords— Distributed arithmetic (DA), Field Programmable
Gate Arrays (FPGA), Finite Impulse Response (FIR) filter, Distributed Arithmetic (DA) is an efficient method for
systolic array. computing inner products when one of the input vectors is
fixed[4]. It uses look-up tables and accumulators instead of
I.INTRODUCTION multipliers for computing inner products.
Let us consider the inner-product of two N-point vectors
Finite Impulse Response (FIR) filters are one of the most
A and B given by Eq. (1) as,
common components of Digital Signal Processing (DSP)
systems. FIR filtering is achieved by convolving the input
data samples with the desired unit response of the filter. Since
the complexity of implementation grows with the filter order
and the precision of computation, real-time realization of
these filters with desired level of accuracy is a challenging
task. Several attempts have, therefore, been made to develop
dedicated and reconfigurable architectures for realization of
FIR filters in Application Specific Integrated Circuits (ASIC)
and FPGA platforms. DA provides an approach for
multiplier-less implementation of FIR filters where the filter
coefficients are programmable. In other words, the same filter
structure can be used for a different set of coefficients.
A systolic system consists of a set of interconnected cells,
each capable of performing some simple operation. Because
simple, regular communication and control structures have
substantial advantages over complicated ones in design and
implementation, cells in a systolic system are typically
interconnected to form a systolic array or a systolic tree.
Information in a systolic system flows between cells in a
pipelined fashion, and communication with the outside world
occurs only at the “boundary cells.” For example, in a systolic
array, only those cells on the array boundaries may be I/O
ports for the system[5]. The basic principle of a systolic
© 2011 ACEEE 42
DOI: 01.IJIT.01.01.120](https://image.slidesharecdn.com/120-120913004908-phpapp01/85/FIR-Filter-Implementation-by-Systolization-using-DA-based-Decomposition-1-320.jpg)
![ACEEE Int. J. on Information Technology, Vol. 01, No. 01, Mar 2011
where
for l = 0, 1, …. , L-1 and p = 0, 1, …. , P-1.
The bit vector (bn)l,p in Eq. (4b) is used as address word
for the lookup table and F is the memory-read operation.
III.1-D SYSTOLIC ARRAY FOR FIR FILTERS
A linear array consisting of P number of PEs and an output
cell is shown in Fig. 1 and the function of the PEs is described
in Fig. 1(b)[3].
From the data presented in Table 1 and from the
Figures 2 to 5 it can be seen that for a given filter order N,
the case for M = 4 yields the most area-time efficient archi-
tecture when compared to the case for M = 2 and 8. This can
be explained by the fact that the increase in control logic
and number of delay elements outweighs the gains made by
reduction of LUT size for M = 2, while for M = 8, the memory
requirement of LUTs is too high [1].Frequency is also maxi-
mum for lower orders. Power consumption is the lowest.
Figure. 1. The 1-D array for DA-based implementation of FIR filter: (a)
Linear systolic array; (b) function of PE; and (c) function of output cell.
delta stands for a unit delay.
The input sequence {x(n)} is fed to a serial-in parallel-
out input register where content of the register is serially
right shifted by one position and transferred in parallel to
the bit-serial word-parallel converter in every L cycles. The
function of the output cell is shown in Fig. 1(c). After L
cycles, it delivers a desired filter output. The structure will
yield its first filter output (L+P) cycles after the first input is
fed to the first PE, while the successive output becomes
available in every L cycles.
IV.IMPLEMENTATION
This section is concerned with the description of the
implementation of the FIR filter based on conventional and
systolic decomposition of DA-based computation.
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![ACEEE Int. J. on Information Technology, Vol. 01, No. 01, Mar 2011
Figure 11. Plot of variation of Power Consumption with filter order for
existing system generator block and 1-D Decomposition method for L
= 8.
Figure 9. Plot of variation of Frequency with filter order for 1-D
Conventional method and 1-D Decomposition method for L = 8.
Figure 12. Hardware co-simulation of 1-D DA-based Decomposition
method for L = 8.
CONCLUSION
The project presents hardware-efficient designs for
computation of finite digital convolution by address
decomposition of DA-based inner-product computation. The
advantages of DA kind of implementation are its high usable
frequency and minimum gate count. The main advantage is
it overcomes the usage of multipliers. This method uses
adders, LUTs and shift registers.The systolic decomposition
The address length M is taken to be four for the proposed implementation. scheme is found to offer a flexible choice of the address
From the above shown Table 3 it is clear that the 1- length of the lookup tables (LUT) for DA-based computation.
D systolic decomposition method significantly outperforms The 1-D systolic array provides reduction in ROM size and
the existing implementations in terms of two important key the number of adders by several orders of magnitude
metrics, namely the frequency and power consumption for compared to the conventional method.
all the values of N.
REFERENCES
[1] P. K. Meher, Shrutisagar Chandrasekaran and Abbes Amira,
“FPGA realization of FIR filters by efficient and flexible
systolization using distributed arithmetic”, IEEE Trans. signal
process., vol. 56, no. 7, pp. 3009-3017, July 2008.
[2] B.K.Mohanty, P.K.meher “Cost effective novel flexible cell-
level systolic architecture for high throughput implementation
of 2D FIR filters” IEE 1996. Technical note.
[3] P. K. Meher, “Hardware-efficient systolization of DA-based
calculation of finite digital convolution”, IEEE Trans. Circuits
Syst. II, Exp. Briefs, vol. 53, no. 8, pp. 707–711, Aug. 2006.
[4] S. A. White, “Applications of the distributed arithmetic to digital
signal processing: A tutorial review”, IEEE ASSP Mag., vol.
6, no. 3, pp. 5–19, Jul. 1989.
[5] H. T. Kung, “Why systolic architectures?”, IEEE Computer,
Figure 10. Plot of variation of Frequency with filter order for existing
vol. 15, no. 1, pp. 37–45, Jan. 1982.
system generator block and 1-D Decomposition method for L = 8. [6] R. Wyrzykowski and S. Ovramenko, “Flexible systolic
architecture for VLSI FIR filters”, IEE Proceedings-E,
vol.139,no.2,March1992
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DOI: 01.IJIT.01.01.120](https://image.slidesharecdn.com/120-120913004908-phpapp01/85/FIR-Filter-Implementation-by-Systolization-using-DA-based-Decomposition-4-320.jpg)
FIR Filter Implementation by Systolization using DA-based Decomposition
- 1. ACEEE Int. J. on Information Technology, Vol. 01, No. 01, Mar 2011 FIR Filter Implementation by Systolization using DA-based Decomposition Shreeharsha K G, Rekha Bhandarkar Department of Electronics and Communication Engineering Alva’s Institute of Engineering and Technology, Mijar – 574 225, Moodbidri, INDIA [email protected] Rekha Bhandarkar Department of Electronics and Communication Engineering NMAM Institute of Technology, Nitte – 574 110 Karkala, INDIA [email protected] Abstract– In this paper we present 1D and 2D systolic architecture, array in particular, is replacing a single Distributed Arithmetic (DA) based structures that are designed Processing Element (PE) with an array of PEs or cells. Being for the implementation of Finite Impulse Response (FIR) filters. able to use each input data item a number of times (and thus The paper compares the 1D DA based systolic structure with achieving high computation throughput with only modest 1D systolic DA based decomposition method. The filters are memory bandwidth) is one of the advantages of the systolic implemented on a Xilinx Virtex II Pro (XC2VP30) FPGA using approach. They have several attractive features such as HDL and system metrics like Area, Gate Count, Maximum Usable Frequency and Power consumption are estimated for simplicity, regularity and modularity of structure [2]. In different filter orders and address lengths. The 1D systolic addition, they also possess significant potential to yield high- decomposition structure is also compared with the existing throughput rate by exploiting high-level of concurrency using system generator implementation of DA FIR.. Results for an pipelining or parallel processing or both. exemplary implementation are presented. II.DISTRIBUTED ARITHMETIC Keywords— Distributed arithmetic (DA), Field Programmable Gate Arrays (FPGA), Finite Impulse Response (FIR) filter, Distributed Arithmetic (DA) is an efficient method for systolic array. computing inner products when one of the input vectors is fixed[4]. It uses look-up tables and accumulators instead of I.INTRODUCTION multipliers for computing inner products. Let us consider the inner-product of two N-point vectors Finite Impulse Response (FIR) filters are one of the most A and B given by Eq. (1) as, common components of Digital Signal Processing (DSP) systems. FIR filtering is achieved by convolving the input data samples with the desired unit response of the filter. Since the complexity of implementation grows with the filter order and the precision of computation, real-time realization of these filters with desired level of accuracy is a challenging task. Several attempts have, therefore, been made to develop dedicated and reconfigurable architectures for realization of FIR filters in Application Specific Integrated Circuits (ASIC) and FPGA platforms. DA provides an approach for multiplier-less implementation of FIR filters where the filter coefficients are programmable. In other words, the same filter structure can be used for a different set of coefficients. A systolic system consists of a set of interconnected cells, each capable of performing some simple operation. Because simple, regular communication and control structures have substantial advantages over complicated ones in design and implementation, cells in a systolic system are typically interconnected to form a systolic array or a systolic tree. Information in a systolic system flows between cells in a pipelined fashion, and communication with the outside world occurs only at the “boundary cells.” For example, in a systolic array, only those cells on the array boundaries may be I/O ports for the system[5]. The basic principle of a systolic © 2011 ACEEE 42 DOI: 01.IJIT.01.01.120
- 2. ACEEE Int. J. on Information Technology, Vol. 01, No. 01, Mar 2011 where for l = 0, 1, …. , L-1 and p = 0, 1, …. , P-1. The bit vector (bn)l,p in Eq. (4b) is used as address word for the lookup table and F is the memory-read operation. III.1-D SYSTOLIC ARRAY FOR FIR FILTERS A linear array consisting of P number of PEs and an output cell is shown in Fig. 1 and the function of the PEs is described in Fig. 1(b)[3]. From the data presented in Table 1 and from the Figures 2 to 5 it can be seen that for a given filter order N, the case for M = 4 yields the most area-time efficient archi- tecture when compared to the case for M = 2 and 8. This can be explained by the fact that the increase in control logic and number of delay elements outweighs the gains made by reduction of LUT size for M = 2, while for M = 8, the memory requirement of LUTs is too high [1].Frequency is also maxi- mum for lower orders. Power consumption is the lowest. Figure. 1. The 1-D array for DA-based implementation of FIR filter: (a) Linear systolic array; (b) function of PE; and (c) function of output cell. delta stands for a unit delay. The input sequence {x(n)} is fed to a serial-in parallel- out input register where content of the register is serially right shifted by one position and transferred in parallel to the bit-serial word-parallel converter in every L cycles. The function of the output cell is shown in Fig. 1(c). After L cycles, it delivers a desired filter output. The structure will yield its first filter output (L+P) cycles after the first input is fed to the first PE, while the successive output becomes available in every L cycles. IV.IMPLEMENTATION This section is concerned with the description of the implementation of the FIR filter based on conventional and systolic decomposition of DA-based computation. © 2011 ACEEE 43 DOI: 01.IJIT.01.01.120
- 3. ACEEE Int. J. on Information Technology, Vol. 01, No. 01, Mar 2011 The above shown Table 2 is the comparison results of filters of different orders for 1-D systolic conventional method and 1-D systolic decomposition method. The decomposition method is better in all metrics for all values of N, as seen from the graphs shown in Figure 6 to 9. The synthesis tool used is Xilinx ISE 9.2i. The simulation tool used is ModelSim XE 6.2c. The target device selected is Virtex II Pro (XC2VP30). Figure 2. Plot of variation of Area with filter order for 1-D Decomposition method for L = 8. Figure 6. Plot of variation of Area with filter order for 1-D Conventional method and 1-D Decomposition method for L = 8. Figure 3. Plot of variation of Frequency with filter order for 1-D Decomposition method for L = 8. Figure 7. Plot of variation of Power Consumption with filter order for 1- D Conventional method and 1-D Decomposition method for L = 8. Figure 4. Plot of variation of Power Consumption with filter order for 1- D Decomposition method for L = 8. Figure 5. Plot of variation of Gate Count with filter order for 1-D Figure 8. Plot of variation of Gate Count with filter order for 1-D Decomposition method for L = 8. Conventional method and 1-D Decomposition method for L = 8. © 2011 ACEEE 44 DOI: 01.IJIT.01.01.120
- 4. ACEEE Int. J. on Information Technology, Vol. 01, No. 01, Mar 2011 Figure 11. Plot of variation of Power Consumption with filter order for existing system generator block and 1-D Decomposition method for L = 8. Figure 9. Plot of variation of Frequency with filter order for 1-D Conventional method and 1-D Decomposition method for L = 8. Figure 12. Hardware co-simulation of 1-D DA-based Decomposition method for L = 8. CONCLUSION The project presents hardware-efficient designs for computation of finite digital convolution by address decomposition of DA-based inner-product computation. The advantages of DA kind of implementation are its high usable frequency and minimum gate count. The main advantage is it overcomes the usage of multipliers. This method uses adders, LUTs and shift registers.The systolic decomposition The address length M is taken to be four for the proposed implementation. scheme is found to offer a flexible choice of the address From the above shown Table 3 it is clear that the 1- length of the lookup tables (LUT) for DA-based computation. D systolic decomposition method significantly outperforms The 1-D systolic array provides reduction in ROM size and the existing implementations in terms of two important key the number of adders by several orders of magnitude metrics, namely the frequency and power consumption for compared to the conventional method. all the values of N. REFERENCES [1] P. K. Meher, Shrutisagar Chandrasekaran and Abbes Amira, “FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic”, IEEE Trans. signal process., vol. 56, no. 7, pp. 3009-3017, July 2008. [2] B.K.Mohanty, P.K.meher “Cost effective novel flexible cell- level systolic architecture for high throughput implementation of 2D FIR filters” IEE 1996. Technical note. [3] P. K. Meher, “Hardware-efficient systolization of DA-based calculation of finite digital convolution”, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 8, pp. 707–711, Aug. 2006. [4] S. A. White, “Applications of the distributed arithmetic to digital signal processing: A tutorial review”, IEEE ASSP Mag., vol. 6, no. 3, pp. 5–19, Jul. 1989. [5] H. T. Kung, “Why systolic architectures?”, IEEE Computer, Figure 10. Plot of variation of Frequency with filter order for existing vol. 15, no. 1, pp. 37–45, Jan. 1982. system generator block and 1-D Decomposition method for L = 8. [6] R. Wyrzykowski and S. Ovramenko, “Flexible systolic architecture for VLSI FIR filters”, IEE Proceedings-E, vol.139,no.2,March1992 © 2011 ACEEE 45 DOI: 01.IJIT.01.01.120