Group 1_FinFET Final.pptx

Contents:
 Invention History
 Why FinFET
 Structure of FinFET
 Planar MOSFET vs FinFET
 FinFET Classifications
 Geometric parameters of FinFET
 Current equations
 Characteristics
 Fabrication
 Advantages & Disadvantages
 Applications
 Various gate structures for FET
 State of Art
 Future of FinFET
2

 In 1999, Chenming Hu crammed a record number of
transistors onto a chip with his invention of “FinFET,”
short for Fin Field Effect Transistor.
Invention Of Finfet
1998 – N-channel FinFET (17 nm)
1999 – P-channel FinFET
2001 – 15 nm FinFET
2002 – 10 nm FinFET
2004 – High-κ/metal gate FinFET
Reference: FinFET [Online]. Available: https://en.wikipedia.org/wiki/FinFET
3

Moore's law:
the number of transistors on a microchip doubles every two years.
Reference: Moore’s law [Online]. Available: https://en.wikipedia.org/wiki/Moore%27s_law
4

Why FinFET?
 At a point of scaling MOSFET, short channel effects show up.
 Shift of Vth (DIBL)
 Sub threshold slope (SS) degrades
 Off current (Ioff) Increases
 So overall performance degrades.
 FinFET is a way to overcome this problem & continue scaling.
Reference: Impact of quantum effects on the short channel effects of III–V nMOSFETs in weak and strong inversion regimes
[Online]. Available: https://www.sciencedirect.com/science/article/abs/pii/S003811011300169X
5

Reference: 1506 Samsung SLSI 14nm FinFET

Planar MOSFET vs FinFET
• One gate, so less control
over channel
• More leakage current
• Two gates, so more control
over channel
• Very less leakage current
Reference: FinFET Physics [Online]. Available: https://www.mksinst.com/n/finfet-physics
7

It is common for a single FinFET transistor to
contain several fins, arranged side by side and
all covered by the same gate, that act
electrically as one, to increase drive strength
and performance.
Reference: A Review Paper on CMOS, SOI and FinFET Technology [Online]. Available: https://www.design-
reuse.com/articles/41330/cmos-soi-finfet-technology-review-paper.html

FinFET Classification:
SG FinFET:
• Having 3 Terminals
• Higher Ion & Ioff
• Require lesser area
IG FinFET:
• Having 4 Terminals
• Vth modulation is possible
• Require more area
1. Shorted gate FinFET & Insulated gate FinFET
Reference: FinFETs: From Devices to Architectures [Online]. Available: https://www.hindawi.com/journals/aelc/2014/365689/
9

SOI FinFET:
• ∆Hfin ↓
• Expensive
• Lesser Heat Dissipation
Bulk FinFET:
• ∆Hfin↑
• Less Expensive
• Higher Heat Dissipation
• Parasitic BJT
2. SOI FinFET & Bulk FinFET
Reference: Compairing FinFETs: SOI Vs Bulk: Process variability, process cost, and device performance [Online]. Available:
https://www.semanticscholar.org/paper/Compairing-FinFETs%3A-SOI-Vs-Bulk%3A-Process-process-Deshmukh-
Khanzode/8303e7d5bdcc8187b15af29da595f6e33e04a2dd
10

Geometric Parameters of FinFET
• The electrical width of a FinFET is twice the height plus the width.
• FinFET exhibits a property known as width quantization: its width is a multiple
of its height. Random widths are not possible.
Reference: www.synopsys.com (By Jamil Kawa, R&D Group Director, Synopsys, Inc.)
11

Calculation of FinFET Transistor Width
• Lg = gate length
• Wfin = fin width
• Hfin = fin height
• W = transistor width (single fin)
• Weff = effective transistor width (multiple fins)
For double-gate: W = 2 ∙ Hfin
For tri-gate: W = 2 ∙ Hfin + Wfin
Multiple fins will increase the transistor width.
Weff = n ∙ W
Where n = number of fins
Reference: www.ieeeexplore.org
12

Current Equations of FinFET for Different Regions
The current equation in saturation region :
Where
Xd = depletion layer thickness
13

Cutoff Region ( Vg < Vt ) :
Linear Region (Vg > Vt) :
Δφ is the work function difference between the gate electrode and the almost intrinsic silicon body.
Drain current following an exponential decompose is referred to as sub threshold current.
Current in Subthreshold region is given as:
14

Characteristics of FinFET
1. Output Characteristic with specifications :
 Lch = 10um,
 Wfin = 150nm,
 tsi = 30nm
• Upto pinch off voltage, drain current increases
with drain voltage.
• After pinch off voltage, no effect of drain
voltage over drain current
Reference: A Qualitative Approach on FinFET Devices Characteristics Md.Alamgir hossain,student of Dhaka University of Engineering &
Technology
15

2. Transfer Characteristics :
Fig. Transfer characteristics of FinFet with
specifications :
 Lch = 10um,
 Wfin = 150nm,
 tsi = 30nm
Fig. Ids − Vgs characteristics obtained from the analytic
model for two different values of tfin (solid and dashed
curves), compared with the 2D numerical simulation
results (symbols). The same currents are plotted on
both logarithmic (left) and linear (right) scales. A
constant mobility of 300 cm−2 V−1 sec−1 is used in
calculations.
Reference: A Qualitative Approach on FinFET Devices Characteristics Md.Alamgir hossain, student of Dhaka University of Engineering &
Technology
16

3. Sub threshold Current for specifications :
 Lch = 10um,
 Wfin = 150nm,
 tsi = 30nm
This figure indicate the Subthreshold
current of n‐Channel FinFET where
current is flowing although threshold
voltage has not crossed.
Fig. Subthreshold current of FinFet
Reference: A Qualitative Approach on FinFET Devices Characteristics Md.Alamgir hossain, student of Dhaka University of
Engineering & Technology
17

4. Effective mobility vs Effective field
 This figure indicates the two
components that contribute to the
effective mobility degradation.
 Coulomb scattering (uc ) at low field
rise sharply whereas phonon
scattering(uph ) at high field fall
gradually.
 For uc , effective mobility ueff rise at
low value of Eeff but after certain value
of Eeff, it goes straightly due to phonon
scattering.
Fig. Effective mobilities versus effective field for 10μm n-channel
FinFET and tsi =30nm.
Reference: Electrical Characteristics Of Trigate Finfet By M. Zakir Hossain, Md.Alamgir Hossain, Md.Saiful Islam, Md. Mijanur Rahman, Mahfuzul
Haque Chowdhury, Dhaka University of Engineering & Technology
18

Fabrication of FinFET:
Step 1 Step 3
Step 2
Step 5 Step 7
Step 6
Step 4
19

ADVANTAGES
 Better control over the channel
 Suppressed short-channel effects
 Lower static leakage current
 Faster switching speed
 Higher drain current (More drive-current per footprint)
 Lower switching voltage
 Low power consumption
20

DISADVANTAGES
 Difficult to control dynamic Vth
 Quantized device-width. It is impossible to make fractions of the fins, whereby
designers can only specify the devices’ dimensions in multiples of whole fins.
 Higher parasitic due to 3-D profile
 Very high capacitances
 Corner effect: electric field at the corner is always amplified compared to the
electric field at the sidewall. This can be minimized using a nitrate layer in corners.
 High fabrication cost
21

APPLICATIONS
 Used in Microprocessors and Microcontrollers.
 Used in Compact Chip.
 Used in Dielectric films.
 Used in power electronics and radio-frequency (RF) applications.
 Used in motor drives and grid inverters.
 FinFETs have a wide range of applications from high-end performance-critical
computing to energy-constraint mobile applications and smart Internet-of-Things
(IoT) devices.
 Its applications include home computers, laptops, tablets, smartphones, wearables,
high-end networks, automotive, and more.
22

Various Gate structures for FET
Tri-gate FinFET
Double-gate
FinFET
Reference: FinFET Evolution [Online]. Available: https://eepower.com/technical-articles/what-is-a-finfet/#
23

STATE OF ART
 In theory, FinFETs are expected to scale to 5nm as defined by Intel. (A fully-scaled
5nm process is roughly equivalent to 3nm from the foundries). Regardless of the
confusing node names, the FinFET likely will run out of steam when the fin width
reaches 5nm. So at 5nm or beyond, chipmakers will need a new solution.
Otherwise, traditional chip scaling will slow down or stop completely.
24

Reference : https://semiengineering.com/transistor-options-beyond-3nm/ (by Mark Lapedus, Executive Editor for manufacturing at
Semiconductor Engineering.)
25

Reference: https://sites.ji.sjtu.edu.cn/xinfei-guo/wp-content/uploads/sites/27/2021/05/pdf.pdf
26

FUTURE OF FINFET
 The taller a building, the more complex the support structure needs to be. It’s the same for fins on
a FET.
 FinFETs with the physical gate length being aggressively shrunk down to 10 nm and the fin width
down to 12 nm.
 In short, they will migrate to whichever path offers them better performance for the lowest price
with a solid roadmap for future revs.
27

References
 [1] FinFET [Online]. Available: https://en.wikipedia.org/wiki/FinFET
 [2] Moore’s law [Online]. Available: https://en.wikipedia.org/wiki/Moore%27s_law
 [3] Impact of quantum effects on the short channel effects of III–V nMOSFETs in weak and strong inversion regimes [Online]. Available:
https://www.sciencedirect.com/science/article/abs/pii/S003811011300169X
 [4] 1506 Samsung SLSI 14nm FinFET
 [5] FinFET Physics [Online]. Available: https://www.mksinst.com/n/finfet-physics
 [6] A Review Paper on CMOS, SOI and FinFET Technology [Online]. Available: https://www.design-reuse.com/articles/41330/cmos-soi-finfet-
technology-review-paper.html
 [7] FinFETs: From Devices to Architectures [Online]. Available: https://www.hindawi.com/journals/aelc/2014/365689/
 [8] Compairing FinFETs: SOI Vs Bulk: Process variability, process cost, and device performance [Online]. Available:
https://www.semanticscholar.org/paper/Compairing-FinFETs%3A-SOI-Vs-Bulk%3A-Process-process-Deshmukh-
Khanzode/8303e7d5bdcc8187b15af29da595f6e33e04a2dd
 [9] www.synopsys.com (By Jamil Kawa, R&D Group Director, Synopsys, Inc.)
 [10] www.ieeeexplore.org
 [11] A Qualitative Approach on FinFET Devices Characteristics Md.Alamgir hossain,student of Dhaka University of Engineering & Technology
 [12] Electrical Characteristics Of Trigate Finfet By M. Zakir Hossain, Md.Alamgir Hossain, Md.Saiful Islam, Md. Mijanur Rahman, Mahfuzul Haque
Chowdhury, Dhaka University of Engineering & Technology
 [13] https://semiengineering.com/transistor-options-beyond-3nm/
 [14] https://sites.ji.sjtu.edu.cn/xinfei-guo/wp-content/uploads/sites/27/2021/05/pdf.pdf
28

Group 1_FinFET Final.pptx

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Group 1_FinFET Final.pptx