3. Input/Output(I/O)
The computer system’s I/O architecture is its interface to the outside world. This
architecture is designed to provide a systematic way of controlling interaction with the
outside world and to provide the operating system with the information it needs to
manage I/O activity effectively.
There are three principal I/O techniques:
Programmed I/O: in which I/O occurs under he direct and continuous control of
the program requesting the I/O operation.
Interrupt-driven I/O: in which a program issues an I/O command and then
continues to execute, until it is interrupted by the I/O hardware to signal the end of
the I/O operations.
Direct memory access (DMA): in which a specialized I/O processor takes over
control of an I/O operation to move a large block of data.
4. Model of an I/O Module
Computer system is a set of I/O modules.
Each module interfaces to the system bus or
central switch and controls one or more
peripheral devices. An I/O module is not sim-
ply a set of mechanical connectors that wire a
device into the system bus. Rather, the
I/O module contains logic for performing a
communication function between the pe-
ripheral and the bus.
The main purposes of I/O module are:
Interface to the processor and memory via
the system bus or control switch.
Interface to one or more peripheral devices
Control and timing
Data buffering
Error detection
5. I/O Device Interface
An I/O device is connected to the
interconnection network by using a circuit,
called the device interface, which is used for
data transfer and for the exchange of status and
control information needed to facilitate the data
transfers and governs the operation of the
device.The interface includes some registers:
Data register: Serves as a buffer for data
transfers.
Control register: May store the information
that controls the operational behavior of the
device.
Status register: This register may hold
information about the current status of the
device.
These data, status, and control registers are
accessed by program instructions as if they
were memory locations.
6. I/O Module Structure
Given figure provides a general block diagram of
an I/O module.
The module connects to the rest of the computer
through a set of system bus lines.
This module includes some registers that can be
accessed by the processor.One register may serve
as a buffer for data transfers, another may hold
information about the current status of the
device, and yet another may store the information
that controls the operational behavior of the
device.
The logic within the module interacts with the
processor via a set of control lines.
The processor uses the control lines to issue
commands to the I/O module.the I/O module
contains logic specific to the interface with each
device that it controls.
I/O module may hide device details from the
processor so the processor only functions in
terms of simple read and write operations –
timing, formats, etc…
7. Programmed I/O
Programmed I/O instructions are the result of I/O instructions written in computer program.
Each data item transfer is initiated by the instruction in the program.
Processor executes an I/O instruction by issuing command to appropriate I/O module.
I/O module performs the requested action and then sets the appropriate bits in
the I/O status register – I/O module takes not further action to alert the processor- it does
not interrupt the processor.
The processor periodically checks the status of the I/O module until it determines that the
operation is complete.
Usually the program controls data transfer to and from CPU and peripheral. Transferring
data under programmed I/O requires constant monitoring of the peripherals by the CPU.
In the programmed I/O technique, some I/O commands issued by the processor to the I/O
module,and then from the point of view of the I/O instructions executed by the processor.
These commands are control,test,read and write.
8. I/O Commands
To execute an I/O-related instruction, the processor issues an address, specifying
the particular I/O module and external device, and an I/O command.There are four types
of I/O commands:
Control: Used to activate a peripheral and tell it what to do. For example, a magnetic-
tape unit may be instructed to rewind or to move forward one record.
Test: Used to test various status conditions associated with an I/O module and its
peripherals. The processor will want to know if the most recent I/O operation is
completed and if any errors occurred.
Read: Causes the I/O module to obtain an item of data from the peripheral and place
it in an internal buffer i.e. the data register.The processor can then obtain the data item
by requesting that the I/O module place it on the data bus.
Write: Causes the I/O module to take an item of data (byte or word) from the data
bus and subsequently transmit that data item to the peripheral.
9. An example of data transfer from an input out-put
device through an interface into the cpu is described in
the given figure. Consider that it is byte addressable.
When a byte of data is available,the devices places it
in the I/O bus and enables its data valid line.
The interface accepts the byte into its data register
and enables data accepted line.
The device will not transfer another byte until the data
accepted line is disabled by the inteface.
The interface sets a bit in the status register that is
refer to as an F or flag bit, used to determine whether
a byte has been placed in the data register by the I/O
device or not.
If flag=1, CPU reads the data from the data register.
The flag bit is then cleared to 0 either by the CPU or
the interface.
Once the flag is cleared, the interface disables the data
accepted line and the device can then transfer the next
byte.
Interface
Data
Register
Status
Register F
I/O bus
Data
Valid
Data
Accepted
Data bus
Address
bus
I/O read
I/O write
CPU I/O
device
F=Flag bit
Fig: Data Transfer from I/O Device to CPU
Example of Programmed I/O
10. Flowchart for CPU Program to Input Data
Read Data Register
Check Flag bit
Flag
Read Status Register
Transfer Data to Memory
Operation
Complete?
Continue with
Program
0=
=1
No
Yes
A flowchart of the program that must be
written for the CPU is shown in the
given figure. We are assuming that the
device is sending sequence of bytes that
must be stored in memory.Typically
transfer of each byte requires three
instructions:
Read the status register.
Check the status of the flag bit,if it is
not set,branch it to step 1 or branch it
to step 3 if it is set.
Read the data register.
11. Limitations of Programmed I/O
Major limitations of programmed I/O are:
The I/O transfer rate is limited by the speed with which the processor can test and service a
device.
The processor is tied up in managing anI/O transfer; a number of instructions must be executed
for each I/O transfer.
It used only in some low-end microcomputers.
It has single input and single output instruction.
The processor has to wait a long time for the I/O module of concern to be ready for either
reception or transmission of data.
The processor, while waiting, must repeatedly interrogate the status of the I/O module. as a
result, the level of the performance of the entire system is severely degraded.
12. Interrupt-Driven I/O
Interrupt driven I/O overcomes two major limitations of programmed I/O:
Overcomes the processor having to wait long periods of time for I/O modules.
The processor does not have to repeatedly check the I/O module status.
Interrupt driven I/O works as follows:
For the processor to issue an I/O command to a module and then go on to do some other useful
work.
The I/O module will then interrupt the processor to request service when it is ready to
exchange data with the processor.
The processor then executes the data transfer, as before, and then resumes its former
processing.
For example:
For input, the I/O module receives a READ command from the processor.
The I/O module then proceeds to read data in from an associated peripheral.
Once the data are in the module’s data register, the module signals an interrupt to the
processor over a control line.
The module then waits until its data are requested by the processor.
When the request is made, the module places its data on the data bus and is then ready for
another I/O operation.
13. Simple Interrupt Processing
Processor loads new
PC value based on
interrupt
Save remainder of
process state
information
Process interrupt
Restore process state
information
Device controller or
Other system hardware
issues an interrupt
Processor finishes
execution of current
instruction
Processor signals
Acknowledgment of
intrrupt
Processor pushes PSW
and PC onto control
stack
Restore old PSW
and PC
Hardware
Software
14. Interrupt Processing
i. A device driver initiates an I/O request on behalf of a process.
ii. The device driver signals the I/O controller for the proper device, which initiates the
requested I/O.
iii. The device signals the I/O controller that is ready to retrieve input, the output is
complete or that an error has been generated.
iv. The CPU receives the interrupt signal on the interrupt-request line and transfer
control over the interrupt handler routine.
v. The interrupt handler determines the cause of the interrupt, performs the
necessary processing and executes a “return from” interrupt instruction.
vi. The CPU returns to the execution state prior to the interrupt being signaled.
vii. The CPU continues processing until the cycle begins again.
15. Design Issues of Interrupt-Driven I/O
There are two main problems for interrupt I/O, which are:
There are multiple I/O modules, how should the processor determine the device that
issued the interrupt signal?
How does the processor decide which module to process when multiple interrupts
have occurred?
There are four main ways to counter these problems, which are:
Multiple Interrupt Lines
Software Poll
Daisy Chain (Hardware Poll, Vectored)
Bus Arbitration (Vectored)
16. Design Issues Cont...
Multiple Interrupt Lines:
It provides multiple interrupt lines between the processor and the I/O modules.
This allows multiple modules to be handled at the same time.
However, it is not practical to assign many bus lines and processor pins to interrupt lines. One
of the reasons is that there might be more than one I/O module attached to a single line. This
defeats the purpose of this technique.
Software Poll:
Whenever an interrupt is detected by the processor, it branches to an interrupt service routine
which will poll each and every I/O module to determine the exact interrupting module.
The processor raises a poll which could be in the form of a command line.
Consequently, the address of the respective I/O module which is interacted by the poll will be
placed on the address line.
The module will respond positively if it is responsible for setting the interrupt.
On the other hand, every I/O module has an addressable status register. This register can be
read by the processor to determine the interrupting module. After that, the processor is then
branched to a specific device-service routine.
17. Design Issues Cont...
Daisy Chain (Hardware Poll, Vectored):
It is actually a hardware poll.
The interrupt acknowledge line is daisy chained to all the modules.
Whenever there is an interrupt, the processor send out an interrupt acknowledge which will
propagate throughout the series of I/O modules.
This process will continue until it reaches a requesting module. The module will respond by
placing a word on the data lines. The word is known as vector. This vector can either be the
address of the module or a specific identifier.
The processor subsequently directs the module to its’ specific device-service routine based on
its’ vector. This technique is also known as the vectored interrupt. It completely removes the
need for interrupt-service routine.
Bus Arbitration (Vectored):
The last method which also utilizes vectored interrupts.
This method involves the I/O module gaining control over the bus before requesting for the
interrupt.
This is limited to only one module at a time.
The processor sends an acknowledge signal whenever it detects an interrupt. The requesting
module then places its’ vector on the data lines.
18. Direct Memory Access
There are two major drawbacks of interrupt driven I/O:
The I/O transfer rate is limited by the speed with which the processor can test and
service a device.
The processor is tied up in managing an I/O transfer; a number of instructions must
be executed for each I/O transfer.
However if a block of data is to be transferred, using simple programmed I/O, the
processor is dedicated to the task of I/O and can move data at a rather high rate.
Interrupt I/O frees up the processor to some extent at the expense of the
I/O transfer rate.
When large volumes of data are to be moved, a more efficient technique is re-
quired: direct memory access (DMA).
DMA transfers the block of data between the memory and peripheral devices of the
system, without the participation of the processor. The unit that controls the activity
of accessing memory directly is called a DMA controller.
19. Direct Memory Access Diagram
Data
Count
Data
Register
Address
Register
Control
Logic
Data Lines
Address Lines
Request to DMA
Acknowledge from DMA
Interrupt
Rrad
Write
Whenever processor is requested to read or write a block of data,
i.e. transfer a block of data, it instructs the DMA controller by
sending the following information.
The first information is whether the data has to be read from
memory or the data has to be written to the memory. It passes
this information via read or write control lines that is between
the processor and DMA controllers control logic unit.
The processor also provides the starting address
of/ for the data block in the memory, from where
the data block in memory has to be read or where
the data block has to be written in memory. DMA
controller stores this in its address register.
The processor also sends the word count, i.e. how
many words are to be read or written. It stores
this information in the data count or the
word count register.
The most important is the address of I/O device
that wants to read or write data. This information
is stored in the data register.
20. DMA Controller Data Transfer
Processor DMA
Controller
I/O
Device
Memory
I/OWR DRQ DACK
HLDA
HLD
MRW
DMA controller is a hardware unit that allows I/O devices
to access memory directly without the participation of the
processor.
1. Whenever an I/O device wants to transfer the data to or
from memory, it sends the DMA request (DRQ) to the
DMA controller. DMA controller accepts this DRQ and
asks the CPU to hold for a few clock cycles by sending it
the Hold request (HLD).
2. CPU receives the Hold request (HLD) from DMA
controller and relinquishes the bus and sends the Hold
acknowledgement (HLDA) to DMA controller.
3. After receiving the Hold acknowledgement (HLDA),
DMA controller acknowledges I/O device (DACK) that
the data transfer can be performed and DMA controller
takes the charge of the system bus and transfers the data
to or from memory.
4. When the data transfer is accomplished, the DMA raise
an interrupt to let know the processor that the task of
data transfer is finished and the processor can take control
over the bus again and start processing where it has left.
21. Data Transfer Mode of DMA Controller
The DMA controller transfers the data in three modes:
Burst Mode: Here, once the DMA controller gains the charge of the system bus,
then it releases the system bus only after completion of data transfer. Till then the
CPU has to wait for the system buses.
Cycle Stealing Mode: In this mode, the DMA controller forces the CPU to stop its
operation and relinquish the control over the bus for a short term to DMA
controller. After the transfer of every byte, the DMA controller releases the bus and
then again requests for the system bus. In this way, the DMA controller steals the
clock cycle for transferring every byte.
Transparent Mode: Here, the DMA controller takes the charge of system bus only
if the processor does not require the system bus.
22. Direct Memory Access Advantages and Disadvantages
Advantages:
Transferring the data without the involvement of the processor will speed up the
read-write task.
DMA reduces the clock cycle requires to read or write a block of data.
Implementing DMA also reduces the overhead of the processor.
Disadvantages:
As it is a hardware unit, it would cost to implement a DMA controller in the system.
Cache coherence problem can occur while using DMA controller.
23. Bus Organization
Micropr-
ocessor
Unut
(MPU)
Adress Bus
Data Bus
Control Bus
Memory Input Output
A bus organization is a group of conducting wires which
carries information, all the peripherals are connected to
microprocessor through the bus.
The MPU (Micro Processing Unit) performs primarily
four operations:
Memory Read: Read data (or instructions) from
memory.
Memory Write: Write data (or instructions) into
memory.
I/O Read: Accepts data from I/P devices.
I/O Write: Sends data to O/P devices.
Types of Bus in the microprocessor are: Control
Bus,Data Bus and Address Bus.
Control Bus: The control bus is used for sending control
signals to the memory and I/O devices. The CPU sends
control signal on the control bus to enable the outputs of
addressed memory devices or I/O port devices.
Some of the control bus signals are as follows:
Memory read,Memory write,I/O read and I/O write.
24. Bus Organization Cont...
Micropr-
ocessor
Unut
(MPU)
Adress Bus
Data Bus
Control Bus
Memory Input Output
Address Bus:
The address bus carries information about the location of
data in the memory. The addresses bus is unidirectional
because of data flow in one direction, from the
microprocessor to memory or from the microprocessor to
input/out devices. Length of Address bus of 8085
microprocessor is 16 bit (That is, four hexadecimal
digits), ranging from 0000H to FFFF H. The
microprocessor 8085 can transfer maximum 16-bit
address which means it can address 65,536 different
memory location i.e 64KB memory.
Data Bus:
The data bus allows data to travel between the
microprocessor (CPU) and memory (RAM). The data bus
is bidirectional because of data flow in both directions,
from the microprocessor to memory or input/output
devices and from memory or input/output devices to
microprocessors. Length of Databus of 8085
microprocessor is 8 bit (that is, two hexadecimal Digits0,
ranging from 00H to FF H.
25. Secondary Storage
Used in computer system to overcome limitations of primary storage like limited
capacity,volatileness,etc.
Has virtually unlimited capacity because cost per bit of storage is very low.
Has an operating speed far slower than the primary storage.
Used to store large volume of data on permanent basis.
It is also called as auxiliary memory.
Classification of secondary storage are as follows:
Sequential Access Direct Access
Magnetic Tape
Magnetic Disk
Optical Disk
Flash Drive/
Memory Card
Secondary Storage
26. Sequential & Direct Access
Sequential Access:
Arrival at the desired storage location may be preceded by sequencing by other
location.
Data can only be retrieved in the same sequence in which it is stored.
Access time varies according to the storage location of the information being
accessed.
Suitable for sequential processing applications where most,if not all, of the data
records need to be processed one after another.
Magnetic tape is a typical example of such a storage device.
Direct Access:
Devices where any storage location may be selected and accessed at random.
Permits access to individual information in a more direct or immediate manner.
Approximately equal access time is required for accessing information from any
storage location.
Magnetic, optical, and magneto-optical disks are typical examples of such a
storage device.
27. Magnetic Tape
In magnetic tape only one side of the ribbon is used for storing data.
It is sequential memory which contains thin plastic ribbon to store data and coated by
magnetic oxide.
Data on the tape are structured as a number of parallel tracks running lengthwise.
It is highly reliable which requires magnetic tape drive writing and reading data.
The recording of data in this form is referred to as parallel recording. Most modern systems
instead use serial recording, in which data are laid out as a sequence of bits along each track.
The typical recording technique used in serial tapes is referred to as serpentine recording. In
this technique, when data are being recorded, the first set of bits is recorded along the whole
length of the tape. When the end of the tape is reached, the heads are repositioned to record a
new track, and the tape is again recorded on its whole length, this time in the opposite
direction. That process continues, back and forth, until the tape is full.
Data read/write speed is slower because of sequential access.
Disadvantages :
Sequential access is the disadvantage, means it does not allow access randomly or directly.
It requires caring to store, i.e., vulnerable humidity, dust free, and suitable environment.
It stored data cannot be easily updated or modified, i.e., difficult to make updates on data.
28. Magnetic Disk
Commonly used direct-access secondary storage device.
Physically, a magnetic disk is a thin, circular plate/platter made of metal or plastic that is
usually coated on both sides with a magnetizable recording material such as iron-oxide.
Data are recorded on the disk in the form of tiny invisible magnetized and non-magnetized
spots (representing 1s and 0s) on the coated surfaces of the disk.
The disk is stored in a specially designed protective envelope or cartridge, or several of them
are stacked together in a sealed, contamination-free container.
Improvement in the uniformity of the magnetic film surface to increase disk reliability.
A significant reduction in overall surface defects to help reduce read-write errors.
Greater ability to withstand shock and damag.
.
29. Data Organization and Formatting in Disk
A disk’s surface is divided into a number of invisible
concentric circles called tracks.
The tracks are numbered consecutively from
outermost to innermost starting from zero.
Adjacent tracks are separated by gaps. This prevents,
or at least minimizes, errors due to misalignment of
the head or simply interference of magnetic fields.
Each track of a disk is subdivided into sectors.
There are typically hundreds of sectors per track, and
these may be of either fixed or variable length.
To avoid imposing unreasonable precision
requirements on the system, adjacent sectors are
separated by intra-track (inter-sector) gaps.
Disk address represents the physical location of the
record on the disk.
It is comprised of the sector number, track number,
and surface number (when double-sided disks are
used).
30. Disk Storage Organization
Central Shaft
Upper Surface
(Not used)
Surface 0
Surface 1
Surface 2
Surface 3
Surface 4
Surface 5
Lower Surface
(Not used)
Cylinder
Read/Write
Head
Direction of
Movement of
access arm
assembly
Access arm
assembly
In this example,
No. of disk platters = 4 and
No. of usable surfaces=6
A set of corresponding tracks on all the 6
surfaces is called a cylinder..
Storage capacity of a disk system = Number
of recording surfaces * Number of tracks per
surface * Number of sectors pe rtrack *
Number of bytes per sector
31. Disk Access Mechanism
Disk access time: Disk access time is the interval between the instant a computer makes a
request for transfer of data from a disk system to the primary storage and the instant this
operation is completed.
Disk access time depends on the following three parameters:
Seek Time: It is the time required to position the read/write head over the desired track, as
soon as a read/write command is received by the disk unit.
Latency: It is the time required to spin the desired sector under the read/write head, once the
read/write head is positioned on the desired track.
Transfer Rate: It is the rate at which data are read/written to the disk, once the read/write head
is positioned over the desired sector.
Average access time= avg seek time + avg latency time + transfer time
Typically, avg latency time=1/2(rotational delay)
32. Flash Drives
Pen Drives or Thumb drives or Flash drives are the recently emerged portable storage media. It
is an EEPROM based flash memory which can be repeatedly erased and written using electric
signals. This memory is accompanied with a USB connector which enables the pendrive to
connect to the computer. They have a capacity smaller than a hard disk but greater than a CD.
Pendrive has following advantages:
Transfer Files:
A pen drive being plugged into a USB port of the system can be used as a device to transfer
files, documents and photos to a PC and also vice versa. Similarly, selected files can be
transferred between a pen drive and any type of workstation.
Portability:
The lightweight nature and smaller size of a pen drive make it possible to carry it from place
to place which makes data transportation an easier task.
Backup Storage:
Most of the pen drives now come with a feature of having password encryption, important
information related to family, medical records and photos can be stored on them as a backup.
Transport Data:
Professionals/Students can now easily transport large data files and video/audio lectures on a
pen drive and gain access to them from anywhere. Independent PC technicians can store
work-related utility tools, various programs and files on a high-speed 64 GB pen drive and
move from one site to another.
33. Asynchronous Data Transfer Methods
Asynchronous data transfer enables computers to send and receive data without
having to wait for a real-time response. With this technique, data is conveyed in
discrete units known as packets that may be handled separately.
Terminologies used in Asynchronous Data Transfer
1. Sender: The machine or gadget that transfers the data.
2. Receiver: A device or computer that receives data.
3. Packet: A discrete unit of transmitted and received data.
4. Buffer: A short-term location for storing incoming or departing data.
35. Strobe Control Method
The Strobe Control method of asynchronous data transfer employs a single control line to time each
transfer. This control line is also known as a strobe, and it may be achieved either by source or destination,
depending on which initiate the transfer.
•Source initiated strobe: In the block diagram, we can see
that strobe is initiated by source, and as shown in the timing
diagram, the source unit first places the data on the data
bus. After a brief delay to ensure that the data resolve to a
stable value, the source activates a strobe pulse. The
information on the data bus and strobe control signal
remains in the active state for a sufficient time to allow the
destination unit to receive the data.
The destination unit uses a falling edge of strobe control to
transfer the contents of a data bus to one of its internal
registers. The source removes the data from the data bus
after it disables its strobe pulse. Thus, new valid data will
be available only after the strobe is enabled again.
In this case, the strobe may be a memory-write control
signal from the CPU to a memory unit. The CPU places the
word on the data bus and informs the memory unit, which
is the destination.
36. Destination Initiated Strobe
In the block diagram, we see that the strobe
initiated by destination, and in the timing
diagram, the destination unit first activates the
strobe pulse, informing the source to provide the
data.
The source unit responds by placing the
requested binary information on the data bus.
The data must be valid and remain on the bus
long enough for the destination unit to accept it.
The falling edge of the strobe pulse can use
again to trigger a destination register. The
destination unit then disables the strobe. Finally,
and source removes the data from the data bus
after a determined time interval.
In this case, the strobe may be a memory read
control from the CPU to a memory unit. The
CPU initiates the read operation to inform the
memory, which is a source unit, to place the
selected word into the data bus.
37. Handshaking Method
•The strobe method has the disadvantage that the source unit that initiates the transfer has
no way of knowing whether the destination has received the data that was placed in the bus.
Similarly, a destination unit that initiates the transfer has no way of knowing whether the
source unit has placed data on the bus.
•So this problem is solved by the handshaking method. The handshaking method introduces
a second control signal line that replays the unit that initiates the transfer.
•In this method, one control line is in the same direction as the data flow in the bus from the
source to the destination. The source unit uses it to inform the destination unit whether there
are valid data in the bus.
•The other control line is in the other direction from the destination to the source. This is
because the destination unit uses it to inform the source whether it can accept data. And in it
also, the sequence of control depends on the unit that initiates the transfer. So it means the
sequence of control depends on whether the transfer is initiated by source and destination.
38. Source Initiated Handshaking
In the block diagram, we can see that two handshaking
lines are "data valid", which is generated by the source
unit, and "data accepted", generated by the destination
unit.
The timing diagram shows the timing relationship of
the exchange of signals between the two units. The
source initiates a transfer by placing data on the bus
and enabling its data valid signal. The destination unit
then activates the data accepted signal after it accepts
the data from the bus.
The source unit then disables its valid data signal,
which invalidates the data on the bus.
After this, the destination unit disables its data
accepted signal, and the system goes into its initial
state. The source unit does not send the next data item
until after the destination unit shows readiness to
accept new data by disabling the data accepted signal.
This sequence of events described in its sequence
diagram, which shows the above sequence in which
the system is present at any given time.
39. Destination Initiated Handshaking
In the block diagram, we see that the two
handshaking lines are "data valid", generated by
the source unit, and "ready for data" generated
by the destination unit.
Note that the name of signal data accepted
generated by the destination unit has been
changed to ready for data to reflect its new
meaning.
The destination transfer is initiated, so the
source unit does not place data on the data bus
until it receives a ready data signal from the
destination unit. After that, the handshaking
process is the same as that of the source
initiated.
The sequence of events is shown in its sequence
diagram, and the timing relationship between
signals is shown in its timing diagram.
Therefore, the sequence of events in both cases
would be identical.
40. Advantages & Disadvantages of Asynchronous
Data Transfer
Advantages:
1. It is more flexible, and devices can exchange information at their own pace. In addition,
individual data characters can complete themselves so that even if one packet is corrupted,
its predecessors and successors will not be affected.
2. It does not require complex processes by the receiving device. Furthermore, it means that
inconsistency in data transfer does not result in a big crisis since the device can keep up
with the data stream. It also makes asynchronous transfers suitable for applications where
character data is generated irregularly.
Disadvantages:
3. The success of these transmissions depends on the start bits and their recognition.
Unfortunately, this can be easily susceptible to line interference, causing these bits to be
corrupted or distorted.
4. A large portion of the transmitted data is used to control and identify header bits and thus
carries no helpful information related to the transmitted data. This invariably means that
more data packets need to be sent.
41. References
“Computer Organization and Design:The Hardware/Software Interface” by David A Patterson and John L
Hennessy.
“Computer Architecture and Organization” by John P Hayes.
“Computer Organization and Architecture: Designing for Performance” by William Stallings
“COMPUTER ORGANIZATION AND EMBEDDED SYSTEMS” by Carl Hamacher and et. al.
Computer System Architecture” by Morris Mano.
https://www.ecs.csun.edu/~cputnam/Comp546/Input-Output-Web.pdf
http://inputoutput5822.weebly.com/programmed-io.html
https://www.coursehero.com/file/p79r3bn/Drawbacks-of-Programmed-and-Interrupt-Driven-IO-Both-forms-
of-IO-suffer-from/
https://www.eng.auburn.edu/~nelsovp/courses/elec5260_6260/slides/Chapter3%20IO.pdf
https://www.hzu.edu.in/csit/Secondary%20Storage%20%20computer%20fundamentals.pdf
https://bcisnotes.com/thirdsemester/computer-architecture-and-microprocessor/bus-organization-
introduction-to-microprocessor-bcis-notes/#:~:text=A%20bus%20organization%20is%20a,of%20wires
