![FPGA Implementation Of Cordic Algorithm For Pipelined FFT Realization
And Finger Print Recognition
Mr.SANTHOSH K P Mr. RAVISIMHA B N Dr. M Z KURIAN
Dept. of ECE Dept. of ECE HOD, Dept. of ECE
Sri Siddhartha Institute of Technology Sri Siddhartha Institute of Technology Sri Siddhartha Institute of Technology
Tumkur Karnataka, India Tumkur Karnataka, India Tumkur Karnataka, India
santhoshkpraj@gmail.com Ravisimhabn@gmail.com mzkurianbc.@yahoo.com
ABSTRACT: The Radix-2 FFT algorithm used as a FFT
compute DFT in a fast and efficient manner . For twiddle factor
calculation, Co-ordinate Rotation Digital Computer (CORDIC)
algorithm is used, which helps to reduce the computation time
and make processor faster. The CORDIC provides the
opportunity to calculate all the required functions in a simple
fashion. This paper deals with an efficient CORDIC pipelined
FFT for finger print recognition on FPGA.
KEYWORDS:FFT, Radix-2, CORDIC, FPGA.
INTRODUCTION
The CORDIC gives the unified solution for a large set of
computational tasks involving the evaluation of trigonometric
functions, calculation of multiplication, division, square-root
and logarithm, solution of linear systems, QR-decomposition,
and SVD, etc. Moreover, CORDIC is implemented by a
simple hardware through repeated shift-add operations. and
also it is inherently suitable for pipelined designs, due to its
iterative behavior, and small cycle time compared with the
conventional arithmetic. For high throughput applications,
efficient pipelined-architectures with multiple-CORDIC units
could be developed to take the advantage of pipeline ability of
CORDIC, because the digital hardware is getting cheaper
along with the progressive device-scaling. Another way to use
CORDIC efficiently, is to transform the computational
algorithm into independent segments, and to implement the
individual segments by different CORDIC processors. With
enhancement of its throughput and reduction of latency, it is
expected that CORDIC would be useful for many high-speed
and real-time applications.
The FFT plays an important role for extracting the features.
The idea is to reduce the Computational complexity of FFT.
This is achieved by implementing CORDIC processor for
FFT. In this paper we propose hardware efficient CORDIC
FFT and finger print recognition which minimizes the
computational complexity[1][3].
In general, the ROTATION and VECTORING operations
should be considered constant-length routines in which the
number of word times per operation is equal to the word
length. Similar algorithms have been developed for
multiplication, division, conversion between binary and
mixed radix systems, extractions of square root, hyperbolic
coordinate trans formations, exponentiation and generation of
logarithms. It is believed that similar algorithms based on this
for many other computing requirements.
In FFT processors, butterfly operation is the most
computationally demanding stage. Traditionally, a butterfly
unit is composed of complex adders and multipliers, and the
multiplier is usually the speed bottleneck in the pipeline of the
FFT processor. The CORDIC algorithm is an alternative
method to realize the butterfly operation without using any
dedicated multiplier hardware. CORDIC algorithm is very
versatile and hardware efficient since it requires only add and
shift operations, making it very suitable for the butterfly
operations in FFT. Instead of storing actual twiddle factors in
a ROM, the CORDIC-based FFT processor needs to store
only the twiddle factor angles in a ROM for the butterfly
operation. Additionally, the CORDIC-based butterfly can be
twice faster than traditional multiplier-based butterflies in
VLSI implementations[3][4].
ISBN:978-1534910799
www.iaetsd.in
Proceedings of ICAER-2016
©IAETSD 201625](https://image.slidesharecdn.com/iaetsdfpgaimplementationofcordicalgorithmforpipelinedfftrealizationand-160630055208/85/Iaetsd-fpga-implementation-of-cordic-algorithm-for-pipelined-fft-realization-and-1-320.jpg)
![CORDIC Theory
The CORDIC is very simple and iterative convergence
algorithm that reduces complex multiplication, greatly
simplifying overall hardware complexity. This gives attractive
option to system designers as they continue to face the
challenges of minimizing the cost and power targets with the
increased performance. The basic principle underlying the
CORDIC-based computation, and present its iterative
algorithm for different operating modes and planar coordinate
system[7].
All of the trigonometric functions can be computed or derived
from functions using vector rotations, which will be discussed
in the following sections. Vector rotation can also be used for
polar to rectangular and rectangular to polar conversions, for
vector magnitude, and as a building block in certain
transforms such as the DFT and DCT. The CORDIC
algorithm provides an iterative method of performing vector
rotations by arbitrary angles using only shifts and adds
operations.
Fig 1.Rotation of two dimensional vector
As shown in Fig 1, the rotation of a Two-dimensional
vector p0=[x0 y0] through an angle θ to obtain a rotated vector
pn= [xn yn] could be performed by the matrix product pn=R.p0
where R is the rotation matrix:
R= …… (1)
By factoring out the cosine term in (1), the rotation matrix R
can be rewritten as
R=[(1+tan2
𝜃)-1/2
] …………… . .(2)
and can be interpreted as a product of a scale-factor
K=[(1+tan2
𝜃)-1/2
] with a pseudo rotation matrix Rc,given by
RC= ……………… …. (3)
The pseudo rotation operation rotates the vector p0 by an
angle𝜃 and changes its magnitude by a factor K=cos𝜃 to
produce a pseudo-rotated vector p’n= Rcp0
To achieve simplicity of hardware realization of the rotation,
the key ideas used in CORDIC arithmetic are to (i)
decompose the rotations into a sequence of elementary
rotations through predefined angles that could be
implemented with minimum hardware cost; and (ii) to avoid
scaling, that might involve arithmetic operation, such as
square-root and division. The second idea is based on the
scale-factor contains only the magnitude information but no
information about the angle of rotation[5][8].
Generalized Block Diagram
The proposed architecture is designed using the butterfly
structure using CORDIC, angle generator, ram, multiplexer,
demultiplexer and registers. This architecture (Fig 2) can be
classified into input block, core block and output block. The
input block will have the ram, demultiplexer, register and
multiplexer arrangement, input for the system is going to be
binary data input. Input block will have a RAM where the
data will be saved by incremental addressing and that data
will enter in to the demux unit, output of demux unit is saved
in the register. The register chosen for saving the data is
based on the select line of the demux, output of the register
are applied to the muxing unit. The multiplexer unit will
produce input for the core block[6][7].
The core block consists of the butterfly structure
of the FFT which is designed using the CORDIC algorithm to
replace the complex multipliers. An angle generator is used to
generate the twiddle factor angle for rotation to the pipe-lined
CORDIC structure. The core block will be designed for the
radix 2 and radix-4 FFT structure. The output from the core
block also will have the demux - mux arrangement with
registers, the data output will be stored before sending the
data out.
ISBN:978-1534910799
www.iaetsd.in
Proceedings of ICAER-2016
©IAETSD 201626](https://image.slidesharecdn.com/iaetsdfpgaimplementationofcordicalgorithmforpipelinedfftrealizationand-160630055208/85/Iaetsd-fpga-implementation-of-cordic-algorithm-for-pipelined-fft-realization-and-2-320.jpg)
![Input
core black
output
Figure 2: General block diagram for FFT.
FFT Design In CORDIC
The Discrete Fourier transform(DFT) converts a time-
domain sequence into an equivalent frequency-domain
sequence. The inverse discrete Fourier transform performs the
reverse operation and converts a frequency-domain sequence
into an equivalent time-domain sequence. The fast Fourier
transform (FFT) is a very efficient algorithm technique based
on the discrete Fourier transform but with fewer computations
required. The FFT is one of the most commonly used
operations in digital signal processing to provide a frequency
spectrum analysis. Two different procedures are introduced to
compute an FFT: the decimation-in-frequency and the
decimation-in-time.
Decimation in Frequency DIF –FFT algorithm
The Decimation-In-Frequency(DIF) radix-2 FFT partitions
the DFT computation into even-indexed and odd-indexed
outputs it is shown in figure 3, which can each be computed
by shorter-length DFTs of different combinations of input
samples. Recursive application of this decomposition to the
shorter-length DFTs results in the full radix-2 decimation-in-
time FFT.
Figure 3 : SFG of Computation of 8 point DFT using DIF FFT
The decimation, however, causes shuffling in data. The
entire process involves v = log2 N stages of decimation, where
each stage involves N/2 butterflies of the type shown in the
Figure 4.
Figure 4:Butterfly structure
Here WN = e –j 2 / N,
is the Twiddle factor.
Consequently, the computation of N-point DFT via this
algorithm requires (N/2) log2 N complex
multiplications[1][2].
Conclusion
The architecture is dedicated to the computation
of trigonometric and arctangent functions. Nevertheless, it can
be adapted to all functions by reprogramming the FPGA. The
module uses radix-2 number representation, this leads to
small circuits by replacing the costly multiplications by a
small number of additions. The obtained operators provide
very small average error. In that way this algorithm suitable
for FFT and finger print recognition.
References
[1] Dr.P Malathi and Dr Manisha sharma " Pipelined cordic
architecture for FFT processors implementation on FPGA"
IJAREEEIE,2015.
[2] George Joseph ana Vijyakumar K " Variants of cordic for
trigonomatric function and its applications",ISSN 2091-2730,2015.
Input block
Butterfly structure
Angle generator
Output block
ISBN:978-1534910799
www.iaetsd.in
Proceedings of ICAER-2016
©IAETSD 201627](https://image.slidesharecdn.com/iaetsdfpgaimplementationofcordicalgorithmforpipelinedfftrealizationand-160630055208/85/Iaetsd-fpga-implementation-of-cordic-algorithm-for-pipelined-fft-realization-and-3-320.jpg)
![[3] Yidong Liu and Lihang Fan " A modified cordic FPGA
implementation for wave generation" springer science business media
New york,2013.
[4] Yasodai A and Ramprasad A " A new memory reduced radix-4
cordic processor for FFT operation " IOSR-JVSP ,2013.
[5] Hunny Pahuja, Lavish Kansal and Paramdeep Singh " Cordic
algorithm implementation in FPGA computation of sine
and cosine signals " international journal of scientific and
engineering research,2011.
[6] Ramanpreeth and Parminder Singh Jassal " FPGA implementation of
cordic algorithm architecture " international journal of
scientific knowlegde,2011.
[7] Leena vachani and Promod k.mehor " Efficient
cordic algorithm and architecture for low area and high
throughput implementation" IEEE,2009.
[8] Volder, J.," The CORDIC Trigonometric Computing Technique," IRE
Trans. Electronic Computing, Vol EC-8, pp330-334 Sept
1959.
.
ISBN:978-1534910799
www.iaetsd.in
Proceedings of ICAER-2016
©IAETSD 201628](https://image.slidesharecdn.com/iaetsdfpgaimplementationofcordicalgorithmforpipelinedfftrealizationand-160630055208/85/Iaetsd-fpga-implementation-of-cordic-algorithm-for-pipelined-fft-realization-and-4-320.jpg)
Iaetsd fpga implementation of cordic algorithm for pipelined fft realization and
- 1. FPGA Implementation Of Cordic Algorithm For Pipelined FFT Realization And Finger Print Recognition Mr.SANTHOSH K P Mr. RAVISIMHA B N Dr. M Z KURIAN Dept. of ECE Dept. of ECE HOD, Dept. of ECE Sri Siddhartha Institute of Technology Sri Siddhartha Institute of Technology Sri Siddhartha Institute of Technology Tumkur Karnataka, India Tumkur Karnataka, India Tumkur Karnataka, India [email protected] [email protected] [email protected] ABSTRACT: The Radix-2 FFT algorithm used as a FFT compute DFT in a fast and efficient manner . For twiddle factor calculation, Co-ordinate Rotation Digital Computer (CORDIC) algorithm is used, which helps to reduce the computation time and make processor faster. The CORDIC provides the opportunity to calculate all the required functions in a simple fashion. This paper deals with an efficient CORDIC pipelined FFT for finger print recognition on FPGA. KEYWORDS:FFT, Radix-2, CORDIC, FPGA. INTRODUCTION The CORDIC gives the unified solution for a large set of computational tasks involving the evaluation of trigonometric functions, calculation of multiplication, division, square-root and logarithm, solution of linear systems, QR-decomposition, and SVD, etc. Moreover, CORDIC is implemented by a simple hardware through repeated shift-add operations. and also it is inherently suitable for pipelined designs, due to its iterative behavior, and small cycle time compared with the conventional arithmetic. For high throughput applications, efficient pipelined-architectures with multiple-CORDIC units could be developed to take the advantage of pipeline ability of CORDIC, because the digital hardware is getting cheaper along with the progressive device-scaling. Another way to use CORDIC efficiently, is to transform the computational algorithm into independent segments, and to implement the individual segments by different CORDIC processors. With enhancement of its throughput and reduction of latency, it is expected that CORDIC would be useful for many high-speed and real-time applications. The FFT plays an important role for extracting the features. The idea is to reduce the Computational complexity of FFT. This is achieved by implementing CORDIC processor for FFT. In this paper we propose hardware efficient CORDIC FFT and finger print recognition which minimizes the computational complexity[1][3]. In general, the ROTATION and VECTORING operations should be considered constant-length routines in which the number of word times per operation is equal to the word length. Similar algorithms have been developed for multiplication, division, conversion between binary and mixed radix systems, extractions of square root, hyperbolic coordinate trans formations, exponentiation and generation of logarithms. It is believed that similar algorithms based on this for many other computing requirements. In FFT processors, butterfly operation is the most computationally demanding stage. Traditionally, a butterfly unit is composed of complex adders and multipliers, and the multiplier is usually the speed bottleneck in the pipeline of the FFT processor. The CORDIC algorithm is an alternative method to realize the butterfly operation without using any dedicated multiplier hardware. CORDIC algorithm is very versatile and hardware efficient since it requires only add and shift operations, making it very suitable for the butterfly operations in FFT. Instead of storing actual twiddle factors in a ROM, the CORDIC-based FFT processor needs to store only the twiddle factor angles in a ROM for the butterfly operation. Additionally, the CORDIC-based butterfly can be twice faster than traditional multiplier-based butterflies in VLSI implementations[3][4]. ISBN:978-1534910799 www.iaetsd.in Proceedings of ICAER-2016 ©IAETSD 201625
- 2. CORDIC Theory The CORDIC is very simple and iterative convergence algorithm that reduces complex multiplication, greatly simplifying overall hardware complexity. This gives attractive option to system designers as they continue to face the challenges of minimizing the cost and power targets with the increased performance. The basic principle underlying the CORDIC-based computation, and present its iterative algorithm for different operating modes and planar coordinate system[7]. All of the trigonometric functions can be computed or derived from functions using vector rotations, which will be discussed in the following sections. Vector rotation can also be used for polar to rectangular and rectangular to polar conversions, for vector magnitude, and as a building block in certain transforms such as the DFT and DCT. The CORDIC algorithm provides an iterative method of performing vector rotations by arbitrary angles using only shifts and adds operations. Fig 1.Rotation of two dimensional vector As shown in Fig 1, the rotation of a Two-dimensional vector p0=[x0 y0] through an angle θ to obtain a rotated vector pn= [xn yn] could be performed by the matrix product pn=R.p0 where R is the rotation matrix: R= …… (1) By factoring out the cosine term in (1), the rotation matrix R can be rewritten as R=[(1+tan2 𝜃)-1/2 ] …………… . .(2) and can be interpreted as a product of a scale-factor K=[(1+tan2 𝜃)-1/2 ] with a pseudo rotation matrix Rc,given by RC= ……………… …. (3) The pseudo rotation operation rotates the vector p0 by an angle𝜃 and changes its magnitude by a factor K=cos𝜃 to produce a pseudo-rotated vector p’n= Rcp0 To achieve simplicity of hardware realization of the rotation, the key ideas used in CORDIC arithmetic are to (i) decompose the rotations into a sequence of elementary rotations through predefined angles that could be implemented with minimum hardware cost; and (ii) to avoid scaling, that might involve arithmetic operation, such as square-root and division. The second idea is based on the scale-factor contains only the magnitude information but no information about the angle of rotation[5][8]. Generalized Block Diagram The proposed architecture is designed using the butterfly structure using CORDIC, angle generator, ram, multiplexer, demultiplexer and registers. This architecture (Fig 2) can be classified into input block, core block and output block. The input block will have the ram, demultiplexer, register and multiplexer arrangement, input for the system is going to be binary data input. Input block will have a RAM where the data will be saved by incremental addressing and that data will enter in to the demux unit, output of demux unit is saved in the register. The register chosen for saving the data is based on the select line of the demux, output of the register are applied to the muxing unit. The multiplexer unit will produce input for the core block[6][7]. The core block consists of the butterfly structure of the FFT which is designed using the CORDIC algorithm to replace the complex multipliers. An angle generator is used to generate the twiddle factor angle for rotation to the pipe-lined CORDIC structure. The core block will be designed for the radix 2 and radix-4 FFT structure. The output from the core block also will have the demux - mux arrangement with registers, the data output will be stored before sending the data out. ISBN:978-1534910799 www.iaetsd.in Proceedings of ICAER-2016 ©IAETSD 201626
- 3. Input core black output Figure 2: General block diagram for FFT. FFT Design In CORDIC The Discrete Fourier transform(DFT) converts a time- domain sequence into an equivalent frequency-domain sequence. The inverse discrete Fourier transform performs the reverse operation and converts a frequency-domain sequence into an equivalent time-domain sequence. The fast Fourier transform (FFT) is a very efficient algorithm technique based on the discrete Fourier transform but with fewer computations required. The FFT is one of the most commonly used operations in digital signal processing to provide a frequency spectrum analysis. Two different procedures are introduced to compute an FFT: the decimation-in-frequency and the decimation-in-time. Decimation in Frequency DIF –FFT algorithm The Decimation-In-Frequency(DIF) radix-2 FFT partitions the DFT computation into even-indexed and odd-indexed outputs it is shown in figure 3, which can each be computed by shorter-length DFTs of different combinations of input samples. Recursive application of this decomposition to the shorter-length DFTs results in the full radix-2 decimation-in- time FFT. Figure 3 : SFG of Computation of 8 point DFT using DIF FFT The decimation, however, causes shuffling in data. The entire process involves v = log2 N stages of decimation, where each stage involves N/2 butterflies of the type shown in the Figure 4. Figure 4:Butterfly structure Here WN = e –j 2 / N, is the Twiddle factor. Consequently, the computation of N-point DFT via this algorithm requires (N/2) log2 N complex multiplications[1][2]. Conclusion The architecture is dedicated to the computation of trigonometric and arctangent functions. Nevertheless, it can be adapted to all functions by reprogramming the FPGA. The module uses radix-2 number representation, this leads to small circuits by replacing the costly multiplications by a small number of additions. The obtained operators provide very small average error. In that way this algorithm suitable for FFT and finger print recognition. References [1] Dr.P Malathi and Dr Manisha sharma " Pipelined cordic architecture for FFT processors implementation on FPGA" IJAREEEIE,2015. [2] George Joseph ana Vijyakumar K " Variants of cordic for trigonomatric function and its applications",ISSN 2091-2730,2015. Input block Butterfly structure Angle generator Output block ISBN:978-1534910799 www.iaetsd.in Proceedings of ICAER-2016 ©IAETSD 201627
- 4. [3] Yidong Liu and Lihang Fan " A modified cordic FPGA implementation for wave generation" springer science business media New york,2013. [4] Yasodai A and Ramprasad A " A new memory reduced radix-4 cordic processor for FFT operation " IOSR-JVSP ,2013. [5] Hunny Pahuja, Lavish Kansal and Paramdeep Singh " Cordic algorithm implementation in FPGA computation of sine and cosine signals " international journal of scientific and engineering research,2011. [6] Ramanpreeth and Parminder Singh Jassal " FPGA implementation of cordic algorithm architecture " international journal of scientific knowlegde,2011. [7] Leena vachani and Promod k.mehor " Efficient cordic algorithm and architecture for low area and high throughput implementation" IEEE,2009. [8] Volder, J.," The CORDIC Trigonometric Computing Technique," IRE Trans. Electronic Computing, Vol EC-8, pp330-334 Sept 1959. . ISBN:978-1534910799 www.iaetsd.in Proceedings of ICAER-2016 ©IAETSD 201628