![SC 0 AR PC IR M[AR], PC PC+1 Decode IR(12-14) IR(15), AR IR(0-11) D I I Execute reg. reference Execute I/O reference Execute memory reference Execute memory reference Nothing AR M[AR] =0 Memory reference I/O or reg. reference 1= =1 0= =1 0= I](https://image.slidesharecdn.com/instructioncycle-111228101635-phpapp01/85/Instruction-cycle-11-320.jpg)
![Fetch operation The circuit comprises of various registers, memory unit I/O devices, control and timing unit ALU and a common bus. AR PC IR M[AR], PC PC+1 The instruction read from memory is then placed in the instruction register.](https://image.slidesharecdn.com/instructioncycle-111228101635-phpapp01/85/Instruction-cycle-12-320.jpg)
![Execution Operation If D=0 and IR(15)=0, that means memory reference instruction is direct address instruction. If D=0 and IR(15)=1, that means memory reference instruction is indirect address instruction. AR M[AR], AR holds the address part of the instruction After the instruction is executed, SC is cleared to 0 and control returns to the fetch phase.](https://image.slidesharecdn.com/instructioncycle-111228101635-phpapp01/85/Instruction-cycle-15-320.jpg)
Instruction cycle
- 2. INSTRUCTION Instruction is command which is given by the user to computer.
- 3. Instruction cycle The time period during which one instruction is fetched from memory and execute when a computer given an instruction in machine language. Each instruction is further divided into sequence of phases. After the execution the program counter is incremented to point to the next instruction.
- 4. Phases Fetch an instruction from memory Decode the instruction Execute the instruction
- 5. Fetch cycle In this phase the sequence counter is initialized to 0. The address of first instruction from PC is loaded into address register during the first clock cycle.
- 6. Fetch cycle 0002 Mov AC, 0 Mov AC, 0 0000 0001 0002 0003 IR Decode unit Execute unit PC AC
- 7. Decode cycle The instruction is decoded by the instruction decoder of a processor. All the bits of the instruction under execution stored in IR are analyzed and decode in third clock cycle.
- 8. Decode cycle 0002 Mov AC,0 Mov AC, 0 0000 0001 0002 0003 IR Decode unit Execute unit PC AC
- 9. Execute cycle In the last phase, the processor execute the instruction. This involves setting the contents of the internal register AC to constant value 0.
- 10. Execute cycle 0003 AC 0 Mov AC,0 Mov AC, 0 0000 0001 0002 0003 IR Decode unit Execute unit PC AC
- 11. SC 0 AR PC IR M[AR], PC PC+1 Decode IR(12-14) IR(15), AR IR(0-11) D I I Execute reg. reference Execute I/O reference Execute memory reference Execute memory reference Nothing AR M[AR] =0 Memory reference I/O or reg. reference 1= =1 0= =1 0= I
- 12. Fetch operation The circuit comprises of various registers, memory unit I/O devices, control and timing unit ALU and a common bus. AR PC IR M[AR], PC PC+1 The instruction read from memory is then placed in the instruction register.
- 13. Decode operation In decode operation processor decode the instruction which is fetched from memory. I IR(15), Decode IR(12-14) AR IR(0-11) 0-11 bits in the instruction format are store in the address register. 12-14 bits are decoded. 15 bit is I means direct or indirect address.
- 14. Execution Operation After decoding the instruction, the timing signal that is active. There are three types of instruction:- 1) Memory Reference 2) Register Reference 3) I/O Reference If D=1 and IR(15)=0, that means the instruction is register reference. If d=1 and IR(15)=1, that means the instruction is I/O reference.
- 15. Execution Operation If D=0 and IR(15)=0, that means memory reference instruction is direct address instruction. If D=0 and IR(15)=1, that means memory reference instruction is indirect address instruction. AR M[AR], AR holds the address part of the instruction After the instruction is executed, SC is cleared to 0 and control returns to the fetch phase.
- 16. THANKS