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Intro to Cell Broadband Engine for HPC
- 1. © 2006 IBM Corporation Intro to Cell Broadband Engine for HPC H. Peter Hofstee Cell/B.E. Chief Scientist Cell Broadband Engine is a trademark of Sony Computer Entertainment Inc. IBM Systems and Technology Group
- 2. 2 © 2006 IBM CorporationCell/B.E. for HPC Dealing with the Memory Wall in the Compute Node Manage locality – Cell/B.E. does this explicitly, but applies to nearly every processor once you tune Go very (thread) parallel in the node – Many relatively slow threads so that memory appears closer – IBM BlueGene, Sun Niagra, CRAY XMT, … Prefetch – Generalization of long-vector ( compute is the easy part ) – Cell/B.E. (code and data), old-style CRAY All place a burden on programmers – Automatic caching has its limits – Auto-parallelization has its limits – Automatic pre-fetching / Deep auto-vectorization has its limits All have proven efficiency benefits – BGP and RoadRunner have about same GFlops/W – Both have significantly improved application efficiency on a variety of applications over clusters of conventional processors.
- 3. 3 © 2006 IBM CorporationCell/B.E. for HPC Memory Managing Processor vs. Traditional General Purpose Processor IBM AMD Intel Cell BE
- 4. 4 © 2006 IBM CorporationCell/B.E. for HPC
- 5. 5 © 2006 IBM CorporationCell/B.E. for HPC 2006 2007 2008 2009 2010 Cell BE (1+8) 90nm SOI Cell BE (1+8) 90nm SOI Cost Reduction Path Next Gen (2PPE’+32SPE’) 45nm SOI ~1 TF-SP (est.) Cell Broadband Engine™ Architecture (CBEA) Technology Competitive Roadmap Performance Enhancements/ Scaling Path Enhanced Cell (1+8eDP SPE) 65nm SOI Enhanced Cell (1+8eDP SPE) 65nm SOI Cell eDP chip: To be used in Roadrunner IBM® PowerXCell™ 8i 102.4 GF/s double precision Up to16 GB DDR2 @ 21-25 GB/s PowerXCell is IBM’s name for this new enhanced double- precision (eDP) Cell processor variant All future dates and specifications are estimations only; Subject to change without notice. Dashed outlines indicate concept designs. Continued shrinks Cell/B.E. (1+8) 65nm SOI Cell/B.E. (1+8) 45nm SOI
- 6. 6 © 2006 IBM CorporationCell/B.E. for HPC Boeing 777 iRT Demo Hybrid Configuration Ridgeback memory server (112GB memory) QS21 rendering accelerators (6 Tflops, 14 blades) 350M Triangle model 25GB working set 23000x more complex than today’s game models On demand transfers to blades NFS RDMA over IB Real-time 1080p ray-traced output Compute Hierarchy Head node load balancing blades PPE load balancing SPEs Transparent Memory Hierarchy128GB 2GB 256KB (x86 disk) –> (x86 memory) –> (Cell memory) –> (SPE local store) –> (SPE register file) 120MB/sec 2GB/sec 25GB/sec 50GB/sec http://gametomorrow.com/blog/index.php/2007/11/09/cell-and-the-boeing-777-at-sc07/
- 7. 7 © 2006 IBM CorporationCell/B.E. for HPC A Roadrunner “Triblade” node integrates Cell and Opteron blades QS22 is a future IBM Cell blade containing two new enhanced double- precision (eDP/PowerXCell™) Cell chips Expansion blade connects two QS22 via four internal PCI-E x8 links to LS21 and provides the node’s ConnectX IB 4X DDR cluster attachment LS21 is an IBM dual-socket Opteron blade 4-wide IBM BladeCenter packaging Roadrunner Triblades are completely diskless and run from RAM disks with NFS & Panasas only to the LS21 Node design points: – One Cell chip per Opteron core – ~400 GF/s double-precision & ~800 GF/s single-precision – 16 GB Cell memory & 8 GB Opteron memory Cell eDP Cell eDP HT2100 Cell eDP QS22 2xPCI-E x16 (Unused) HT x16AMD Dual Core LS21 Std PCI-E Connector HSDC Connector (unused) IB 4x DDR PCI-E x8 PCI-E x8 HT x16 HT x16 HT x16 QS22 I/O Hub I/O Hub I/O Hub I/O Hub 2 x HT x16 Exp. Connector Dual PCI-E x8 flex-cable 2xPCI-E x16 (Unused) 2x PCI-E x8 AMD Dual Core Cell eDP Dual PCI-E x8 flex-cable Expansion blade HT2100 IB 4x DDR to cluster 2 x HT x16 Exp. Connector HT x164 GB 4 GB 4 GB 4 GB 4 GB 4 GB 2x PCI-E x8
- 8. 8 © 2006 IBM CorporationCell/B.E. for HPC Roadrunner is a hybrid Cell-accelerated 1.4 PF system of modest size delivered in 2008 18 clusters 3,456 nodes 12 links per CU to each of 8 switches Eight 2nd-stage 288-port IB 4X DDR switches Connected Unit (CU) cluster 180 compute nodes w/ Cells 12 I/O nodes 288-port IB 4x DDR 288-port IB 4x DDR 12,960 Cell eDP chips ⇒ 1.3 PF, 52 TB 6,912 dual-core Opterons ⇒ 50 TF, 28 TB 12,960 Cell eDP chips ⇒ 1.3 PF, 52 TB 6,912 dual-core Opterons ⇒ 50 TF, 28 TB PCI-e attached Cell blades I/O 296 racks 3.9 MW
- 9. 9 © 2006 IBM CorporationCell/B.E. for HPC Roadrunner Entry Level System 12 Hybrid Node Cluster Hybrid Compute Node – 24 - QS22s a future IBM Cell blade containing two new enhanced double-precision IBM® PowerXCell™8i processors – 12 - LS21 an IBM dual-socket Opteron blade – Conneced via four PCI-e x8 links – Includes a ConnectX IB 4X DDR cluster attachment – Compute node is diskless IBM x3655 I/O and Management Servers 4-wide IBM BladeCenter packaging 24 Port IB 4X DDR Switch & Fabric RHEL & Fedora Linux IBM SDK 3.0 for Multicore Acceleration IBM xCAT Cluster Management – System-wide GigEnet network Performance Host Cell Total Peak (TF) 0.35 4.92 5.26 Memory (GB) 96 192 288 Ext IO (GB/s) 1.2
- 10. 10 © 2006 IBM CorporationCell/B.E. for HPC Cell and hybrid speedup results are promising. all comparisons are to a single Opteron core parallel behavior unaffected, as will be shown in the scaling results Cell / hybrid SPaSM implementation does twice the work of Opteron-only code Milagro Cell-only results are preliminary first 3 columns are measured, last column is projected Application Type Cell Only (kernels) Hybrid (Opteron+Cell) CBE eDP CBE+IB eDP+PCIe SPaSM full app 3x 4.5x 2.5x >4x VPIC full app 9x 9x 6x >7x Milagro full app 5x 6.5x 5x >6x Sweep3D kernel 5x 9x 5x >5x Courtesy John Turner, LANL
- 11. 11 © 2006 IBM CorporationCell/B.E. for HPC These results were achieved with a relatively modest level of effort. Code Class Language Lines of code FY07 FTEs Orig. Modified VPIC full app C/C++ 8.5k 10% 2 SPaSM full app C 34k 20% 2 Milagro full app C++ 110k 30% 2 x 1 Sweep3D kernel C 3.5k 50% 2 x 1 all staff started with little or no knowledge of Cell / hybrid programming 2 x 1 denotes separate efforts of roughly 1 FTE each most efforts also added code Courtesy John Turner, LANL
- 12. 12 © 2006 IBM CorporationCell/B.E. for HPC Where can we take Cell/B.E. next? Build bridges to facilitate code porting and code portability – E.g. compiler managed instruction and data caches – Target is competitive chip-level efficiency without Cell-specific software – Still allows full Cell benefit with optimized libraries and tuning – E.g. Multicore (and) Acceleration software development toolkit – Allow a wider audience to write parallel codes for a node – Porting across wide variety of systems Continue to enhance the Synergistic Processor Elements – Continue to increase application reach – Continue to measure ourselves on – application performance/W – application performance/mm2 Integrate the equivalent of a RoadRunner node on a chip – Leverage Power 7 technology – Allows a 10PFlop system of reasonable size – Improved SPE – main core latency and bandwidth – Improved cross-system latencies