IRJET- Design and Simulation of Comparator Architectures for Various ADC Applications
0 likes29 views
This document discusses the design and simulation of different CMOS comparator architectures for analog-to-digital converter applications. It begins by introducing comparators and their use in ADCs. It then describes various comparator topologies including open-loop, regenerative, and cascaded high-speed designs. Simulation results comparing parameters like power, propagation delay, and speed are presented for a two-stage uncompensated comparator, dynamic latch, and high-speed comparator. The high-speed comparator using a cascaded three-stage design with pre-amplification, latch, and post-amplification stages achieved the fastest speed of 84 GHz but at the cost of higher power compared to the regenerative comparator.
1 of 5
Download to read offline
![International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 06 Issue: 05 | May 2019 www.irjet.net p-ISSN: 2395-0072
© 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 5817
Design and Simulation of Comparator Architectures for Various ADC
Applications
Disha Gaude1, Bathini Poornima2, K. M. Sudharshan3, Prashant V. Joshi4
1,2,3,4Dept. of Electronics and communication Engineering, REVA University, Bengaluru, India
----------------------------------------------------------------------***---------------------------------------------------------------------
Abstract - This paper presents design and simulation of
different CMOS comparators. The designs are simulated and
studied in 180 nm Technology with Cadence Virtuoso Tool
with supply voltage 3.3 V and reference voltage of 3V. The
clock used in comparator has a frequency of 1 M Hz. The
comparators are mostly used in converting analog signals to
digital signals for processing. Comparators are used in the
applications requiring less power dissipation, good accuracy
and high resolution.
Key Words: comparator, Dynamic, Static, Latch, Clock
Frequency, Pre amplifier, post amplifier.
Ⅰ. Introduction
Comparator is a circuit which compares two input
voltages in which one is analog input and other is
reference voltage and outputs binary 0 or 1 depending on
comparison. It is basically a 1 bit analog to digital
converter. In ADCs sample and hold circuit samples the
analog input signal and the sampled signal is given to
comparator, depending on reference voltage it produces
digital output which is equivalent to analog input signal
[1].
Comparators are used in all ADCs requiring less power
dissipation, high speed, low noise, less offset voltage, good
slew rate etc. Different types of comparators are available
namely open loop comparator, regenerative comparator
and combination of both open loop and regenerative
comparator (cascaded comparators) [2]. Open loop
compactors are basically single and two stage differential
amplifiers without compensation and feedback loop.
Regenerative comparators use positive feedback to
improve the performance [3]. Comparator circuits can also
be built by separating the comparators into number of
cascaded stages. This helps in reducing the total
propagation delay time and hence can be used in high
speed applications like radar receivers and LAN interfaces.
Fig -1. Symbol of comparator
Above figure shows the symbol of comparator. It is
basically operational amplifier because every comparator
has one or many of the same characteristics as a high gain
amplifier. The voltage Vp applied to the positive terminal of
the comparator gives output 1 if voltage Vn applied to
negative terminal is less or equal to Vp or else the output of
the comparator gives 0 [11].
Ⅱ. Characterization of a comparator
Static characteristics
Gain
The ideal aspect of this model is the way in which the
output makes a transition between VOL and VOH. The output
changes states for an input change of ΔV, where ΔV
approaches zero [4]. The gain is given as
Gain = AV =
Fig -2. Ideal transfer curve
Offset Voltage
A mismatch in the threshold voltages and the trans
conductance parameters of the transistor generates offset
voltage in comparator. If the output did not change until
the input difference reached a value of VOS then the
difference would be defined as the offset voltage [5].](https://image.slidesharecdn.com/irjet-v6i5782-191009051331/85/IRJET-Design-and-Simulation-of-Comparator-Architectures-for-Various-ADC-Applications-1-320.jpg)
![International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 06 Issue: 05 | May 2019 www.irjet.net p-ISSN: 2395-0072
© 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 5818
Fig -3. Transfer curve of a comparator including offset
voltage and noise
Dynamic characteristics
Propagation Delay
Propagation delay is defined as at how much speed the
amplifier responds with applied input [6].
Propagation delay time = (rising propagation delay time +
falling propagation delay time)/2
Fig -4. Propagation delay curve
Ⅲ Comparator Topologies
A. Two stage open loop comparator
Comparator requires differential input and high gain to
achieve desirable resolution. As a result two stage
operational amplifiers can be used as a comparator.
Comparator requires large bandwidth as possible so that
faster response can be achieved. This is done by making
two stage operational amplifiers as an open loop mode,
thus no compensation is required [7].The advantage of
this comparator is to provide high gain, large output
voltage swing and disadvantage is that it consumes more
power. Hence, it is not suitable for high speed and low
power applications.
Fig -5. Open loop comparator
Small signal gain of the comparator as given by
AV = ( ) ( )
Two stage comparator consists of two pole, first and
second stage output poles P1 and P2 respectively are
given as
P1 = -
Where CI is the sum of capacitance connected to the
output of first stage.
P2 =
Where CII is the sum of capacitance connected to the
output of second stage.
B. Regenerative comparator
Regenerative comparators use positive feedback to
accomplish the comparison of two signals. The
regenerative comparator is also called a latch or bistable.
The simplest form of a latch is shown below
Fig -6. NMOS Latch](https://image.slidesharecdn.com/irjet-v6i5782-191009051331/85/IRJET-Design-and-Simulation-of-Comparator-Architectures-for-Various-ADC-Applications-2-320.jpg)
![International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 06 Issue: 05 | May 2019 www.irjet.net p-ISSN: 2395-0072
© 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 5819
Normally, the latch has two modes of operation. The first
mode disables the positive feedback and applies the input
signal to the terminals as V01 and V02. The initial voltages
applied during this mode will be as V01
1 and V01
2. The
second mode enables the latch and depending on the
relative values of V01
1 and V01
2, one of the outputs will go
high and the other will go low. A two phase clock is used to
determine the modes of operation [10].
Fig -7. Dynamic latch
C. High speed comparator
High speed comparators should have a propagation delay
time as small as possible. To achieve this goal, one must
understand the requirement for fast comparator. This is
best understood by separating the comparator into a
number of cascading stages. So, this three cascading stages
consists of input pre amplification stage, latch stage and
output post amplification stage [8].
Pre amplification stage consists of current mirror single
stage differential amplifier with high gain and low slew
rate. This stage improves sensitivity of the comparator by
isolating input from kickback noise and amplifying the
smallest minimum input voltage. Latch is basically positive
feedback circuit which determines the difference of the
two input signals. Post amplification stage consists of self-
biased differential amplifier followed by inverter. This
stage helps in driving the high load and inters parasitic
capacitance [9].
Fig -8. High speed comparator
Ⅵ Simulation Results
Fig -9. Schematic of two stage uncompensated comparator
Fig -10. Output waveforms of two stage uncompensated
comparator
Fig -11. Schematic of dynamic latch
Fig -12. Output waveforms of dynamic latch](https://image.slidesharecdn.com/irjet-v6i5782-191009051331/85/IRJET-Design-and-Simulation-of-Comparator-Architectures-for-Various-ADC-Applications-3-320.jpg)
![International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 06 Issue: 05 | May 2019 www.irjet.net p-ISSN: 2395-0072
© 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 5820
Fig -13. Schematic of high speed comparator
Fig -14. Output waveforms of comparator
Table -1. Comparision of different types of comparator
parameters
Comparator Power
Dissipatio
n [uW]
Propagatio
n Delay [ps]
Speed
[GHz]
Two satge
uncompens
ated
comparator
101.5 57.12 7.507
Regenarativ
e
Comparaor
19.57 186.5 5.3619
High Speed
Comparator
2.121 11.9 84.03
Ⅴ. Conclusion
In this paper two stage uncompensated comparator,
dynamic latch, regenerative comparator and high speed
comparator with cascaded stages are implemented and
simulated and simulation is carried out using Cadence
tools, with gpdk 180nm. It is also verified with LT-SPICE
using tsmc180nm technology file. The power dissipation,
total propagation delay and speed are compared and
calculated for different types of comparators with supply
voltage 5 V.
Ⅵ. Acknowledgement
I am extremely thankful to Dr. Rajashekhar C Biradar,
Director of the school of Electronics and Communication
Engineering, Prof. Prashanth V Joshi coordinator, Mr. H. G.
Yatheesh from VLSI industry for their valuable guidance
and useful suggestions to work effectively with my project.
References
[1] S. Kim and K. Kwon, "A hybrid ADC combining
capacitive DAC-based multi-bit/cycle SAR ADC with flash
ADC," 2016 International Conference on Electronics,
Information, and Communications (ICEIC), Da Nang, 2016.
[2] U. M. Kulkarni, C. Parikh and S. Sen, "A Systematic
Approach to Determining the Weights of the Capacitors in
the DAC of a Non-binary Redundant SAR ADCs," 2018 31st
International Conference on VLSI Design and 2018 17th
International Conference on Embedded Systems (VLSID),
Pune, 2018.
[3] W. Kim et al., "A 0.6 V 12 b 10 MS/s Low-Noise
Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-
SAR) ADC," in IEEE Journal of Solid-State Circuits, vol. 51,
no. 8, pp. 1826-1839, Aug. 2016.
[4] C. Liu, M. Huang and Y. Tu, "A 12 bit 100 MS/s SAR-
Assisted Digital-Slope ADC," in IEEE Journal of Solid-State
Circuits, vol. 51, no. 12, pp. 2941-2950, Dec. 2016.
[5] S. Lee, A. P. Chandrakasan and H. Lee, "A 1 GS/s 10b
18.9 mW Time-Interleaved SAR ADC With Background
Timing Skew Calibration," in IEEE Journal of Solid-State
Circuits, vol. 49, no. 12, pp. 2846-2856, Dec. 2014.
[6] V. P. Singh, G. K. Sharma and A. Shukla, "Power efficient
SAR ADC designed in 90 nm CMOS technology," 2017 2nd
International Conference on Telecommunication and
Networks (TEL-NET), Noida, 2017.
[7] S. Z. Hoseini and K. Lee, "Compact Time-Mode SAR ADC
With Capacitor Flipping Bit-Cycling Operation," 2018 IEEE
61st International Midwest Symposium on Circuits and
Systems (MWSCAS), Windsor, ON, Canada, 2018.
[8] A. Bekal, M. Goswami, B. R. Singh and D. Pal, "A Low
Power 8-Bit Asynchronous SAR ADC Design Using Charge
Scaling DAC," 2014 Fifth International Symposium on
Electronic System Design, Surathkal, 2014.
[9] I. G. Naveen and S. Sonoli, "Design and simulation of
10-bit SAR ADC for low power applications using 180nm
technology," 2016 International Conference on Electrical,
Electronics, Communication, Computer and Optimization
Techniques (ICEECCOT), Mysuru, 2016.](https://image.slidesharecdn.com/irjet-v6i5782-191009051331/85/IRJET-Design-and-Simulation-of-Comparator-Architectures-for-Various-ADC-Applications-4-320.jpg)
![International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 06 Issue: 05 | May 2019 www.irjet.net p-ISSN: 2395-0072
© 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 5821
[10] Yin, G. M., Eynde, F. O., & Sansen, W. (1992). A high-
speed CMOS comparator with 8-bit resolution. IEEE
Journal of Solid-State Circuits.
[11] Donadkar, D. N., & Bhandari, S. U. (2015). Review on
Comparator Design for High Speed ADCs. 2015
International Conference on Computing Communication
Control and Automation.
[12] Babayan-Mashhadi, S., & Lotfi, R. (2014). Analysis and
Design of a Low-Voltage Low-Power Double-Tail
Comparator. IEEE Transactions on Very Large Scale
Integration (VLSI) Systems.
[13] Vinodiya, S. K., & Gamad, R. S. (2017). Analysis and
design of low power, high speed comparators in 180nm
technology with low supply voltages for ADCs. 2017 8th
International Conference on Computing, Communication
and Networking Technologies (ICCCNT).
[14] Fouzy, B. B. A., Reaz, M. B. I., Bhuiyan, M. A. S., Badal,
M. T. I., & Hashim, F. H. (2016). Design of a low-power
high-speed comparator in 0.13μm CMOS. 2016
International Conference on Advances in Electrical,
Electronic and Systems Engineering (ICAEES).
[15] Rangari, A. V., & Gaidhani, Y. A. (2016). Design of
comparator using Domino Logic and CMOS Logic. 2016
Online International Conference on Green Engineering and
Technologies (IC-GET).](https://image.slidesharecdn.com/irjet-v6i5782-191009051331/85/IRJET-Design-and-Simulation-of-Comparator-Architectures-for-Various-ADC-Applications-5-320.jpg)
Ad
Recommended
IRJET- Design and Implementation of High Speed, Low Power Charge Shared R...
IRJET- Design and Implementation of High Speed, Low Power Charge Shared R...IRJET Journal This document presents the design and implementation of a high-speed, low-power charge shared reset method based dynamic latch comparator using 45nm CMOS technology. The proposed comparator architecture uses a charge shared reset technique where the output voltage levels are held at a constant value during the reset phase, allowing for faster comparison during the evaluation phase. This reduces power consumption and delay. The comparator was designed and tested using Cadence Virtuoso 45nm tools. Simulation results show the proposed comparator has a power consumption of 128nW, delay of 22.8ps, and area of 21.56μm2, demonstrating improved performance over existing comparator designs.
IRJET- Modified Cascaded H - Bridge Multilevel Inverter for Household Appliances
IRJET- Modified Cascaded H - Bridge Multilevel Inverter for Household AppliancesIRJET Journal This document describes a study on a modified cascaded H-bridge multilevel inverter for household appliances. The researchers developed a 9-level single phase inverter using 4 H-bridge cells. They used sinusoidal pulse width modulation to generate switching signals and reduce harmonic distortion. Simulations in MATLAB/Simulink showed the output voltage waveform and total harmonic distortion of 9.12%. A hardware prototype was built and tested to verify the design, demonstrating a 53.9V output voltage with 8.22% total harmonic distortion. The modified topology reduces switching losses and improves output capability compared to other multilevel inverter configurations.
IRJET- A Review of Approximate Adders for Energy-Efficient Digital Signal Pro...
IRJET- A Review of Approximate Adders for Energy-Efficient Digital Signal Pro...IRJET Journal The document reviews recent progress in approximate adders for energy-efficient digital signal processing. It summarizes various types of approximate adders that have been proposed, including speculative adders, segmented adders, carry select adders, and adders using approximate full adders. The document provides details on the design and operation of several specific approximate adder circuits. It also compares the delay and area complexity of different approximate adder designs.
IRJET - A Speculative Approximate Adder for Error Recovery Unit
IRJET - A Speculative Approximate Adder for Error Recovery UnitIRJET Journal This document presents a speculative approximate adder for error recovery. The adder is partitioned into non-overlapping blocks whose carries are predicted based on input signals of the current and next blocks. This reduces the critical path delay on average to one block. An error recovery unit is also proposed to further reduce output error rates. Simulation results show the proposed adder achieves lower error rates and error metrics compared to state-of-the-art approximate adders, with only a small increase in delay and area due to the error recovery unit.
IRJET- Accuracy Configurable Adder
IRJET- Accuracy Configurable AdderIRJET Journal This document presents a design for a simple accuracy reconfigurable adder (SARA) to improve the accuracy-power-delay efficiency of approximate adders. SARA is proposed as an alternative to existing accuracy configurable adders that require large areas due to redundancy and error correction circuitry. SARA uses a simple carry prediction approach without redundancy. It is evaluated as part of a 16-bit adder and shown to reduce delay compared to a ripple carry adder. SARA is also applied in an 8x8 Wallace multiplier, demonstrating reduced delay compared to using a ripple carry adder. The proposed SARA design achieves improvements in area, power, and delay efficiency for approximate arithmetic circuits.
IRJET- Modified Perturb and Observe MPPT Algorithm for Drift Avoidance using ...
IRJET- Modified Perturb and Observe MPPT Algorithm for Drift Avoidance using ...IRJET Journal 1. The document presents a modified Perturb and Observe (P&O) MPPT algorithm to avoid drift. The traditional P&O algorithm can drift from the maximum power point during changing weather conditions.
2. The modified algorithm incorporates change in current (dI) in addition to change in voltage and power. This helps identify actual maximum power point during increases in solar irradiance, avoiding drift.
3. The performance of the modified P&O algorithm is evaluated through MATLAB/Simulink simulations and experimental hardware tests. Results show the modified algorithm tracks the maximum power point more accurately without drift, improving efficiency over the traditional P&O method.
IRJET- A Novel Modified Switched Capacitor Nine Level Inverter Topology with ...
IRJET- A Novel Modified Switched Capacitor Nine Level Inverter Topology with ...IRJET Journal The document proposes a new switched-capacitor multilevel inverter topology with reduced switch count that can produce a nine-level staircase output voltage from multiple DC sources. It utilizes asymmetric DC voltage sources from renewable energy farms to reduce the number of inverters needed. The topology inherently solves the capacitor voltage balancing problem and can step up the input voltage without a bulky transformer. It is intended for use in high frequency AC power distribution systems to achieve benefits like smaller component sizes and higher power density. The performance of the proposed topology is evaluated using MATLAB/Simulink.
IRJET- Maximum Power Point Tracking from Pv Panel using Fuzzy Logic Controller
IRJET- Maximum Power Point Tracking from Pv Panel using Fuzzy Logic ControllerIRJET Journal This document discusses maximizing power point tracking from a photovoltaic (PV) panel using a fuzzy logic controller. A 1.1 kW PV panel and boost converter system is designed. A fuzzy logic controller is used to track the maximum power point from the PV panel in order to improve efficiency. The fuzzy logic controller provides a duty cycle input to the boost converter based on the PV panel voltage to transfer maximum power to the load. Simulation results show the output voltage is maintained at 230V with an average efficiency of 98.5% using this system.
IRJET- Single Switched Capacitor High Gain Boost Quasi-Z Source Converter
IRJET- Single Switched Capacitor High Gain Boost Quasi-Z Source ConverterIRJET Journal This document describes a proposed single switched capacitor high gain boost quasi-Z source converter. The converter aims to achieve the benefits of both quasi-Z source converters and switched capacitor converters. It maintains low current stress on the switch, low voltage stress on the diodes at the output, and provides high voltage gain across the load using similar components as other step-up DC-DC converters. Simulation and experimental results are presented to verify the characteristics of the proposed converter, such as achieving maximum efficiencies of 92-94% theoretically and practically.
Development of Multilevel Inverters for Control Applications
Development of Multilevel Inverters for Control ApplicationsIRJET Journal This document discusses the development of multilevel inverters for control applications. It begins by introducing multilevel inverters and their advantages over traditional two-level inverters for high power applications. It then describes the different types of multilevel inverters and compares their characteristics. The document simulates a five-level cascaded H-bridge multilevel inverter using sinusoidal pulse width modulation and analyzes its output waveforms. It then proposes using a neural network controller for the inverter and simulates its performance, showing lower total harmonic distortion compared to the conventional control method.
At044289292
At044289292IJERA Editor This paper discusses the design and analysis of low power CMOS comparators for high-speed analog-to-digital converters (ADCs) using 90nm technology. It reviews various comparator designs, focusing on reducing power consumption and delay while maintaining performance under smaller feature sizes, and provides simulation results that demonstrate significant power reduction. The proposed dynamic latch comparators with inverter buffers show improved efficiency compared to traditional designs.
Analytical model of the half bridge series resonant inverter for improved pow...
Analytical model of the half bridge series resonant inverter for improved pow...LeMeniz Infotech The document presents an analytical model for the half-bridge series resonant inverter, aiming to improve power conversion efficiency and performance by offering a streamlined evaluation of converter operations and losses. It highlights the advantages of lower switching loss, applicability to high-efficiency dc-dc conversion, and suitability for induction heating and contactless energy transfer systems. The study emphasizes the importance of a closed-form expression for better design processes and operational improvements using modern control techniques.
IRJET- Implementation and Analysis of Hybridization in Modified Parallel Adde...
IRJET- Implementation and Analysis of Hybridization in Modified Parallel Adde...IRJET Journal The document compares different types of adder circuits including carry save adders (CSA), carry skip adders (CSkA), carry increment adders (CIA), and modified carry select adders using D-latches. It analyzes the delay, power consumption, and area of hybrid adders that combine elements of different adders, such as a CSA-CSkA hybrid adder and CSA-CIA hybrid adder. Simulation results using Verilog HDL show that the hybrid adders have lower delay, area, or power consumption compared to basic adder circuits. The most efficient adder depends on the specific metrics considered such as being best for lower or higher bit operations.
A Design of Sigma-Delta ADC Using OTA
A Design of Sigma-Delta ADC Using OTAIJERA Editor This document summarizes the design of a sigma-delta analog-to-digital converter (ADC) using operational transconductance amplifiers (OTAs). It first describes the basic architecture of a sigma-delta ADC and the role of the OTA. It then presents the design of a two-stage OTA with sleep insertion and leakage feedback techniques to improve parameters such as gain and power consumption. The design is simulated in 0.18μm CMOS technology with a 1.8V supply. Other blocks of the ADC such as the comparator, 1-bit digital-to-analog converter, and integrator are also described along with simulation results showing improvements in power and performance over earlier designs.
IRJET- Fin FET Two Bit Comparator for Low Voltage, Low Power, High Speed and ...
IRJET- Fin FET Two Bit Comparator for Low Voltage, Low Power, High Speed and ...IRJET Journal This document presents a design for a 2-bit Fin FET comparator for low voltage, low power, high speed, and low area applications in 18nm technology. Simulation results show that the proposed Fin FET comparator reduces dynamic power by 90%, leakage power by 87%, delay by 73%, and area by 60% compared to a conventional design. The Fin FET comparator was designed and simulated using Cadence tools at a supply voltage of 0.5V in 18nm technology. Comparisons of the Fin FET and conventional designs show improvements in power, speed, and area with voltage scaling.
Area Versus Speed Trade-off Analysis of a WiMAX Deinterleaver Circuit Design
Area Versus Speed Trade-off Analysis of a WiMAX Deinterleaver Circuit Designijsrd.com The document discusses a trade-off analysis between area and speed in the design of a WiMAX deinterleaver circuit, emphasizing the need to balance hardware efficiency with performance. It presents findings that speed-optimized designs outperform area-optimized ones, despite minor hardware differences, and provides detailed experimental results comparing various methods. The conclusion advocates for prioritizing speed over area in design decisions due to significant performance advantages.
IRJET- Implementation of Low Power 32-Bit Carry-Look Ahead Adder using Ad...
IRJET- Implementation of Low Power 32-Bit Carry-Look Ahead Adder using Ad...IRJET Journal This document describes the design and implementation of a low power 32-bit carry look ahead adder using adiabatic efficient charge recovery logic (ECRL). ECRL is an adiabatic logic that allows for energy recovery, leading to lower power consumption than conventional CMOS logic. The authors designed inverters, AND, OR, and EX-OR gates as well as 4, 8, 16, and 32-bit carry look ahead adders using ECRL in a 45nm technology. Simulation results showed the ECRL implementations consumed less average power than equivalent static CMOS designs. For example, the 32-bit ECRL carry look ahead adder consumed 36.76μw on average
IRJET- Dynamic Voltage Restorer Frame Work to Improve Power Quality of the Di...
IRJET- Dynamic Voltage Restorer Frame Work to Improve Power Quality of the Di...IRJET Journal This document discusses a proposed framework for integrating ultracapacitors (UCAP) with a dynamic voltage restorer (DVR) to improve power quality on the distribution grid. The DVR compensates for voltage sags and swells by injecting voltage in-phase with the grid. Integrating UCAP provides active power support to handle deeper or longer disturbances without relying solely on the grid. Simulation results show the UCAP-DVR system can maintain constant load voltage during faults by injecting compensating voltage from the UCAP through a bi-directional DC-DC converter and three-phase inverter. This integration improves the DVR's capability to restore voltages during faults on the distribution grid.
krishnaraj CV1
krishnaraj CV1krishnaraj Subramani Mr. Krishnaraj has over 6 years of experience as an electrical design engineer. He has worked on projects in Qatar and India, designing substations from 220kV to 11kV systems. His responsibilities include relay setting calculations, short circuit analysis, cable sizing, preparing design drawings and documentation. He holds a B.E. in Electrical and Electronics Engineering from Mailam Engineering College with over 6 years of experience in electrical substation design.
A high step down multiple output converter with wide input voltage range base...
A high step down multiple output converter with wide input voltage range base...LeMeniz Infotech The document discusses a high step-down multiple output converter utilizing a quasi two-stage architecture and dual-output LLC resonant converter, aimed at applications with a wide input voltage range. It emphasizes the efficiency improvements possible through specific design choices, such as using synchronous rectifiers and a semi-regulation control scheme. Applications highlighted include aerospace, telecommunication, and satellite power systems, along with tools and software used for development.
IRJET- An Inclusive Review on Various Multilevel Converter Topologies for a G...
IRJET- An Inclusive Review on Various Multilevel Converter Topologies for a G...IRJET Journal This document reviews various multilevel inverter topologies that can be used for grid-connected photovoltaic systems. It discusses four main topologies: diode-clamped, flying capacitor, cascaded, and Z-source inverters. For each topology, the document outlines their construction, advantages, and disadvantages when used in renewable energy power systems. It finds that cascaded inverters require fewer components than other topologies but many separate DC sources, while diode-clamped and flying capacitor inverters can share a single DC source but have more complex voltage balancing requirements. The review aims to help selection of the appropriate multilevel inverter topology based on specific system needs and tradeoffs between component counts and control complexity
IRJET- A Implementation of High Speed On-Chip Monitoring Circuit by using SAR...
IRJET- A Implementation of High Speed On-Chip Monitoring Circuit by using SAR...IRJET Journal This document describes the design and implementation of a high-speed on-chip monitoring circuit using a SAR-based comparator. It discusses a 10-bit pipelined analog-to-digital converter that uses a pipeline comparator architecture to achieve high speed and resolution. The design uses dynamic amplifiers in the multiplying digital-to-analog converters to enable high-speed operation even at low supply voltages. A 16-bit prototype achieves 160 MS/s conversion rate at 0.55V supply voltage. The document also reviews various comparator architectures and identifies current-mode algorithmic comparators as well as operating transistors in subthreshold region as promising approaches for achieving very low power consumption suitable for applications such as distributed sensor networks.
IRJET- PV System Connected High Step-Up Boost DC-DC Converter based Voltag...
IRJET- PV System Connected High Step-Up Boost DC-DC Converter based Voltag...IRJET Journal 1. The document presents a photovoltaic (PV) system interfaced with a high step-up DC-DC converter to support the DC link of a dynamic voltage restorer (DVR) and alleviate voltage sags and swells in a low voltage power distribution system.
2. The high step-up DC-DC boost converter uses a coupled inductor design to achieve high voltage gain from the low output of the PV array while maintaining low voltage stress on the power switches. This reduces the size and power rating needed for the series injection transformer.
3. Simulation results show the effectiveness of the proposed PV-supported DVR in mitigating voltage sags and swells in a low voltage single-
Low Power-Area Design of Full Adder Using Self Resetting Logic with GDI Techn...
Low Power-Area Design of Full Adder Using Self Resetting Logic with GDI Techn...VLSICS Design The document discusses the design of a low power full adder circuit using self-resetting logic (SRL) combined with gate diffusion input (GDI) techniques. It highlights the advantages of this approach in terms of reduced power consumption, delay, and overall performance compared to existing full adder designs. Simulation results indicate that the proposed design outperforms traditional CMOS circuits, achieving significant improvements in power efficiency and speed.
[IJET-V1I2P6] Authors :Sarat K Kotamraju, K.Ch.Sri Kavya, A.Gnandeep Reddy, G...
[IJET-V1I2P6] Authors :Sarat K Kotamraju, K.Ch.Sri Kavya, A.Gnandeep Reddy, G...IJET - International Journal of Engineering and Techniques This paper discusses the design of a Ku-band power amplifier using GaN-HEMT technology for defense and aerospace applications, achieving over 10W output power with 42% power added efficiency in the 3-5 GHz frequency range. It addresses the significance of highly efficient power amplifiers and utilizes both schematic and electromagnetic simulations for design analysis. The findings underscore the performance benefits of GaN devices, particularly their high breakdown voltage and efficiency compared to other semiconductor technologies.
IRJET- Total Harmonic Distortion (THD) Compensation Via UPQC using PID Contro...
IRJET- Total Harmonic Distortion (THD) Compensation Via UPQC using PID Contro...IRJET Journal This document discusses using a PID controller to compensate for total harmonic distortion (THD) in a unified power quality conditioner (UPQC). A UPQC uses two voltage source inverters connected back-to-back to compensate for voltage sags/swells and reduce current harmonics and reactive power. The proposed method uses a PID controller to regulate voltage and current parameters and reduce THD. Simulation results show the PID controller reduces THD in the load current to below 5% and regulates the DC bus voltage. The paper concludes the UPQC with PID controller provides effective compensation of current THD.
IRJET- 127 Multilevel Inverter
IRJET- 127 Multilevel InverterIRJET Journal The document describes a proposed 127-level hybrid multilevel inverter topology. Multilevel inverters are useful for medium-voltage high-power applications as they can generate stepped voltage waveforms to reduce harmonic distortion. The proposed topology uses a bypass diode technique and H-bridge configuration to produce 31 voltage levels with only 8 switches and 4 diodes, reducing components compared to other multilevel inverter topologies. The performance of the 31-level inverter is studied using MATLAB/Simulink simulation. A 1 kW hardware prototype is developed to experimentally verify the concept. The proposed topology aims to reduce switching losses and total harmonic distortion in the output waveform.
Performance Evaluation of Personal Ad-hoc Area Network Based on Different Mob...
Performance Evaluation of Personal Ad-hoc Area Network Based on Different Mob...IRJET Journal This document evaluates the performance of a personal ad-hoc area network (PANET) using different node mobility models in a simulation. It simulates four mobility models - Random Waypoint, Reference Point Group, Freeway, and City Section - and compares their performance based on metrics like packet delivery ratio, end-to-end delay, throughput, routing overhead, and data loss. The simulation results show that the freeway mobility model performs better than the others, with the highest packet delivery ratio and one of the lowest end-to-end delays and data losses.
International Journal of Engineering Research and Development
International Journal of Engineering Research and DevelopmentIJERD Editor The document presents a novel design of a low power high speed fully dynamic CMOS latched comparator, which demonstrates a 62% reduction in delay sensitivity, achieving a delay of 0.098ns compared to conventional designs. The proposed comparator leverages a unique architecture that improves gain while maintaining low power consumption and smaller area. Simulation results confirm enhancements in performance against traditional dynamic comparators, marking it a viable option for applications like high-speed analog-to-digital converters.
A1040106
A1040106IJERD Editor This document describes the design of a low power, high speed fully dynamic CMOS latched comparator. It begins with an abstract that outlines the goal of designing a comparator with less sensitivity to delay using a dynamic CMOS latched comparator approach. It then reviews different comparator architectures including open loop, regenerative, and preamplifier-based designs. The focus is on fully dynamic latched comparators, analyzing their advantages and disadvantages. A novel comparator design is proposed that provides better input offset characteristics and faster operation than previous designs like resistor divider, latch-type, and double-tail comparators. The schematic and operating principles of the proposed comparator are described.
More Related Content
What's hot (20)
IRJET- Single Switched Capacitor High Gain Boost Quasi-Z Source Converter
IRJET- Single Switched Capacitor High Gain Boost Quasi-Z Source ConverterIRJET Journal This document describes a proposed single switched capacitor high gain boost quasi-Z source converter. The converter aims to achieve the benefits of both quasi-Z source converters and switched capacitor converters. It maintains low current stress on the switch, low voltage stress on the diodes at the output, and provides high voltage gain across the load using similar components as other step-up DC-DC converters. Simulation and experimental results are presented to verify the characteristics of the proposed converter, such as achieving maximum efficiencies of 92-94% theoretically and practically.
Development of Multilevel Inverters for Control Applications
Development of Multilevel Inverters for Control ApplicationsIRJET Journal This document discusses the development of multilevel inverters for control applications. It begins by introducing multilevel inverters and their advantages over traditional two-level inverters for high power applications. It then describes the different types of multilevel inverters and compares their characteristics. The document simulates a five-level cascaded H-bridge multilevel inverter using sinusoidal pulse width modulation and analyzes its output waveforms. It then proposes using a neural network controller for the inverter and simulates its performance, showing lower total harmonic distortion compared to the conventional control method.
At044289292
At044289292IJERA Editor This paper discusses the design and analysis of low power CMOS comparators for high-speed analog-to-digital converters (ADCs) using 90nm technology. It reviews various comparator designs, focusing on reducing power consumption and delay while maintaining performance under smaller feature sizes, and provides simulation results that demonstrate significant power reduction. The proposed dynamic latch comparators with inverter buffers show improved efficiency compared to traditional designs.
Analytical model of the half bridge series resonant inverter for improved pow...
Analytical model of the half bridge series resonant inverter for improved pow...LeMeniz Infotech The document presents an analytical model for the half-bridge series resonant inverter, aiming to improve power conversion efficiency and performance by offering a streamlined evaluation of converter operations and losses. It highlights the advantages of lower switching loss, applicability to high-efficiency dc-dc conversion, and suitability for induction heating and contactless energy transfer systems. The study emphasizes the importance of a closed-form expression for better design processes and operational improvements using modern control techniques.
IRJET- Implementation and Analysis of Hybridization in Modified Parallel Adde...
IRJET- Implementation and Analysis of Hybridization in Modified Parallel Adde...IRJET Journal The document compares different types of adder circuits including carry save adders (CSA), carry skip adders (CSkA), carry increment adders (CIA), and modified carry select adders using D-latches. It analyzes the delay, power consumption, and area of hybrid adders that combine elements of different adders, such as a CSA-CSkA hybrid adder and CSA-CIA hybrid adder. Simulation results using Verilog HDL show that the hybrid adders have lower delay, area, or power consumption compared to basic adder circuits. The most efficient adder depends on the specific metrics considered such as being best for lower or higher bit operations.
A Design of Sigma-Delta ADC Using OTA
A Design of Sigma-Delta ADC Using OTAIJERA Editor This document summarizes the design of a sigma-delta analog-to-digital converter (ADC) using operational transconductance amplifiers (OTAs). It first describes the basic architecture of a sigma-delta ADC and the role of the OTA. It then presents the design of a two-stage OTA with sleep insertion and leakage feedback techniques to improve parameters such as gain and power consumption. The design is simulated in 0.18μm CMOS technology with a 1.8V supply. Other blocks of the ADC such as the comparator, 1-bit digital-to-analog converter, and integrator are also described along with simulation results showing improvements in power and performance over earlier designs.
IRJET- Fin FET Two Bit Comparator for Low Voltage, Low Power, High Speed and ...
IRJET- Fin FET Two Bit Comparator for Low Voltage, Low Power, High Speed and ...IRJET Journal This document presents a design for a 2-bit Fin FET comparator for low voltage, low power, high speed, and low area applications in 18nm technology. Simulation results show that the proposed Fin FET comparator reduces dynamic power by 90%, leakage power by 87%, delay by 73%, and area by 60% compared to a conventional design. The Fin FET comparator was designed and simulated using Cadence tools at a supply voltage of 0.5V in 18nm technology. Comparisons of the Fin FET and conventional designs show improvements in power, speed, and area with voltage scaling.
Area Versus Speed Trade-off Analysis of a WiMAX Deinterleaver Circuit Design
Area Versus Speed Trade-off Analysis of a WiMAX Deinterleaver Circuit Designijsrd.com The document discusses a trade-off analysis between area and speed in the design of a WiMAX deinterleaver circuit, emphasizing the need to balance hardware efficiency with performance. It presents findings that speed-optimized designs outperform area-optimized ones, despite minor hardware differences, and provides detailed experimental results comparing various methods. The conclusion advocates for prioritizing speed over area in design decisions due to significant performance advantages.
IRJET- Implementation of Low Power 32-Bit Carry-Look Ahead Adder using Ad...
IRJET- Implementation of Low Power 32-Bit Carry-Look Ahead Adder using Ad...IRJET Journal This document describes the design and implementation of a low power 32-bit carry look ahead adder using adiabatic efficient charge recovery logic (ECRL). ECRL is an adiabatic logic that allows for energy recovery, leading to lower power consumption than conventional CMOS logic. The authors designed inverters, AND, OR, and EX-OR gates as well as 4, 8, 16, and 32-bit carry look ahead adders using ECRL in a 45nm technology. Simulation results showed the ECRL implementations consumed less average power than equivalent static CMOS designs. For example, the 32-bit ECRL carry look ahead adder consumed 36.76μw on average
IRJET- Dynamic Voltage Restorer Frame Work to Improve Power Quality of the Di...
IRJET- Dynamic Voltage Restorer Frame Work to Improve Power Quality of the Di...IRJET Journal This document discusses a proposed framework for integrating ultracapacitors (UCAP) with a dynamic voltage restorer (DVR) to improve power quality on the distribution grid. The DVR compensates for voltage sags and swells by injecting voltage in-phase with the grid. Integrating UCAP provides active power support to handle deeper or longer disturbances without relying solely on the grid. Simulation results show the UCAP-DVR system can maintain constant load voltage during faults by injecting compensating voltage from the UCAP through a bi-directional DC-DC converter and three-phase inverter. This integration improves the DVR's capability to restore voltages during faults on the distribution grid.
krishnaraj CV1
krishnaraj CV1krishnaraj Subramani Mr. Krishnaraj has over 6 years of experience as an electrical design engineer. He has worked on projects in Qatar and India, designing substations from 220kV to 11kV systems. His responsibilities include relay setting calculations, short circuit analysis, cable sizing, preparing design drawings and documentation. He holds a B.E. in Electrical and Electronics Engineering from Mailam Engineering College with over 6 years of experience in electrical substation design.
A high step down multiple output converter with wide input voltage range base...
A high step down multiple output converter with wide input voltage range base...LeMeniz Infotech The document discusses a high step-down multiple output converter utilizing a quasi two-stage architecture and dual-output LLC resonant converter, aimed at applications with a wide input voltage range. It emphasizes the efficiency improvements possible through specific design choices, such as using synchronous rectifiers and a semi-regulation control scheme. Applications highlighted include aerospace, telecommunication, and satellite power systems, along with tools and software used for development.
IRJET- An Inclusive Review on Various Multilevel Converter Topologies for a G...
IRJET- An Inclusive Review on Various Multilevel Converter Topologies for a G...IRJET Journal This document reviews various multilevel inverter topologies that can be used for grid-connected photovoltaic systems. It discusses four main topologies: diode-clamped, flying capacitor, cascaded, and Z-source inverters. For each topology, the document outlines their construction, advantages, and disadvantages when used in renewable energy power systems. It finds that cascaded inverters require fewer components than other topologies but many separate DC sources, while diode-clamped and flying capacitor inverters can share a single DC source but have more complex voltage balancing requirements. The review aims to help selection of the appropriate multilevel inverter topology based on specific system needs and tradeoffs between component counts and control complexity
IRJET- A Implementation of High Speed On-Chip Monitoring Circuit by using SAR...
IRJET- A Implementation of High Speed On-Chip Monitoring Circuit by using SAR...IRJET Journal This document describes the design and implementation of a high-speed on-chip monitoring circuit using a SAR-based comparator. It discusses a 10-bit pipelined analog-to-digital converter that uses a pipeline comparator architecture to achieve high speed and resolution. The design uses dynamic amplifiers in the multiplying digital-to-analog converters to enable high-speed operation even at low supply voltages. A 16-bit prototype achieves 160 MS/s conversion rate at 0.55V supply voltage. The document also reviews various comparator architectures and identifies current-mode algorithmic comparators as well as operating transistors in subthreshold region as promising approaches for achieving very low power consumption suitable for applications such as distributed sensor networks.
IRJET- PV System Connected High Step-Up Boost DC-DC Converter based Voltag...
IRJET- PV System Connected High Step-Up Boost DC-DC Converter based Voltag...IRJET Journal 1. The document presents a photovoltaic (PV) system interfaced with a high step-up DC-DC converter to support the DC link of a dynamic voltage restorer (DVR) and alleviate voltage sags and swells in a low voltage power distribution system.
2. The high step-up DC-DC boost converter uses a coupled inductor design to achieve high voltage gain from the low output of the PV array while maintaining low voltage stress on the power switches. This reduces the size and power rating needed for the series injection transformer.
3. Simulation results show the effectiveness of the proposed PV-supported DVR in mitigating voltage sags and swells in a low voltage single-
Low Power-Area Design of Full Adder Using Self Resetting Logic with GDI Techn...
Low Power-Area Design of Full Adder Using Self Resetting Logic with GDI Techn...VLSICS Design The document discusses the design of a low power full adder circuit using self-resetting logic (SRL) combined with gate diffusion input (GDI) techniques. It highlights the advantages of this approach in terms of reduced power consumption, delay, and overall performance compared to existing full adder designs. Simulation results indicate that the proposed design outperforms traditional CMOS circuits, achieving significant improvements in power efficiency and speed.
[IJET-V1I2P6] Authors :Sarat K Kotamraju, K.Ch.Sri Kavya, A.Gnandeep Reddy, G...
[IJET-V1I2P6] Authors :Sarat K Kotamraju, K.Ch.Sri Kavya, A.Gnandeep Reddy, G...IJET - International Journal of Engineering and Techniques This paper discusses the design of a Ku-band power amplifier using GaN-HEMT technology for defense and aerospace applications, achieving over 10W output power with 42% power added efficiency in the 3-5 GHz frequency range. It addresses the significance of highly efficient power amplifiers and utilizes both schematic and electromagnetic simulations for design analysis. The findings underscore the performance benefits of GaN devices, particularly their high breakdown voltage and efficiency compared to other semiconductor technologies.
IRJET- Total Harmonic Distortion (THD) Compensation Via UPQC using PID Contro...
IRJET- Total Harmonic Distortion (THD) Compensation Via UPQC using PID Contro...IRJET Journal This document discusses using a PID controller to compensate for total harmonic distortion (THD) in a unified power quality conditioner (UPQC). A UPQC uses two voltage source inverters connected back-to-back to compensate for voltage sags/swells and reduce current harmonics and reactive power. The proposed method uses a PID controller to regulate voltage and current parameters and reduce THD. Simulation results show the PID controller reduces THD in the load current to below 5% and regulates the DC bus voltage. The paper concludes the UPQC with PID controller provides effective compensation of current THD.
IRJET- 127 Multilevel Inverter
IRJET- 127 Multilevel InverterIRJET Journal The document describes a proposed 127-level hybrid multilevel inverter topology. Multilevel inverters are useful for medium-voltage high-power applications as they can generate stepped voltage waveforms to reduce harmonic distortion. The proposed topology uses a bypass diode technique and H-bridge configuration to produce 31 voltage levels with only 8 switches and 4 diodes, reducing components compared to other multilevel inverter topologies. The performance of the 31-level inverter is studied using MATLAB/Simulink simulation. A 1 kW hardware prototype is developed to experimentally verify the concept. The proposed topology aims to reduce switching losses and total harmonic distortion in the output waveform.
Performance Evaluation of Personal Ad-hoc Area Network Based on Different Mob...
Performance Evaluation of Personal Ad-hoc Area Network Based on Different Mob...IRJET Journal This document evaluates the performance of a personal ad-hoc area network (PANET) using different node mobility models in a simulation. It simulates four mobility models - Random Waypoint, Reference Point Group, Freeway, and City Section - and compares their performance based on metrics like packet delivery ratio, end-to-end delay, throughput, routing overhead, and data loss. The simulation results show that the freeway mobility model performs better than the others, with the highest packet delivery ratio and one of the lowest end-to-end delays and data losses.
[IJET-V1I2P6] Authors :Sarat K Kotamraju, K.Ch.Sri Kavya, A.Gnandeep Reddy, G...
[IJET-V1I2P6] Authors :Sarat K Kotamraju, K.Ch.Sri Kavya, A.Gnandeep Reddy, G...IJET - International Journal of Engineering and Techniques
Similar to IRJET- Design and Simulation of Comparator Architectures for Various ADC Applications (20)
International Journal of Engineering Research and Development
International Journal of Engineering Research and DevelopmentIJERD Editor The document presents a novel design of a low power high speed fully dynamic CMOS latched comparator, which demonstrates a 62% reduction in delay sensitivity, achieving a delay of 0.098ns compared to conventional designs. The proposed comparator leverages a unique architecture that improves gain while maintaining low power consumption and smaller area. Simulation results confirm enhancements in performance against traditional dynamic comparators, marking it a viable option for applications like high-speed analog-to-digital converters.
A1040106
A1040106IJERD Editor This document describes the design of a low power, high speed fully dynamic CMOS latched comparator. It begins with an abstract that outlines the goal of designing a comparator with less sensitivity to delay using a dynamic CMOS latched comparator approach. It then reviews different comparator architectures including open loop, regenerative, and preamplifier-based designs. The focus is on fully dynamic latched comparators, analyzing their advantages and disadvantages. A novel comparator design is proposed that provides better input offset characteristics and faster operation than previous designs like resistor divider, latch-type, and double-tail comparators. The schematic and operating principles of the proposed comparator are described.
Design of Low Power & High Speed Comparator with 0.18μm Technology for ADC Ap...
Design of Low Power & High Speed Comparator with 0.18μm Technology for ADC Ap...IJERA Editor This paper discusses the design of a high-speed, low-power CMOS comparator for analog to digital converter (ADC) applications, fabricated in a 0.18μm technology with a power supply of 1.8V. The proposed comparator exhibits a speed of 0.8108 GHz and a low power dissipation of 108.0318μW, achieving enhanced performance over earlier designs. Simulation results, comparisons of various comparator designs, and the implications for future ADC technologies are presented, confirming the effectiveness of the proposed preamplifier-based comparator.
Analysis and Comparison of CMOS Comparator At 90 NM Technology
Analysis and Comparison of CMOS Comparator At 90 NM TechnologyIJERA Editor The document presents a CMOS comparator designed for low power dissipation using a preamplifier latch architecture. The proposed design is compared with a conventional double tail comparator, showing improvements in speed and reduced kickback noise. Simulations in a 90 nm technology environment demonstrate that the proposed comparator achieves significantly lower average power consumption compared to traditional designs.
Study and implementation of comparator in cmos 50 nm
Study and implementation of comparator in cmos 50 nmeSAT Publishing House This document discusses the design and implementation of two types of comparators used in flash analog-to-digital converters (ADC) with a focus on a single-ended threshold inverter quantizer (TIQ) and a two-stage open-loop comparator using 50nm CMOS technology. It highlights the performance implications of each comparator, their configurations, and provides simulation results from LT-spice and Microwind software. The paper concludes that the two-stage open-loop comparator is simpler and can be extended for medium-to-high resolution applications.
Study and implementation of comparator in cmos 50 nm technology
Study and implementation of comparator in cmos 50 nm technologyeSAT Journals The document discusses the design and implementation of comparator circuits in 50nm CMOS technology, particularly focusing on the 'Threshold Inverter Quantizer' (TIQ) and 'two-stage open-loop comparator' for applications in flash analog-to-digital converters (ADCs). It highlights the performances, advantages, and disadvantages of each comparator type, detailing their circuitry, functionality, and simulation results. Additionally, the paper suggests that the two-stage open-loop comparator architecture can be applied to medium-to-high resolution applications and indicates future work to design a low power flash ADC using this comparator design.
IRJET - Design and Analysis of a Comparator for ADC in Tanner EDA
IRJET - Design and Analysis of a Comparator for ADC in Tanner EDAIRJET Journal This document describes the design and analysis of comparators for use in flash analog-to-digital converters (ADCs). It discusses several comparator circuit designs including dynamic comparators, latch-track comparators, low voltage comparators, and high-speed comparators. The comparators are simulated in Cadence Virtuoso using a 180nm CMOS technology to compare their power, area, and delay characteristics for optimizing flash ADC design. Key goals in comparator design for flash ADCs include reducing power consumption, area overhead, and increasing conversion speed.
Double tail comparator
Double tail comparatorMdLogic Mdls This document discusses the design and analysis of a low-voltage, low-power double-tail comparator, which is crucial for high-speed applications in mixed signal systems. It highlights the trade-offs between speed and power dissipation in comparator designs, comparing conventional comparators to a dynamic latched comparator that offers improved performance. The paper also addresses power management techniques in low-power designs and provides insights into the functionality of retention memory elements used for data preservation during sleep modes.
Design & characterization of high speed power efficient cmos comparator
Design & characterization of high speed power efficient cmos comparatorIAEME Publication The paper presents the design and characterization of a high-speed, power-efficient CMOS voltage comparator for A/D converters utilizing 130nm and 90nm technologies. It achieves speeds of 1.92GHz and 2.44GHz with power dissipation of 9.19μW and 7.45μW, respectively, demonstrating improved performance in the smaller technology node. The results indicate better speed and reduced power dissipation while the input common mode range remains comparable across both technologies.
High Speed, Low Offset, Low Power, Fully Dynamic Cmos Latched Comparator
High Speed, Low Offset, Low Power, Fully Dynamic Cmos Latched Comparatoriosrjce This document presents a design of a high speed, low power dynamic CMOS latched comparator, improving upon traditional designs with reduced offset voltage and enhanced performance in various applications. The proposed comparator operates at a supply voltage of 1.8V, with a resolution of 300nV and power consumption of 450μW, achieving a delay of 5ns. It demonstrates significant advantages in speed, resolution, and area efficiency over conventional comparators, validated through simulations in the Cadence Virtuoso environment.
Cw4301569573
Cw4301569573IJERA Editor This document discusses the development and analysis of clocked regenerative comparators used in analog-to-digital conversion, highlighting their low power, low delay, and high-speed characteristics. It presents a comparative study between conventional dynamic comparators and double tail conventional dynamic comparators, showcasing a delay reduction of up to 31% with the latter in a 180nm technology. The study emphasizes the importance of these comparators in high-speed applications and provides detailed simulations of their performance.
ANALYSIS AND DESIGN OF DOUBLE TAIL COMPARATOR USING A LOW POWER GATING TECHNI...
ANALYSIS AND DESIGN OF DOUBLE TAIL COMPARATOR USING A LOW POWER GATING TECHNI...RK CONSULTANCY SERVICES The document presents an analysis and design of double tail comparators using low power gating techniques, emphasizing their importance in high-speed analog to digital converters (ADCs) and the challenges posed by low voltage supply. It compares various dynamic double tail comparator architectures and their performance in terms of delay, power, area, and glitches, proposing a new design method that improves efficiency and reduces delay. The paper concludes with experimental results indicating that the proposed comparator outperforms conventional designs while operating at lower supply voltages.
Analysis and Characterization of Different Comparator Topologies
Analysis and Characterization of Different Comparator TopologiesAalay Kapadia The document discusses the design and implementation of comparators in analog circuits, particularly in sub-micron and deep sub-micron technologies. It details various topologies, including the basic comparator and self-biased comparator, and presents pre-layout simulation results comparing their voltage gain, output impedance, and power dissipation. The findings highlight the trade-offs between different designs, emphasizing the importance of selecting the appropriate topology based on specific application requirements.
Analysis and design_of_a_low-voltage_low-power[1]
Analysis and design_of_a_low-voltage_low-power[1]Srinivas Naidu The document presents an analysis of the delay characteristics of dynamic comparators. It analyzes the delay of conventional dynamic and double-tail comparators, deriving analytical expressions showing the impact of various design parameters on delay. A new dynamic comparator is then proposed based on modifying the circuit of a conventional double-tail comparator to strengthen positive feedback, reducing delay time. Simulation results on the proposed comparator show significantly reduced power consumption and delay compared to conventional designs, enabling higher clock frequencies at lower supply voltages.
Design of Low Voltage and High Speed Double-Tail Dynamic Comparator for Low P...
Design of Low Voltage and High Speed Double-Tail Dynamic Comparator for Low P...International Journal of Engineering Inventions www.ijeijournal.com This paper presents the design of a low voltage and high-speed double-tail dynamic comparator aimed at improving performance in low-power applications. The proposed comparator features a new configuration that reduces offset voltage and enhances load drivability, achieving lower delay and power consumption compared to conventional designs. Simulation results validate the effectiveness of this design, showing significant improvements in speed and energy efficiency.
Ijetcas14 562
Ijetcas14 562Iasir Journals This document describes a proposed low power and high speed voltage sense amplifier circuit. The circuit replaces the back-to-back inverters in a previous design with a dual input single output differential amplifier. This modification improves noise immunity and reduces delay and power consumption. Simulation results show a 24% reduction in delay and 23% reduction in energy usage compared to the previous circuit, while maintaining the same offset voltage. The circuit is designed using a 180nm CMOS process at 1.8V.
Design & implementation of 3 bit flash adc in 0.18µm cmos
Design & implementation of 3 bit flash adc in 0.18µm cmosIAEME Publication This document describes the design and implementation of a 3-bit flash analog-to-digital converter (ADC) using a 0.18um CMOS technology. It includes 7 comparators and a thermometer-to-binary encoder. The ADC architecture consists of a resistive ladder, comparators that compare the input voltage to reference voltages from the ladder, and an encoder that converts the thermometer code from the comparators to a binary code. Simulation results show the ADC operates up to 4GHz and correctly converts the input signal to a 3-bit digital output. A layout is designed with common centroid layout for the comparators to reduce fabrication errors.
comparator.pptx
comparator.pptxPrasunSinghal2 The document discusses CMOS comparators. It describes comparators as circuits that detect the polarity of an analog input signal and produce a digital output. Comparators are used in applications like AD conversion, communication receivers, memory readout circuits, and power electronics. The document covers comparator design considerations like accuracy, speed, sensitivity, and power consumption. It also describes different comparator circuit topologies, including single-stage, multi-stage, and latch-based designs. Offset cancellation techniques for multi-stage comparators are discussed in detail.
An adjustable Comparator for 2-bit/step SAR ADC Configuring with multiple sam...
An adjustable Comparator for 2-bit/step SAR ADC Configuring with multiple sam...Association of Scientists, Developers and Faculties This paper presents an adjustable comparator for a 2-bit/step successive approximation register (SAR) analog-to-digital converter (ADC) operating at high speed with reduced power consumption using a dynamic threshold configuration in 40nm CMOS technology. The proposed dual tail comparator minimizes power and delay, achieving over 50% speed improvement compared to conventional designs while maintaining immunity against power supply variations. The innovative architecture demonstrates considerable efficiency suitable for low power applications, particularly in mobile and wireless communications.
Design and Analysis of Low Power Double Tail Comparator for 2-bit Fast ADC
Design and Analysis of Low Power Double Tail Comparator for 2-bit Fast ADCIJCSIS Research Publications The document discusses the design and analysis of a low power double tail comparator for a 2-bit flash ADC, highlighting the need for low power consumption in modern digital circuits. The proposed comparator, which incorporates a sleepy inverter to reduce power usage, achieved a power consumption of 30μW, compared to 35μW in a conventional comparator. The overall performance of the flash ADC using the new comparator resulted in a power consumption of 45mW, making it suitable for applications requiring efficient analog-to-digital conversion.
ANALYSIS AND DESIGN OF DOUBLE TAIL COMPARATOR USING A LOW POWER GATING TECHNI...
ANALYSIS AND DESIGN OF DOUBLE TAIL COMPARATOR USING A LOW POWER GATING TECHNI...RK CONSULTANCY SERVICES
Design of Low Voltage and High Speed Double-Tail Dynamic Comparator for Low P...
Design of Low Voltage and High Speed Double-Tail Dynamic Comparator for Low P...International Journal of Engineering Inventions www.ijeijournal.com
An adjustable Comparator for 2-bit/step SAR ADC Configuring with multiple sam...
An adjustable Comparator for 2-bit/step SAR ADC Configuring with multiple sam...Association of Scientists, Developers and Faculties
Design and Analysis of Low Power Double Tail Comparator for 2-bit Fast ADC
Design and Analysis of Low Power Double Tail Comparator for 2-bit Fast ADCIJCSIS Research Publications
Ad
More from IRJET Journal (20)
Enhanced heart disease prediction using SKNDGR ensemble Machine Learning Model
Enhanced heart disease prediction using SKNDGR ensemble Machine Learning ModelIRJET Journal https://www.irjet.net/archives/V11/i2/IRJET-V11I201.pdf
Utilizing Biomedical Waste for Sustainable Brick Manufacturing: A Novel Appro...
Utilizing Biomedical Waste for Sustainable Brick Manufacturing: A Novel Appro...IRJET Journal https://www.irjet.net/archives/V11/i2/IRJET-V11I209.pdf
Kiona – A Smart Society Automation Project
Kiona – A Smart Society Automation ProjectIRJET Journal https://www.irjet.net/archives/V11/i2/IRJET-V11I207.pdf
DESIGN AND DEVELOPMENT OF BATTERY THERMAL MANAGEMENT SYSTEM USING PHASE CHANG...
DESIGN AND DEVELOPMENT OF BATTERY THERMAL MANAGEMENT SYSTEM USING PHASE CHANG...IRJET Journal https://www.irjet.net/archives/V11/i2/IRJET-V11I204.pdf
Invest in Innovation: Empowering Ideas through Blockchain Based Crowdfunding
Invest in Innovation: Empowering Ideas through Blockchain Based CrowdfundingIRJET Journal https://www.irjet.net/archives/V11/i2/IRJET-V11I205.pdf
SPACE WATCH YOUR REAL-TIME SPACE INFORMATION HUB
SPACE WATCH YOUR REAL-TIME SPACE INFORMATION HUBIRJET Journal https://www.irjet.net/archives/V11/i2/IRJET-V11I203.pdf
A Review on Influence of Fluid Viscous Damper on The Behaviour of Multi-store...
A Review on Influence of Fluid Viscous Damper on The Behaviour of Multi-store...IRJET Journal https://www.irjet.net/archives/V11/i2/IRJET-V11I206.pdf
Wireless Arduino Control via Mobile: Eliminating the Need for a Dedicated Wir...
Wireless Arduino Control via Mobile: Eliminating the Need for a Dedicated Wir...IRJET Journal https://www.irjet.net/archives/V11/i2/IRJET-V11I208.pdf
Explainable AI(XAI) using LIME and Disease Detection in Mango Leaf by Transfe...
Explainable AI(XAI) using LIME and Disease Detection in Mango Leaf by Transfe...IRJET Journal This paper presents a pre-trained deep learning model, DenseNet169, for the detection of leaf diseases in mango plants using transfer learning and the explainable AI tool LIME. The model achieved an accuracy of 97.41% and emphasizes the importance of model interpretability in agricultural machine learning applications. Future work aims to expand the dataset to enhance the model's generalization for a wider range of plant leaf diseases.
BRAIN TUMOUR DETECTION AND CLASSIFICATION
BRAIN TUMOUR DETECTION AND CLASSIFICATIONIRJET Journal This document presents a study on the application of artificial intelligence (AI) and machine learning (ML), specifically using support vector machines (SVM), for the early detection and classification of brain tumors. It emphasizes the importance of early detection in improving treatment outcomes and reviews existing methodologies and technologies for brain tumor diagnosis. The findings indicate high accuracy in tumor detection, with the SVM model achieving a training score of 0.9887 and a testing score of 0.9592.
The Project Manager as an ambassador of the contract. The case of NEC4 ECC co...
The Project Manager as an ambassador of the contract. The case of NEC4 ECC co...IRJET Journal The document discusses the NEC4 Engineering and Construction Contract (ECC) as a transformative approach to contract management in the construction industry, emphasizing collaborative risk sharing and management. It highlights the innovative features of NEC4, including a focus on mutual trust and early warning processes that facilitate proactive risk management. The article aims to improve traditional contracting models by reviewing the characteristics of NEC4 ECC contracts and their application in project management.
"Enhanced Heat Transfer Performance in Shell and Tube Heat Exchangers: A CFD ...
"Enhanced Heat Transfer Performance in Shell and Tube Heat Exchangers: A CFD ...IRJET Journal This study presents a computational fluid dynamics (CFD) analysis of a shell and tube heat exchanger using twisted tape turbulators and aluminum oxide (Al2O3) nanofluids to enhance heat transfer performance. It reveals that the incorporation of Al2O3 nanofluids significantly improves heat transfer rates, though higher concentrations increase pressure drops, suggesting a trade-off between enhanced heat transfer and pressure drop. The research aims to provide valuable insights for optimizing heat exchanger designs and operational parameters in industrial applications.
Advancements in CFD Analysis of Shell and Tube Heat Exchangers with Nanofluid...
Advancements in CFD Analysis of Shell and Tube Heat Exchangers with Nanofluid...IRJET Journal The document reviews advancements in computational fluid dynamics (CFD) analysis of shell and tube heat exchangers utilizing nanofluids and twisted tape turbulators to enhance heat transfer efficiency. It highlights the potential of nanofluids to improve thermal conductivity and the role of twisted tape in altering flow dynamics, while addressing challenges like nanoparticle agglomeration and increased pressure drop. The findings illustrate the synergy of these technologies, presenting insights for optimizing heat exchanger designs in various industrial applications.
Breast Cancer Detection using Computer Vision
Breast Cancer Detection using Computer VisionIRJET Journal The document discusses a novel computer vision-based method for the early detection and diagnosis of breast cancer, utilizing convolutional neural networks (CNNs) for high accuracy and cost-effectiveness. The research highlights the development of a CNN model that achieved 92.25% accuracy in identifying breast regions in medical images, demonstrating its potential for improving patient outcomes. It also addresses challenges faced in current methodologies and the future scope of enhancing breast cancer detection technologies.
Auto-Charging E-Vehicle with its battery Management.
Auto-Charging E-Vehicle with its battery Management.IRJET Journal The document discusses a novel auto-charging electric vehicle (EV) concept that minimizes charging time and maximizes travel distance by integrating a generator coupled to the vehicle's wheel shaft. It details the system's design involving dual batteries—one for propulsion and the other for storage—along with a controller for efficient power management through hard or soft switching mechanisms. The aim is to reduce reliance on charging stations and contribute to global pollution control by providing an energy-efficient EV solution.
Analysis of high energy charge particle in the Heliosphere
Analysis of high energy charge particle in the HeliosphereIRJET Journal The study analyzes galactic cosmic ray (GCR) flux variations during solar cycles 23-24, focusing on the effects of solar activity and heliospheric conditions. It finds that GCR intensity is modulated by solar winds, coronal mass ejections, and interplanetary magnetic field disturbances, demonstrating an anti-correlation with solar activity indices. The research highlights the impact of these solar phenomena on GCR behavior and their relation to the dynamics of heliospheric plasma.
A Novel System for Recommending Agricultural Crops Using Machine Learning App...
A Novel System for Recommending Agricultural Crops Using Machine Learning App...IRJET Journal The document discusses a novel crop recommendation system utilizing machine learning techniques aimed at improving agricultural productivity, particularly in Maharashtra, India. It highlights the importance of data analysis and precision agriculture in addressing the challenges farmers face due to changing climatic conditions and the need for reliable crop yield predictions. The proposed system aims to provide personalized recommendations based on various agricultural parameters to enhance yield and support farmers in making informed decisions.
Auto-Charging E-Vehicle with its battery Management.
Auto-Charging E-Vehicle with its battery Management.IRJET Journal The document discusses a novel approach to electric vehicles (EVs) featuring an auto-charging mechanism aimed at eliminating long charging times and extending travel distances. The project involves a dual-battery system using a generator coupled to the vehicle's wheel shaft, which allows for efficient energy management through a controller that switches between the main and auxiliary batteries. The proposed solution has the potential to reduce dependency on charging stations and contribute to lower emissions and maintenance costs.
Analysis of high energy charge particle in the Heliosphere
Analysis of high energy charge particle in the HeliosphereIRJET Journal The document presents a data-driven analysis of galactic cosmic rays (GCRs) during solar cycle 23-24, exploring the relationship between solar activity and GCR modulation. It discusses the dependence of GCR diffusion parameters on rigidity and time, emphasizing the influences of solar wind disturbances and interplanetary magnetic field variations. The findings reveal an inverse correlation between GCR intensity and solar activity indices, suggesting unique modulation characteristics during this solar cycle.
Wireless Arduino Control via Mobile: Eliminating the Need for a Dedicated Wir...
Wireless Arduino Control via Mobile: Eliminating the Need for a Dedicated Wir...IRJET Journal This document presents a method for wirelessly controlling Arduino using a mobile device via a laptop without dedicated hardware modules like ESP8266 or ESP32. It details a Python script that acts as a communication bridge, establishing a connection through serial communication and socket networking to exchange commands and responses, specifically demonstrated by controlling an LED. The project emphasizes cost-effectiveness and practicality for IoT applications by leveraging existing resources and offers flexibility for future expansions.
Ad
Recently uploaded (20)
Microwatt: Open Tiny Core, Big Possibilities
Microwatt: Open Tiny Core, Big PossibilitiesIBM Microwatt is a lightweight, open-source core based on the OpenPOWER ISA.
It’s designed for FPGAs and easy experimentation in chip design.
Ideal for education, prototyping, and custom silicon development.
Fully open, it empowers developers to learn, modify, and innovate.
Decoding Kotlin - Your Guide to Solving the Mysterious in Kotlin - Devoxx PL ...
Decoding Kotlin - Your Guide to Solving the Mysterious in Kotlin - Devoxx PL ...João Esperancinha Kotlin can be very handy and easy to use. Kotlin offers the possibility to develop code that is easy to understand, safe, immutable, and thus predictable and follows standards that avoid side effects. I realized that very quickly after I started my Kotlin journey that already amounts to more than 5 years.
This is the third version of this presentation focused on more detail explaining inline, crossinline, tailrec and as a bonus a quick run through unnamed classes.
Tally.ERP 9 at a Glance.book - Tally Solutions .pdf
Tally.ERP 9 at a Glance.book - Tally Solutions .pdfShabista Imam Tally.ERP 9 at a Glance.book, a fully completed guidance to learn tally erp 9.0
ElysiumPro Company Profile 2025-2026.pdf
ElysiumPro Company Profile 2025-2026.pdfinfo751436 Description
ElysiumPro | IEEE Final Year Projects | Best Internship Training | Inplant Training in Madurai
Best Final Year project training center
Address:
First Floor, A Block, 'Elysium Campus, 229, Church Rd, Vaigai Colony, Madurai, Tamil Nadu 625020
Plus Code:
W4CX+56 Madurai, Tamil Nadu
+91 9944793398
[email protected]
Elysium Group of Companies established ElysiumPro in 2001. Since its inception, it has been the most sought-after destination for final year project development and research papers among the students. Our commitment to providing quality project training & documentation to students has always been exceptional. We deliver the final year engineering projects and technical documents that provide extra edge and industry exposure to land prestigious jobs and reputed institutions for higher studies. Students from all over the country avail of our services for their final year projects. On average, we develop 5000+ projects and research papers per year on varied advanced domains. Python, JAVA, PHP, Android, Matlab, LabView, VLSI, SIMULINK, Power electronics, Power System, Antenna, Machine Learning, Deep Learning, Data Science, Artificial Intelligence, data Mining, Big Data, Cloud Computing, IoT,
Hours of Operation: -
Sunday 10am-1pm
Monday 7.30am-8pm
Tuesday 7.30am-8pm
Wednesday 7.30am-8pm
Thursday 7.30am-8pm
Friday 7.30am-8pm
Saturday 7.30am-8pm
Web Site:
https://elysiumpro.in/
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
Youtube Geotagged Video:
https://youtu.be/QULY6XfuMyo
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
Slideshow Images (Google Photos):
https://photos.app.goo.gl/hVwQJtkeptA1JZKd9
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
GBP Listing:
https://goo.gl/maps/6d6hko6TsDYyeDrz9
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
Serving Areas:
https://www.google.com/maps/d/edit?mid=1-fsZogBiEAcjGP_aDyI0UKKIcwVUWfo&usp=sharing
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
Google Site:
https://elysiumpro-project-center.business.site
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
Google Sheet: https://docs.google.com/spreadsheets/d/1uXA07zxrUx2FCnBZWH80PpBZQrrX-2q1UBBe_0k3Yeo
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
Google Document: https://docs.google.com/document/d/1BU4ZHW_41XJm2lvTq9pWYUpZILAEmF9dWEw7-DBbWoE
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
Google Slides: https://docs.google.com/presentation/d/1uF8q6ueJWcAnhKTQsZxLE0Bo9PwgRNwCeuGV_ZgbSyU
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
Complete University of Calculus :: 2nd edition
Complete University of Calculus :: 2nd editionShabista Imam Master the language of change with the Complete Guidance Book of Calculus—your comprehensive resource for understanding the core concepts and applications of differential and integral calculus. Designed for high school, college, and self-study learners, this book takes a clear, intuitive approach to a subject often considered challenging.
Structured Programming with C++ :: Kjell Backman
Structured Programming with C++ :: Kjell BackmanShabista Imam Step into the world of high-performance programming with the Complete Guidance Book of C++ Programming—a definitive resource for mastering one of the most powerful and versatile languages in computer science.
Whether you're a beginner looking to learn the fundamentals or an intermediate developer aiming to sharpen your skills, this book walks you through C++ from the ground up. You'll start with basics like variables, control structures, and functions, then progress to object-oriented programming (OOP), memory management, file handling, templates, and the Standard Template Library (STL).
Complete guidance book of Asp.Net Web API
Complete guidance book of Asp.Net Web APIShabista Imam Unlock the full potential of modern web development with the Complete Guidance Book of ASP.NET Web API—your all-in-one resource for mastering RESTful services using Microsoft’s powerful ASP.NET Core framework. This book takes you on a step-by-step journey from beginner to expert, covering everything from routing and controllers to security, performance optimization, and real-world architecture.
Abraham Silberschatz-Operating System Concepts (9th,2012.12).pdf
Abraham Silberschatz-Operating System Concepts (9th,2012.12).pdfShabista Imam Complete book of operating system edition 9
Deep Learning for Natural Language Processing_FDP on 16 June 2025 MITS.pptx
Deep Learning for Natural Language Processing_FDP on 16 June 2025 MITS.pptxresming1 This gives an introduction to how NLP has evolved from the time of World War II till this date through the advances in approaches, architectures and word representations. From rule based approaches, it advanced to statistical approaches. from traditional machine learning algorithms it advanced to deep neural network architectures. Deep neural architectures include recurrent neural networks, long short term memory, gated recurrent units, seq2seq models, encoder decoder models, transformer architecture, upto large language models and vision language models which are multimodal in nature.
FUNDAMENTALS OF COMPUTER ORGANIZATION AND ARCHITECTURE
FUNDAMENTALS OF COMPUTER ORGANIZATION AND ARCHITECTUREShabista Imam FUNDAMENTALS OF COMPUTER ORGANIZATION AND ARCHITECTURE
By : Mostafa Abd-El-Barr & Hesham El-Rewini:: wiley
A complete guidance book
Tesla-Stock-Analysis-and-Forecast.pptx (1).pptx
Tesla-Stock-Analysis-and-Forecast.pptx (1).pptxmoonsony54 this is data science ppt for tesla stock (linear regression)
Deep Learning for Image Processing on 16 June 2025 MITS.pptx
Deep Learning for Image Processing on 16 June 2025 MITS.pptxresming1 This covers how image processing or the field of computer vision has advanced with the advent of neural network architectures ranging from LeNet to Vision transformers. It covers how deep neural network architectures have developed step-by-step from the popular CNNs to ViTs. CNNs and its variants along with their features are described. Vision transformers are introduced and compared with CNNs. It also shows how an image is processed to be given as input to the vision transformer. It give the applications of computer vision.
IRJET- Design and Simulation of Comparator Architectures for Various ADC Applications
- 1. International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 06 Issue: 05 | May 2019 www.irjet.net p-ISSN: 2395-0072 © 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 5817 Design and Simulation of Comparator Architectures for Various ADC Applications Disha Gaude1, Bathini Poornima2, K. M. Sudharshan3, Prashant V. Joshi4 1,2,3,4Dept. of Electronics and communication Engineering, REVA University, Bengaluru, India ----------------------------------------------------------------------***--------------------------------------------------------------------- Abstract - This paper presents design and simulation of different CMOS comparators. The designs are simulated and studied in 180 nm Technology with Cadence Virtuoso Tool with supply voltage 3.3 V and reference voltage of 3V. The clock used in comparator has a frequency of 1 M Hz. The comparators are mostly used in converting analog signals to digital signals for processing. Comparators are used in the applications requiring less power dissipation, good accuracy and high resolution. Key Words: comparator, Dynamic, Static, Latch, Clock Frequency, Pre amplifier, post amplifier. Ⅰ. Introduction Comparator is a circuit which compares two input voltages in which one is analog input and other is reference voltage and outputs binary 0 or 1 depending on comparison. It is basically a 1 bit analog to digital converter. In ADCs sample and hold circuit samples the analog input signal and the sampled signal is given to comparator, depending on reference voltage it produces digital output which is equivalent to analog input signal [1]. Comparators are used in all ADCs requiring less power dissipation, high speed, low noise, less offset voltage, good slew rate etc. Different types of comparators are available namely open loop comparator, regenerative comparator and combination of both open loop and regenerative comparator (cascaded comparators) [2]. Open loop compactors are basically single and two stage differential amplifiers without compensation and feedback loop. Regenerative comparators use positive feedback to improve the performance [3]. Comparator circuits can also be built by separating the comparators into number of cascaded stages. This helps in reducing the total propagation delay time and hence can be used in high speed applications like radar receivers and LAN interfaces. Fig -1. Symbol of comparator Above figure shows the symbol of comparator. It is basically operational amplifier because every comparator has one or many of the same characteristics as a high gain amplifier. The voltage Vp applied to the positive terminal of the comparator gives output 1 if voltage Vn applied to negative terminal is less or equal to Vp or else the output of the comparator gives 0 [11]. Ⅱ. Characterization of a comparator Static characteristics Gain The ideal aspect of this model is the way in which the output makes a transition between VOL and VOH. The output changes states for an input change of ΔV, where ΔV approaches zero [4]. The gain is given as Gain = AV = Fig -2. Ideal transfer curve Offset Voltage A mismatch in the threshold voltages and the trans conductance parameters of the transistor generates offset voltage in comparator. If the output did not change until the input difference reached a value of VOS then the difference would be defined as the offset voltage [5].
- 2. International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 06 Issue: 05 | May 2019 www.irjet.net p-ISSN: 2395-0072 © 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 5818 Fig -3. Transfer curve of a comparator including offset voltage and noise Dynamic characteristics Propagation Delay Propagation delay is defined as at how much speed the amplifier responds with applied input [6]. Propagation delay time = (rising propagation delay time + falling propagation delay time)/2 Fig -4. Propagation delay curve Ⅲ Comparator Topologies A. Two stage open loop comparator Comparator requires differential input and high gain to achieve desirable resolution. As a result two stage operational amplifiers can be used as a comparator. Comparator requires large bandwidth as possible so that faster response can be achieved. This is done by making two stage operational amplifiers as an open loop mode, thus no compensation is required [7].The advantage of this comparator is to provide high gain, large output voltage swing and disadvantage is that it consumes more power. Hence, it is not suitable for high speed and low power applications. Fig -5. Open loop comparator Small signal gain of the comparator as given by AV = ( ) ( ) Two stage comparator consists of two pole, first and second stage output poles P1 and P2 respectively are given as P1 = - Where CI is the sum of capacitance connected to the output of first stage. P2 = Where CII is the sum of capacitance connected to the output of second stage. B. Regenerative comparator Regenerative comparators use positive feedback to accomplish the comparison of two signals. The regenerative comparator is also called a latch or bistable. The simplest form of a latch is shown below Fig -6. NMOS Latch
- 3. International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 06 Issue: 05 | May 2019 www.irjet.net p-ISSN: 2395-0072 © 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 5819 Normally, the latch has two modes of operation. The first mode disables the positive feedback and applies the input signal to the terminals as V01 and V02. The initial voltages applied during this mode will be as V01 1 and V01 2. The second mode enables the latch and depending on the relative values of V01 1 and V01 2, one of the outputs will go high and the other will go low. A two phase clock is used to determine the modes of operation [10]. Fig -7. Dynamic latch C. High speed comparator High speed comparators should have a propagation delay time as small as possible. To achieve this goal, one must understand the requirement for fast comparator. This is best understood by separating the comparator into a number of cascading stages. So, this three cascading stages consists of input pre amplification stage, latch stage and output post amplification stage [8]. Pre amplification stage consists of current mirror single stage differential amplifier with high gain and low slew rate. This stage improves sensitivity of the comparator by isolating input from kickback noise and amplifying the smallest minimum input voltage. Latch is basically positive feedback circuit which determines the difference of the two input signals. Post amplification stage consists of self- biased differential amplifier followed by inverter. This stage helps in driving the high load and inters parasitic capacitance [9]. Fig -8. High speed comparator Ⅵ Simulation Results Fig -9. Schematic of two stage uncompensated comparator Fig -10. Output waveforms of two stage uncompensated comparator Fig -11. Schematic of dynamic latch Fig -12. Output waveforms of dynamic latch
- 4. International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 06 Issue: 05 | May 2019 www.irjet.net p-ISSN: 2395-0072 © 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 5820 Fig -13. Schematic of high speed comparator Fig -14. Output waveforms of comparator Table -1. Comparision of different types of comparator parameters Comparator Power Dissipatio n [uW] Propagatio n Delay [ps] Speed [GHz] Two satge uncompens ated comparator 101.5 57.12 7.507 Regenarativ e Comparaor 19.57 186.5 5.3619 High Speed Comparator 2.121 11.9 84.03 Ⅴ. Conclusion In this paper two stage uncompensated comparator, dynamic latch, regenerative comparator and high speed comparator with cascaded stages are implemented and simulated and simulation is carried out using Cadence tools, with gpdk 180nm. It is also verified with LT-SPICE using tsmc180nm technology file. The power dissipation, total propagation delay and speed are compared and calculated for different types of comparators with supply voltage 5 V. Ⅵ. Acknowledgement I am extremely thankful to Dr. Rajashekhar C Biradar, Director of the school of Electronics and Communication Engineering, Prof. Prashanth V Joshi coordinator, Mr. H. G. Yatheesh from VLSI industry for their valuable guidance and useful suggestions to work effectively with my project. References [1] S. Kim and K. Kwon, "A hybrid ADC combining capacitive DAC-based multi-bit/cycle SAR ADC with flash ADC," 2016 International Conference on Electronics, Information, and Communications (ICEIC), Da Nang, 2016. [2] U. M. Kulkarni, C. Parikh and S. Sen, "A Systematic Approach to Determining the Weights of the Capacitors in the DAC of a Non-binary Redundant SAR ADCs," 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), Pune, 2018. [3] W. Kim et al., "A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI- SAR) ADC," in IEEE Journal of Solid-State Circuits, vol. 51, no. 8, pp. 1826-1839, Aug. 2016. [4] C. Liu, M. Huang and Y. Tu, "A 12 bit 100 MS/s SAR- Assisted Digital-Slope ADC," in IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 2941-2950, Dec. 2016. [5] S. Lee, A. P. Chandrakasan and H. Lee, "A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration," in IEEE Journal of Solid-State Circuits, vol. 49, no. 12, pp. 2846-2856, Dec. 2014. [6] V. P. Singh, G. K. Sharma and A. Shukla, "Power efficient SAR ADC designed in 90 nm CMOS technology," 2017 2nd International Conference on Telecommunication and Networks (TEL-NET), Noida, 2017. [7] S. Z. Hoseini and K. Lee, "Compact Time-Mode SAR ADC With Capacitor Flipping Bit-Cycling Operation," 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS), Windsor, ON, Canada, 2018. [8] A. Bekal, M. Goswami, B. R. Singh and D. Pal, "A Low Power 8-Bit Asynchronous SAR ADC Design Using Charge Scaling DAC," 2014 Fifth International Symposium on Electronic System Design, Surathkal, 2014. [9] I. G. Naveen and S. Sonoli, "Design and simulation of 10-bit SAR ADC for low power applications using 180nm technology," 2016 International Conference on Electrical, Electronics, Communication, Computer and Optimization Techniques (ICEECCOT), Mysuru, 2016.
- 5. International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 06 Issue: 05 | May 2019 www.irjet.net p-ISSN: 2395-0072 © 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 5821 [10] Yin, G. M., Eynde, F. O., & Sansen, W. (1992). A high- speed CMOS comparator with 8-bit resolution. IEEE Journal of Solid-State Circuits. [11] Donadkar, D. N., & Bhandari, S. U. (2015). Review on Comparator Design for High Speed ADCs. 2015 International Conference on Computing Communication Control and Automation. [12] Babayan-Mashhadi, S., & Lotfi, R. (2014). Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. [13] Vinodiya, S. K., & Gamad, R. S. (2017). Analysis and design of low power, high speed comparators in 180nm technology with low supply voltages for ADCs. 2017 8th International Conference on Computing, Communication and Networking Technologies (ICCCNT). [14] Fouzy, B. B. A., Reaz, M. B. I., Bhuiyan, M. A. S., Badal, M. T. I., & Hashim, F. H. (2016). Design of a low-power high-speed comparator in 0.13μm CMOS. 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering (ICAEES). [15] Rangari, A. V., & Gaidhani, Y. A. (2016). Design of comparator using Domino Logic and CMOS Logic. 2016 Online International Conference on Green Engineering and Technologies (IC-GET).