IRJET- Energy Efficient One Bit Subtractor Circuits for Computing Applications in Embedded Systems
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The document describes a proposed 10-transistor one-bit full subtractor circuit for computing applications. It begins with an abstract discussing the need for low-power VLSI circuits as technology scales down. It then reviews prior work on subtractor circuit designs and leakage power reduction techniques. The document goes on to propose a new 10-transistor full subtractor design and compares it to 20-transistor and 14-transistor designs in terms of area, delay, power consumption and energy efficiency. Simulation results indicate the proposed 10-transistor design is more energy efficient.
![International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 06 Issue: 05 | May 2019 www.irjet.net p-ISSN: 2395-0072
© 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 1919
Energy Efficient one Bit Subtractor Circuits for Computing Applications
in Embedded Systems
S. Mohan Das1, N. Ramanjaneyulu2
1Assistant Professor, S.V.R.Engineering College, Nandyal.
2P.G. Student, S.V.R.Engineering College, Nandyal.
---------------------------------------------------------------------***----------------------------------------------------------------------
Abstract - As the technology goes down into the nano-scale
domain, static or leakage power consumption becomes an
important parameter in today’s VLSI design. In this paper,
area-power-energy efficient 10 transistor 1-bit fullsubtractor
has been proposed and compared with 20T and 14T one bit
full subtractor circuits. The simulations for all the circuits
were performed by using Microwind 3.1 CAD tool. Various
parameters such as area, delay, power consumption PDP and
EDP have been determined from Subtractor layout of feature
size 45nm technology. The proposed 10 transistors full
subtractor is energy efficient compared to other counterpart.
Key Words: Leakage power, Full subtractor, CAD tool.
1. INTRODUCTION
Low-power design techniques minimize active leakage
power in nano scale CMOS VLSI systems. Developers of
battery powered devices facing challenges to offer high
levels of functionality, performance and simultaneously
increasing life time of the battery. In some cases, battery
developers are also challenged to develop next generation
products with no battery at all, requiring energy harvesting
from environmental sources such as light, heat and
vibration[1] [2].
Leakage current and power is an important issue in
Deep Sub Micron (DSM) technology. The main contribution
of leakage power in CMOS circuits is due to dynamic power
dissipation which increases with the reduction of channel
length, threshold voltage and gate oxide thickness.
The total power dissipation of a logic gate is given by
PTotal = PStatic + PDynamic + PShort Circuit
PTotal = IS VDD f + αCVDD
2f + ISCVDDf
Where P switching is the power dissipated due to
charging and discharging of the circuit capacitances, Pshort
circuit is the power dissipated due to the short circuit
between Vdd and ground during output transitions and
Pleakage is the power dissipated due to leakagecurrent.The
term, Pleakage, is dramatically increased with technology
down scaling and increase in temperature, resulting in a
reduction of leakage [3] immunity and robustness. Among
these Powers, short circuit power dissipation isverylessi.e.,
almost negligible, when coming to static powerdissipationit
will occur only when gate is excited with inputs, which is
also less compared to dynamic powerdissipationasitoccurs
when transitions (charging and discharging) takes place
from high to low and vice –versa. More than 90 percent of
power dissipation takes place due to dynamic activity of
transistor switching in CMOS VLSI designs. Therefore, it is
very vital to reduce the leakage power of dynamic logic
gates.
Subtractor is a digital circuit that performs subtraction
of numbers and which is one among the four basic binary
operations. In most of the digital systems there is a
requirement for calculating addresses, table indices
frequently in some parts of processor which can be
performed by a subtractor. Integration and differentiations
are the two important mathematical operations which can
be performed frequently in analog circuits where as in
digital circuits, integration is similar to summation and
differentiation is analogous to Subtraction. Unlike the
addition operation, Subtraction in digital circuitsmaynot be
performed directly with logic gate because there is no direct
subtraction logic with transistor. Subtraction in digital
circuits performs by compliments [4] [5]. Full
adders/subtractors are important components in
applications such as digital signal processing (DSP)
architectures and microprocessor. Microprocessors and
digital signal processors rely onthe efficientimplementation
of generic arithmetic logic units and floating-point units to
execute dedicated algorithms.
2. LITERATURE REVIEW
M.MahaboobBasha et.al. presented [4] the design of one
bit full subtractor for energy efficient arithmetic application
in signal processing applications. In this work, they focused
on reducing the area of the digital circuit by reducing the
transistor count. For all the proposed circuits the simulation
has been carried out at 65 nm technology.
M.Mahaboob Basha et.al. proposed [5] low area high
speed energy efficient one bit 10 transistors based full
subtractor with MTCMOS for computing applications. In this
work, they focused on reducing the lealage current whan the
circuit is operated at less than 1 volts supply voltage. For all
the proposed circuits the simulation has been carried out at
65 nm technology.
Anamika Sharmaand RajeshMehraoutlined[6]an“Area
Efficient Layout Design & Analysis of Full Subtractor”. The
Main objective of this paper is to design Full Subtractor by](https://image.slidesharecdn.com/irjet-v6i5374-190909112549/85/IRJET-Energy-Efficient-One-Bit-Subtractor-Circuits-for-Computing-Applications-in-Embedded-Systems-1-320.jpg)
![International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 06 Issue: 05 | May 2019 www.irjet.net p-ISSN: 2395-0072
© 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 1920
using CMOS 65nmtechnologywithlessnumberoftransistors
and hence it is efficient in area and reduces the complexity.
The design of Full subtractor has been obtained
compared using auto generated layout, semi-custom layout
and fully custom layout. Performing the simulation
comparison is made between three layouts between auto
generated, semicustom and fully custom on the basis of area.
In this paper fully custom layout is 45% area efficient than
auto generated and 41% than semicustom layout. Semi-
custom is 6% area efficientthanautogenerated.Fullycustom
has better performance among the three layout techniques.
From the above result analysis it is clear that the fully
customized layout is more efficient in terms of area. Fully
customized layout is 45% is better than semi-custom layout
and 41% is better than auto generated layout approaches.So
this design approach can be implemented where area
reduction is the main consideration. In this approach power
factor compensates for area.
Kamal Jeet Singh and Rajesh Mehra proposed [7] “Design
&Analysis of Full Subtractor using 10T at 45nmTechnology”.
In this paper, a full subtractoris designed using XORgateand
GDI technique. The technology nodeused is 45nm. Transient
analysis forXOR gateand GDItechniquebasedfullsubtractor
is performed. In analysis, we found that the full subtractor
designed with XOR gate uses less number of transistor and
consumelesspowerthanGDItechniquebasedfullsubtractor.
Full subtractor using XOR gate uses 10T where GDI based
uses 14T. Power consumption and timedelay is improvedby
36.04% and 36.13% respectively when compared with GDI
based full subtractor. It is found that XOR gate based full
subtractor uses less number of transistors, less propagation
delay andless power consumption when comparedwithGDI
technique based full subtractor. XOR gate based full
subtractor has power consumptionof1.81μWanddelaytime
is 0.014ns whereas GDI technique based full subtractor have
power consumption of 0.83μW and delay time is 0.023ns.
From the literature, in this work, an attempt is made to
simulate the various one bit full subtractor at 45 nm
technology by using Microwind 3.1 CAD tool. The proposed
circuits could be an alternative in energy efficient divider
applications [8].
3. PROPOSED DESIGN
Now a days, power consumption and sub threshold
leakages are very challenging in the digital integrated circuit
design. A scaling functionality and density of transistors are
based on microprocessor chip. The scaling function helps to
increase performance and operation speed of the integrated
circuit design. In the present days, the leakage current and
power are common problemsinthedigitalcircuitdesign.The
digital system reliability can be improved by decreasing the
physical size, weight, cost and which is accomplished by
reducing the transistors count while designing the circuit.
Irjet Template sample paragraph .Define abbreviations and
acronyms the first time they are used in the text, even after
they have been defined in the abstract. Abbreviationssuchas
IEEE, SI, MKS, CGS, sc, dc, and rms do not have to be defined.
Do not use abbreviations in the title or heads unless they are
unavoidable.
3.1. One Bit Full Subtractor By Using 20 Transistors
The circuit diagram of 1- bit full subtractor with 20
transistors is shown figure.1. The full subtractor design has
less transistor count compared to the conventional full
subtractor design. In this fullsubtractor design, 6 transistors
employed for developing difference equation, 10 transistors
used for borrow equation and remaining 4 transistors for
inverting operation.
In this work, an attempt is made to design a one bit full
subtractor with reduced transistor count from the massive
literatureof adderdesign.Thecircuitconsistof20transistors
which includes one 6 transistors EX-OR module, two CMOS
inverters one at the difference output and otherattheoutput
of borrow and a section with 10 transistors which take care
about the generation of borrow in correspondtotheinputbit
variation and remaining modules.
The borrow section with ten transistors are made up
with 5 PMOS and 5 NMOS transistors and this part is similar
to that of carry section in a conventional 1-bit full adder.
From the observation of the functional truth table of one bit
adder and one bit subtractor it is clear that output sum of
adder and difference outputof subtractor are samewhereas,
they differs in output carry of adder in four outcomes among
eight for one bit operation.
Fig -1: 20 transistors based 1-bit full subtractor
Though it operates for all the remaining input
combination which is depicted in figure.2 perfectly, still it
suffers with low driving capability due to the degradation of](https://image.slidesharecdn.com/irjet-v6i5374-190909112549/85/IRJET-Energy-Efficient-One-Bit-Subtractor-Circuits-for-Computing-Applications-in-Embedded-Systems-2-320.jpg)
![International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 06 Issue: 05 | May 2019 www.irjet.net p-ISSN: 2395-0072
© 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 1923
Fig -10: performance analysis of power for various 1-bit
full subtractor circuits
Fig -11: performance analysis of energy for various 1-bit
full subtractor circuits
Fig -12: performance analysis of EDP for various 1-bit full
subtractor circuits
The performance analysis of various one bit full
subtractor circuits were shown in figure 8,9,10,11 and 12 in
terms of area,delay,power,PDP and EDP respectively.
5. CONCLUSIONS
From the results it is clear that, the 10T one bit full
subtractor occupies less area in comparison with other
counter parts.
The power consumption of 10T one bit full subtractoris
less in comparison with other counter parts whereas the
delay of 10T one bit full subtractor is more when compared
to 14T and 20T one bit full subtractor.
Therefore, the 10T one bit full subtractorisenergy,EDP,
power and area efficient at the cost of delay.
REFERENCES
[1] Neil Weste and D. Harris, “CMOS VLSI Design: A Circuit
and System Perspective,” Pearson Addition Wesley,
third Edition, 2005.
[2] Ken Martin, Digital Integrated Circuit Design, Oxford
University Press, New York, 2000.
[3] CMOS Digital Integrated Circuits Analysis and Design
Third Edition2003, By Sung-Mo Kang, Yusuf Leblebici.
[4] M. Mahaboobbasha, K. Venkataramanaiah, P. Ramana
Reddy. “Noval energy efficient one bit full subtractor at
65nm technology”. International conference on
electrical, electronics, signals, communication and
optimization(EESCO), IEEE, Jan 2015.
[5] M. Mahaboobbasha, K. Venkataramanaiah, P. Ramana
Reddy, “low area high speed energy efficient one bit full
subtractor with MTCMOS”. International Journal of
Applied Engineering Research. Volume 10, Number 11
(2015) pp. 27593-27604.
[6] Anamika Sharma, Rajesh Mehra “Area Efficient Layout
Design & Analysis of Full Subtractor” IJSRET EATHD-
2015 Conference Proceeding, 14-15 March, 2015.
[7] Kamal Jeet Singh, Rajesh Mehra “Design &Analysis of
Full Subtractor using 10T at 45nm Technology” IJETT,
Volume 35 Number 9 - May 2016.
[8] M.Mahaboob Basha, Dr. K.Venkata Ramanaiah, Dr.
P.Ramana Reddy, Salendra. Govindarajulu.” Novel low
Power and high speed array divider in 65nm
technology” International Journal ofAdvancesinScience
and Technology Vol. 6, No. 6, 2013.
[9] B. K. Mohanty and P. K. Meher, "Area–Delay–Energy
Efficient VLSI Architecture for Scalable In-Place
Computation of FFT on Real Data," in IEEE Transactions
on Circuits and Systems I: Regular Papers, vol. 66, no. 3,
pp. 1042-1050, March 2019.
[10] M.Mahaboob Basha, K.Venkata Ramanaiah, P. Ramana
Reddy," Design of Near Threshold 10T- Full Subtractor
Circuit for Energy Efficient Signal Processing
Applications", International Journal of Image, Graphics
and Signal Processing(IJIGSP), Vol.9, No.12, pp. 23-29,
2017.DOI: 10.5815/ ijigsp.2017.12.03.](https://image.slidesharecdn.com/irjet-v6i5374-190909112549/85/IRJET-Energy-Efficient-One-Bit-Subtractor-Circuits-for-Computing-Applications-in-Embedded-Systems-5-320.jpg)
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IRJET- Energy Efficient One Bit Subtractor Circuits for Computing Applications in Embedded Systems
- 1. International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 06 Issue: 05 | May 2019 www.irjet.net p-ISSN: 2395-0072 © 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 1919 Energy Efficient one Bit Subtractor Circuits for Computing Applications in Embedded Systems S. Mohan Das1, N. Ramanjaneyulu2 1Assistant Professor, S.V.R.Engineering College, Nandyal. 2P.G. Student, S.V.R.Engineering College, Nandyal. ---------------------------------------------------------------------***---------------------------------------------------------------------- Abstract - As the technology goes down into the nano-scale domain, static or leakage power consumption becomes an important parameter in today’s VLSI design. In this paper, area-power-energy efficient 10 transistor 1-bit fullsubtractor has been proposed and compared with 20T and 14T one bit full subtractor circuits. The simulations for all the circuits were performed by using Microwind 3.1 CAD tool. Various parameters such as area, delay, power consumption PDP and EDP have been determined from Subtractor layout of feature size 45nm technology. The proposed 10 transistors full subtractor is energy efficient compared to other counterpart. Key Words: Leakage power, Full subtractor, CAD tool. 1. INTRODUCTION Low-power design techniques minimize active leakage power in nano scale CMOS VLSI systems. Developers of battery powered devices facing challenges to offer high levels of functionality, performance and simultaneously increasing life time of the battery. In some cases, battery developers are also challenged to develop next generation products with no battery at all, requiring energy harvesting from environmental sources such as light, heat and vibration[1] [2]. Leakage current and power is an important issue in Deep Sub Micron (DSM) technology. The main contribution of leakage power in CMOS circuits is due to dynamic power dissipation which increases with the reduction of channel length, threshold voltage and gate oxide thickness. The total power dissipation of a logic gate is given by PTotal = PStatic + PDynamic + PShort Circuit PTotal = IS VDD f + αCVDD 2f + ISCVDDf Where P switching is the power dissipated due to charging and discharging of the circuit capacitances, Pshort circuit is the power dissipated due to the short circuit between Vdd and ground during output transitions and Pleakage is the power dissipated due to leakagecurrent.The term, Pleakage, is dramatically increased with technology down scaling and increase in temperature, resulting in a reduction of leakage [3] immunity and robustness. Among these Powers, short circuit power dissipation isverylessi.e., almost negligible, when coming to static powerdissipationit will occur only when gate is excited with inputs, which is also less compared to dynamic powerdissipationasitoccurs when transitions (charging and discharging) takes place from high to low and vice –versa. More than 90 percent of power dissipation takes place due to dynamic activity of transistor switching in CMOS VLSI designs. Therefore, it is very vital to reduce the leakage power of dynamic logic gates. Subtractor is a digital circuit that performs subtraction of numbers and which is one among the four basic binary operations. In most of the digital systems there is a requirement for calculating addresses, table indices frequently in some parts of processor which can be performed by a subtractor. Integration and differentiations are the two important mathematical operations which can be performed frequently in analog circuits where as in digital circuits, integration is similar to summation and differentiation is analogous to Subtraction. Unlike the addition operation, Subtraction in digital circuitsmaynot be performed directly with logic gate because there is no direct subtraction logic with transistor. Subtraction in digital circuits performs by compliments [4] [5]. Full adders/subtractors are important components in applications such as digital signal processing (DSP) architectures and microprocessor. Microprocessors and digital signal processors rely onthe efficientimplementation of generic arithmetic logic units and floating-point units to execute dedicated algorithms. 2. LITERATURE REVIEW M.MahaboobBasha et.al. presented [4] the design of one bit full subtractor for energy efficient arithmetic application in signal processing applications. In this work, they focused on reducing the area of the digital circuit by reducing the transistor count. For all the proposed circuits the simulation has been carried out at 65 nm technology. M.Mahaboob Basha et.al. proposed [5] low area high speed energy efficient one bit 10 transistors based full subtractor with MTCMOS for computing applications. In this work, they focused on reducing the lealage current whan the circuit is operated at less than 1 volts supply voltage. For all the proposed circuits the simulation has been carried out at 65 nm technology. Anamika Sharmaand RajeshMehraoutlined[6]an“Area Efficient Layout Design & Analysis of Full Subtractor”. The Main objective of this paper is to design Full Subtractor by
- 2. International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 06 Issue: 05 | May 2019 www.irjet.net p-ISSN: 2395-0072 © 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 1920 using CMOS 65nmtechnologywithlessnumberoftransistors and hence it is efficient in area and reduces the complexity. The design of Full subtractor has been obtained compared using auto generated layout, semi-custom layout and fully custom layout. Performing the simulation comparison is made between three layouts between auto generated, semicustom and fully custom on the basis of area. In this paper fully custom layout is 45% area efficient than auto generated and 41% than semicustom layout. Semi- custom is 6% area efficientthanautogenerated.Fullycustom has better performance among the three layout techniques. From the above result analysis it is clear that the fully customized layout is more efficient in terms of area. Fully customized layout is 45% is better than semi-custom layout and 41% is better than auto generated layout approaches.So this design approach can be implemented where area reduction is the main consideration. In this approach power factor compensates for area. Kamal Jeet Singh and Rajesh Mehra proposed [7] “Design &Analysis of Full Subtractor using 10T at 45nmTechnology”. In this paper, a full subtractoris designed using XORgateand GDI technique. The technology nodeused is 45nm. Transient analysis forXOR gateand GDItechniquebasedfullsubtractor is performed. In analysis, we found that the full subtractor designed with XOR gate uses less number of transistor and consumelesspowerthanGDItechniquebasedfullsubtractor. Full subtractor using XOR gate uses 10T where GDI based uses 14T. Power consumption and timedelay is improvedby 36.04% and 36.13% respectively when compared with GDI based full subtractor. It is found that XOR gate based full subtractor uses less number of transistors, less propagation delay andless power consumption when comparedwithGDI technique based full subtractor. XOR gate based full subtractor has power consumptionof1.81μWanddelaytime is 0.014ns whereas GDI technique based full subtractor have power consumption of 0.83μW and delay time is 0.023ns. From the literature, in this work, an attempt is made to simulate the various one bit full subtractor at 45 nm technology by using Microwind 3.1 CAD tool. The proposed circuits could be an alternative in energy efficient divider applications [8]. 3. PROPOSED DESIGN Now a days, power consumption and sub threshold leakages are very challenging in the digital integrated circuit design. A scaling functionality and density of transistors are based on microprocessor chip. The scaling function helps to increase performance and operation speed of the integrated circuit design. In the present days, the leakage current and power are common problemsinthedigitalcircuitdesign.The digital system reliability can be improved by decreasing the physical size, weight, cost and which is accomplished by reducing the transistors count while designing the circuit. Irjet Template sample paragraph .Define abbreviations and acronyms the first time they are used in the text, even after they have been defined in the abstract. Abbreviationssuchas IEEE, SI, MKS, CGS, sc, dc, and rms do not have to be defined. Do not use abbreviations in the title or heads unless they are unavoidable. 3.1. One Bit Full Subtractor By Using 20 Transistors The circuit diagram of 1- bit full subtractor with 20 transistors is shown figure.1. The full subtractor design has less transistor count compared to the conventional full subtractor design. In this fullsubtractor design, 6 transistors employed for developing difference equation, 10 transistors used for borrow equation and remaining 4 transistors for inverting operation. In this work, an attempt is made to design a one bit full subtractor with reduced transistor count from the massive literatureof adderdesign.Thecircuitconsistof20transistors which includes one 6 transistors EX-OR module, two CMOS inverters one at the difference output and otherattheoutput of borrow and a section with 10 transistors which take care about the generation of borrow in correspondtotheinputbit variation and remaining modules. The borrow section with ten transistors are made up with 5 PMOS and 5 NMOS transistors and this part is similar to that of carry section in a conventional 1-bit full adder. From the observation of the functional truth table of one bit adder and one bit subtractor it is clear that output sum of adder and difference outputof subtractor are samewhereas, they differs in output carry of adder in four outcomes among eight for one bit operation. Fig -1: 20 transistors based 1-bit full subtractor Though it operates for all the remaining input combination which is depicted in figure.2 perfectly, still it suffers with low driving capability due to the degradation of
- 3. International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 06 Issue: 05 | May 2019 www.irjet.net p-ISSN: 2395-0072 © 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 1921 voltage levels between the intermediate nodes as compared to conventional one at low supply voltages. Fig -2: Timing waveform of 1-bit full subtractor using 20 transistors 3.2. One Bit Full Subtractor By Using 14 Transistors The one bit full subtractor circuit consists of XOR-XNOR modules anda 2x1 multiplexer and requires14transistorsto implement which is shown in figure.3. The XNOR - XOR modules produces two intermediate signals that are passed to 2×1 multiplexer. The two intermediate signals are provided by the above logic gates performances as input to 2×1 multiplexer and the third input performances as selection line used for multiplexer. The differenceoutputisobtainedfrom6TXOR-XNORcell and a multiplexer, whereas borrow is obtained from 6T XOR gate. The 4T XOR module is employed by transistors M1, M2, M3 AND M4. Fig -3: 14 transistors based 1-bit full subtractor The timing waveform for the design circuit for different input combination is shown in below figure.4. With the involvement of multiplexer in theproposeddesignthecircuit performance is better in comparison with 20T and C-CMOS one bit subtractor. Still the circuit suffers with sub threshold leakage current due to the feedback based 6T XOR gatewhen it operates with a supply voltage less than 1.8 volts. Fig -4: Timing waveform of 1-bit full subtractor using 20 transistors Figure.4. With the involvement of multiplexer in the proposed design the circuit performance is better in comparison with 20T andC-CMOSonebitsubtractor.Stillthe circuit suffers with sub threshold leakage current due to the feedback based 6T XOR gate when it operates with a supply voltage less than 1.8 volts. 3.3. One Bit Full Subtractor By Using 10 Transistors The figure.5 shows the logic circuit of one-bit full subtractor design using two XOR gates and one multiplexer which consists three inputs like A, B, and C and two outputs such as Difference and Borrow. The transistor level circuit is implemented by 4 transistor XOR gates and 2x1 multiplexer with two transistors. Furthermore,thedifferenceoutputsare obtained from second XOR gates and borrow from multiplexer. Fig -5: Proposed 1-bit full subtractor logic cell.
- 4. International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 06 Issue: 05 | May 2019 www.irjet.net p-ISSN: 2395-0072 © 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 1922 The outcomes of the first XOR gate is considered as selection line employed for the multiplexer to pass the logic value. The B and C both act as inputs for the multiplexer. Fig -6: (a) (b) Number of transistors used for the XOR gate and Multiplexer. The figure.6 (a) and (b) shows the transistor based circuits used for the XOR gate and multiplexer. The first EX- OR gate is employed with four transistors and other EX-OR gate is employed with four transistors. The two transistors are the part of multiplexer. The proposed design was based on 10T one bit full adder with a bit of change in connections as well as selection of input combination to the multiplexer. Here the output of first XOR cell is select line for second XOR input and multiplexer. If first XOR output is at logic 0, the difference is same as input bit C only; otherwise the difference output is complementofinputbitC.incaseborrow output, if first EX-OR output is at logic 0, the borrowoutputis input bit C only. Similarly, if the first EX-OR gate output is at logic 1, the output borrow is input bit B only. Hence, the entire circuit operation for various possible input bit combination in terms of its timing waveform is depicted in figure 7. Fig -7: Timing waveform of 1-bit full subtractor using 10 transistors 4. RESULTS, DISCUSSION AND CONCLUSION In this work various one-bit full subtractor circuits with reduced transistor count were analyzed and all the simulation has been carried out at 45nm technology with Microwind 3.1 CAD tool. From the simulations, the parameters like Area, Power, Delay, PDP and EDP were measured and compared with one-bit conventional full subtractor. Among 10T, 14T and 20T one bit full subtractor, the 10T one bit full subtractor is energy and EDP efficient which is shown in table 4.1. Table 4.1 Fig -8: performance analysis of area for various 1-bit full subtractor circuits Fig -9: performance analysis of delay for various 1-bit full subtractor circuits
- 5. International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 06 Issue: 05 | May 2019 www.irjet.net p-ISSN: 2395-0072 © 2019, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 1923 Fig -10: performance analysis of power for various 1-bit full subtractor circuits Fig -11: performance analysis of energy for various 1-bit full subtractor circuits Fig -12: performance analysis of EDP for various 1-bit full subtractor circuits The performance analysis of various one bit full subtractor circuits were shown in figure 8,9,10,11 and 12 in terms of area,delay,power,PDP and EDP respectively. 5. CONCLUSIONS From the results it is clear that, the 10T one bit full subtractor occupies less area in comparison with other counter parts. The power consumption of 10T one bit full subtractoris less in comparison with other counter parts whereas the delay of 10T one bit full subtractor is more when compared to 14T and 20T one bit full subtractor. Therefore, the 10T one bit full subtractorisenergy,EDP, power and area efficient at the cost of delay. REFERENCES [1] Neil Weste and D. Harris, “CMOS VLSI Design: A Circuit and System Perspective,” Pearson Addition Wesley, third Edition, 2005. [2] Ken Martin, Digital Integrated Circuit Design, Oxford University Press, New York, 2000. [3] CMOS Digital Integrated Circuits Analysis and Design Third Edition2003, By Sung-Mo Kang, Yusuf Leblebici. [4] M. Mahaboobbasha, K. Venkataramanaiah, P. Ramana Reddy. “Noval energy efficient one bit full subtractor at 65nm technology”. International conference on electrical, electronics, signals, communication and optimization(EESCO), IEEE, Jan 2015. [5] M. Mahaboobbasha, K. Venkataramanaiah, P. Ramana Reddy, “low area high speed energy efficient one bit full subtractor with MTCMOS”. International Journal of Applied Engineering Research. Volume 10, Number 11 (2015) pp. 27593-27604. [6] Anamika Sharma, Rajesh Mehra “Area Efficient Layout Design & Analysis of Full Subtractor” IJSRET EATHD- 2015 Conference Proceeding, 14-15 March, 2015. [7] Kamal Jeet Singh, Rajesh Mehra “Design &Analysis of Full Subtractor using 10T at 45nm Technology” IJETT, Volume 35 Number 9 - May 2016. [8] M.Mahaboob Basha, Dr. K.Venkata Ramanaiah, Dr. P.Ramana Reddy, Salendra. Govindarajulu.” Novel low Power and high speed array divider in 65nm technology” International Journal ofAdvancesinScience and Technology Vol. 6, No. 6, 2013. [9] B. K. Mohanty and P. K. Meher, "Area–Delay–Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 3, pp. 1042-1050, March 2019. [10] M.Mahaboob Basha, K.Venkata Ramanaiah, P. Ramana Reddy," Design of Near Threshold 10T- Full Subtractor Circuit for Energy Efficient Signal Processing Applications", International Journal of Image, Graphics and Signal Processing(IJIGSP), Vol.9, No.12, pp. 23-29, 2017.DOI: 10.5815/ ijigsp.2017.12.03.