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Parallel Computing

Concepts and Terminologies
Terminologies
โ€ข Task
   โ€“ A logically discrete section of computational work. A task is
     typically a program or program-like set of instructions that is
     executed by a processor.
โ€ข Parallel Task
   โ€“ A task that can be executed by multiple processors safely (yields
     correct results)
โ€ข Serial Execution
   โ€“ Execution of a program sequentially, one statement at a time. In
     the simplest sense, this is what happens on a one processor
     machine. However, virtually all parallel tasks will have sections of
     a parallel program that must be executed serially.
โ€ข Parallel Execution
   โ€“ Execution of a program by more than one task, with each task
     being able to execute the same or different statement at the same
     moment in time.
Terminologies
โ€ข Shared Memory
   โ€“ From a strictly hardware point of view, describes a computer
     architecture where all processors have direct (usually bus based)
     access to common physical memory. In a programming sense, it
     describes a model where parallel tasks all have the same "picture"
     of memory and can directly address and access the same logical
     memory locations regardless of where the physical memory
     actually exists.
โ€ข Distributed Memory
   โ€“ In hardware, refers to network based memory access for physical
     memory that is not common. As a programming model, tasks can
     only logically "see" local machine memory and must use
     communications to access memory on other machines where other
     tasks are executing
Terminologies
โ€ข Communications
   โ€“ Parallel tasks typically need to exchange data. There are several
     ways this can be accomplished, such as through a shared memory
     bus or over a network, however the actual event of data exchange
     is commonly referred to as communications regardless of the
     method employed.
โ€ข Synchronization
   โ€“ The coordination of parallel tasks in real time, very often
     associated with communications. Often implemented by
     establishing a synchronization point within an application where a
     task may not proceed further until another task(s) reaches the same
     or logically equivalent point. Synchronization usually involves
     waiting by at least one task, and can therefore cause a parallel
     application's wall clock execution time to increase
Terminologies
โ€ข Granularity
  โ€“ In parallel computing, granularity is a qualitative
    measure of the ratio of computation to communication.
     โ€ข Coarse: relatively large amounts of computational work are
       done between communication events
     โ€ข Fine: relatively small amounts of computational work are
       done between communication events
โ€ข Observed Speedup
  โ€“ Observed speedup of a code which has been
    parallelized, defined as: wall-clock time of
    serial execution / wall-clock time of
    parallel execution
  โ€“ One of the simplest and most widely used indicators for
von Neumann Architecture
โ€ข For over 40 years, virtually all computers have
  followed a common machine model known as the
  von Neumann computer. Named after the
  Hungarian mathematician John von Neumann.
โ€ข A von Neumann computer uses the stored-
  program concept. The CPU executes a stored
  program that specifies a sequence of read and
  write operations on the memory.
von Neumann Architecture
            โ€ข   Memory is used to store both
                program and data instructions
            โ€ข   Program instructions are coded
                data which tell the computer to
                do something
            โ€ข   Data is simply information to
                be used by the program
            โ€ข   A central processing unit
                (CPU) gets instructions and/or
                data from memory, decodes the
                instructions and then
                sequentially performs them
Flynn's Classical Taxonomy
โ€ข There are different ways to classify parallel
  computers. One of the more widely used
  classifications, in use since 1966, is called Flynn's
  Taxonomy.
โ€ข Flynn's taxonomy distinguishes multi-processor
  computer architectures according to how they can
  be classified along the two independent
  dimensions of Instruction and Data. Each of these
  dimensions can have only one of two possible
  states: Single or Multiple.
Flynn's Classical Taxonomy

โ€ข The matrix below defines the 4 possible
  classifications according to Flynn.


                  โ€ขS I S D                            โ€ขS I M D
      โ€ขSingle Instruction, Single Data   โ€ขSingle Instruction, Multiple Data


                โ€ขM I S D                            โ€ขM I M D
       โ€ขMultiple Instruction, Single      โ€ขMultiple Instruction, Multiple
                   Data                                Data
Single Instruction, Single Data (SISD)
โ€ข A serial (non-parallel) computer
โ€ข Single instruction: only one instruction
  stream is being acted on by the CPU
   during any one clock cycle
โ€ข Single data: only one data stream is
  being used as input during any one
  clock cycle
โ€ข Deterministic execution
โ€ข This is the oldest and until recently, the most
  prevalent form of computer
โ€ข Eg: most PCs, single CPU workstations and
  mainframes
Single Instruction, Multiple Data (SIMD):


โ€ข A type of parallel computer
โ€ข Single instruction: All processing units execute
  the same instruction at any given clock cycle
โ€ข Multiple data: Each processing unit can operate on
  a different data element
โ€ข This type of machine typically has an instruction
  dispatcher, a very high-bandwidth internal
  network, and a very large array of very small-
  capacity instruction units.
Single Instruction, Multiple Data
             (SIMD):
Single Instruction, Multiple Data (SIMD):

โ€ข Best suited for specialized problems characterized by a
  high degree of regularity,such as image processing.
โ€ข Synchronous (lockstep) and deterministic execution
โ€ข Two varieties: Processor Arrays and Vector Pipelines
โ€ข Examples (some extinct):
   o Processor Arrays: Connection Machine CM-2, Maspar MP-1,
     MP-2
   o Vector Pipelines: IBM 9000, Cray C90, Fujitsu VP, NEC SX-2,
     Hitachi S820
Multiple Instruction, Single Data
              (MISD):
โ€ข Few actual examples of this class of parallel
  computer have ever existed
โ€ข Some conceivable examples might be:
  โ€“ multiple frequency filters operating on a single
    signal stream
  โ€“ multiple cryptography algorithms attempting to
    crack a single coded message.
Multiple Instruction, Multiple Data
               (MIMD):
โ€ข Currently, the most common type of parallel computer
โ€ข Multiple Instruction: every processor may be executing a
  different instruction stream
โ€ข Multiple Data: every processor may be working with a
  different data stream
โ€ข Execution can be synchronous or asynchronous,
  deterministic or non- deterministic
โ€ข Examples: most current supercomputers, networked
  parallel computer "grids" and multi-processor SMP
  computers - including some types of PCs.
Multiple Instruction, Multiple Data
              (MIMD):
Lecture 2
scalar

sequential            Lookahead

                               Functional
   I/E overlap                 parallelism

             Multiple
             Func. Units
                                     Pipeline

                    Implicit                 Explicit
                    Vector                   vector

                           Mem-to-Mem             Reg-to-Reg


                                    SIMD                MIMD

Assoc.                 Processor                Multicomputer   Multiprocessor
Processor              Array
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Lecture 2

  • 2. Terminologies โ€ข Task โ€“ A logically discrete section of computational work. A task is typically a program or program-like set of instructions that is executed by a processor. โ€ข Parallel Task โ€“ A task that can be executed by multiple processors safely (yields correct results) โ€ข Serial Execution โ€“ Execution of a program sequentially, one statement at a time. In the simplest sense, this is what happens on a one processor machine. However, virtually all parallel tasks will have sections of a parallel program that must be executed serially. โ€ข Parallel Execution โ€“ Execution of a program by more than one task, with each task being able to execute the same or different statement at the same moment in time.
  • 3. Terminologies โ€ข Shared Memory โ€“ From a strictly hardware point of view, describes a computer architecture where all processors have direct (usually bus based) access to common physical memory. In a programming sense, it describes a model where parallel tasks all have the same "picture" of memory and can directly address and access the same logical memory locations regardless of where the physical memory actually exists. โ€ข Distributed Memory โ€“ In hardware, refers to network based memory access for physical memory that is not common. As a programming model, tasks can only logically "see" local machine memory and must use communications to access memory on other machines where other tasks are executing
  • 4. Terminologies โ€ข Communications โ€“ Parallel tasks typically need to exchange data. There are several ways this can be accomplished, such as through a shared memory bus or over a network, however the actual event of data exchange is commonly referred to as communications regardless of the method employed. โ€ข Synchronization โ€“ The coordination of parallel tasks in real time, very often associated with communications. Often implemented by establishing a synchronization point within an application where a task may not proceed further until another task(s) reaches the same or logically equivalent point. Synchronization usually involves waiting by at least one task, and can therefore cause a parallel application's wall clock execution time to increase
  • 5. Terminologies โ€ข Granularity โ€“ In parallel computing, granularity is a qualitative measure of the ratio of computation to communication. โ€ข Coarse: relatively large amounts of computational work are done between communication events โ€ข Fine: relatively small amounts of computational work are done between communication events โ€ข Observed Speedup โ€“ Observed speedup of a code which has been parallelized, defined as: wall-clock time of serial execution / wall-clock time of parallel execution โ€“ One of the simplest and most widely used indicators for
  • 6. von Neumann Architecture โ€ข For over 40 years, virtually all computers have followed a common machine model known as the von Neumann computer. Named after the Hungarian mathematician John von Neumann. โ€ข A von Neumann computer uses the stored- program concept. The CPU executes a stored program that specifies a sequence of read and write operations on the memory.
  • 7. von Neumann Architecture โ€ข Memory is used to store both program and data instructions โ€ข Program instructions are coded data which tell the computer to do something โ€ข Data is simply information to be used by the program โ€ข A central processing unit (CPU) gets instructions and/or data from memory, decodes the instructions and then sequentially performs them
  • 8. Flynn's Classical Taxonomy โ€ข There are different ways to classify parallel computers. One of the more widely used classifications, in use since 1966, is called Flynn's Taxonomy. โ€ข Flynn's taxonomy distinguishes multi-processor computer architectures according to how they can be classified along the two independent dimensions of Instruction and Data. Each of these dimensions can have only one of two possible states: Single or Multiple.
  • 9. Flynn's Classical Taxonomy โ€ข The matrix below defines the 4 possible classifications according to Flynn. โ€ขS I S D โ€ขS I M D โ€ขSingle Instruction, Single Data โ€ขSingle Instruction, Multiple Data โ€ขM I S D โ€ขM I M D โ€ขMultiple Instruction, Single โ€ขMultiple Instruction, Multiple Data Data
  • 10. Single Instruction, Single Data (SISD) โ€ข A serial (non-parallel) computer โ€ข Single instruction: only one instruction stream is being acted on by the CPU during any one clock cycle โ€ข Single data: only one data stream is being used as input during any one clock cycle โ€ข Deterministic execution โ€ข This is the oldest and until recently, the most prevalent form of computer โ€ข Eg: most PCs, single CPU workstations and mainframes
  • 11. Single Instruction, Multiple Data (SIMD): โ€ข A type of parallel computer โ€ข Single instruction: All processing units execute the same instruction at any given clock cycle โ€ข Multiple data: Each processing unit can operate on a different data element โ€ข This type of machine typically has an instruction dispatcher, a very high-bandwidth internal network, and a very large array of very small- capacity instruction units.
  • 13. Single Instruction, Multiple Data (SIMD): โ€ข Best suited for specialized problems characterized by a high degree of regularity,such as image processing. โ€ข Synchronous (lockstep) and deterministic execution โ€ข Two varieties: Processor Arrays and Vector Pipelines โ€ข Examples (some extinct): o Processor Arrays: Connection Machine CM-2, Maspar MP-1, MP-2 o Vector Pipelines: IBM 9000, Cray C90, Fujitsu VP, NEC SX-2, Hitachi S820
  • 14. Multiple Instruction, Single Data (MISD): โ€ข Few actual examples of this class of parallel computer have ever existed โ€ข Some conceivable examples might be: โ€“ multiple frequency filters operating on a single signal stream โ€“ multiple cryptography algorithms attempting to crack a single coded message.
  • 15. Multiple Instruction, Multiple Data (MIMD): โ€ข Currently, the most common type of parallel computer โ€ข Multiple Instruction: every processor may be executing a different instruction stream โ€ข Multiple Data: every processor may be working with a different data stream โ€ข Execution can be synchronous or asynchronous, deterministic or non- deterministic โ€ข Examples: most current supercomputers, networked parallel computer "grids" and multi-processor SMP computers - including some types of PCs.
  • 18. scalar sequential Lookahead Functional I/E overlap parallelism Multiple Func. Units Pipeline Implicit Explicit Vector vector Mem-to-Mem Reg-to-Reg SIMD MIMD Assoc. Processor Multicomputer Multiprocessor Processor Array