lecture25_fpga-conclude.ppt
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1. The document discusses various topics in VLSI physical design automation including different design styles like FPGA, standard cell, and structured ASIC. 2. It compares the design styles based on factors like cell size, placement, routing, area, performance, and cost. FPGA is described as having fixed and programmable logic and interconnect resources. 3. The document also covers FPGA architecture including logic modules, routing resources, and I/O modules. It describes the physical design process of partitioning, placement, and routing for FPGAs which has different challenges compared to other design styles.
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lecture25_fpga-conclude.ppt
- 1. 1/1/2023 1 VLSI Physical Design Automation Prof. David Pan [email protected] Office: ACES 5.434 Misc. Topics and Conclusion
- 2. 2 1/1/2023 Other Design Styles: FPGA • Field Programmable Gate Array • First introduced by Xilinx in 1984. • Pre-fabricated devices and interconnect, which are programmable by user. • Advantages: – short turnaround time. – low manufacturing cost. – fully testable. – re-programmable. • Particularly suitable for prototyping, low or medium- volume production, device controllers, etc.
- 3. 3 1/1/2023 Comparison of Design Styles Full-Custom Standard Cell Gate Array FPGA Cell size variable fixed height fixed fixed Cell type variable variable fixed programma ble Cell placement variable in row fixed fixed Interconnections variable variable variable programma ble Fabrication layers all layers all layers routing layers only no layers
- 4. 4 1/1/2023 Comparison of Design Styles Full-Custom Standard Cell Gate Array FPGA Area compact compact to moderate moderate large Performance high high to moderate moderate low Design cost high medium medium low Time-to-market long medium medium short
- 5. 5 1/1/2023 Programming Technologies • SRAM to control pass transistor / multiplexer • EPROM – UV light Erasable PROM • EEPROM – Electrically Erasable PROM • Antifuses – One time programmable • They are different in ease of manufacturing, manufacturing reliability, area, ON and OFF resistance, parasitic capacitance, power consumption, re-programmability.
- 6. 6 1/1/2023 Typical FPGA Architecture • Consists of: Logic modules, Routing resources, and I/O modules. Logic Module IO Module Routing Tracks & Switch boxes
- 7. 7 1/1/2023 FPGA Architecture Examples Logic Module Array-based Model Row-based Model Sea-of-Gates Model Hierarchical Model Routing resources overlayed on logic modules
- 8. 8 1/1/2023 Two Types of Logic Modules Look-Up Table (LUT) based: • A block of RAM to store the truth table. • A k-input 1-output functions needs 2k bits. • k is usually 5 or 6. Multiplexer based: e.g., f=ABC+ABC C B A A B f
- 9. 9 1/1/2023 Two Types of Switchboxes • First Type: • Second Type:
- 10. 10 1/1/2023 Several Segmentation Models • Non-Segmentation Model: • Uniform Segmentation Model: 1 4 0 0 2 0 0 3 0 5 0 0 0 0 0 0 0 1 0 0 4 0 2 0 3 0 0 5 Connecting Not connecting 1 4 0 0 2 0 0 3 0 5 0 0 0 0 0 0 0 1 0 0 4 0 2 0 3 0 0 5 Fuse or Programmable switch
- 11. 11 1/1/2023 Several Segmentation Models • Uniform Staggered Segmentation Model: • Non-uniform Staggered Segmentation Model: 1 4 0 0 2 0 0 3 0 5 0 0 0 0 0 0 0 1 0 0 4 0 2 0 3 0 0 5 1 4 0 0 2 0 0 3 0 5 0 0 0 0 0 0 0 1 0 0 4 0 2 0 3 0 0 5
- 12. 12 1/1/2023 Comparison of Segmentation Models • The segmented model provides better utilization of routing resources. • However, segmented model uses more fuses or programmable switches. • The delay of a net is directly proportional to the # of fuses or programmable switches in the route – Manhattan-distance based delay model does NOT work anymore – The segmented model is slower in general
- 13. 13 1/1/2023 Physical Design of FPGAs • Very different from other design styles • Architecture dependent: – LUT or Multiplexer in logic modules – Type of switchboxes used – Type of segmentation model used – ...... • Physical Design: – Partitioning – Floorplanning/Placement – Routing
- 14. 14 1/1/2023 Partitioning • Want to partition the circuit such that each partition (cluster) can be implemented by a logic module. • Also called Clustering. • # of I/O pins, not cluster sizes, is important. (For multiplexer based logic modules, functionality of clusters is also important.) Example: Using 4-LUTs
- 15. 15 1/1/2023 Placement • Assign clusters formed during partitioning to logic modules of FPGA. • The problem is the same as gate-array placement.
- 16. 16 1/1/2023 Routing • Global routing: – Similar to global routing in other design styles. – Minimize wire length and balance densities. • Detailed routing: – Very different from other design styles. – Different algorithms for different segmentation models. – Channels and switchboxes have fixed capacities.
- 17. 17 1/1/2023 Structured ASIC • New buzz word, but essentially gate array – Mask reconfigurable – Not field reconfigurable • Between FPGA and standard cells – Balance delay/performance and mask cost • Only programmable once – by vias (e.g., Via-Programmable Gate Array – VPGA)
- 18. 1/1/2023 18 Physcial Design Automation of MCMs and SiPs
- 19. 19 1/1/2023 MCM and SiP • Multi-Chip Module • System in package (SiP) – Different package styles – Thermal consideration for 3D • Alternative packaging approach for high performance systems. • Similar to PCB and IC layout problems, but – PCB layout tools cannot handle the dense and complex wiring structure of MCM. – IC layout tools cannot handle the complex electrical, thermal and geometrical constraints.
- 20. 20 1/1/2023 Example: Pentium Substrate size: 32mmx32mm Package size: 43mmx43mm (4 times smaller)
- 21. 21 1/1/2023 Partitioning • Partitioning a circuit so that each sub-circuit can be implemented into a chip. • MCM may contain as many as 100 chips. • Need to consider timing constraints and thermal constraints • In addition, also need to consider traditional I/O constraints and area constraints.
- 22. 22 1/1/2023 Placement • # of components is much less as compared to IC placement. • However, need to consider timing constraints and thermal constraints (as bare chips are placed close to each other). • Routing is done in routing layers, not between chips. • So no routing region needs to be allocated.
- 23. 23 1/1/2023 Routing • Main objective is to satisfy timing constraints. • Another objective is to minimize # of routing layers, not to minimize routing area. – Cost is directly proportional to # of layers • Crosstalk, skin effect and parasitic effect are important considerations. • Wires are of smaller pitch and more dense than PCB layout.
- 24. 1/1/2023 24 EE382 V -- Conclusions
- 25. 25 1/1/2023 What Have Been Taught? • Introduced different problems in Physical Design. • Numerous algorithms which are different in terms of – design styles – objectives – constraints – techniques – optimality – efficiency – robustness – .....
- 26. 26 1/1/2023 What Is Important? • Understand the problems – How to formulate the problems, represent the constraints, solutions, etc. – Reasonable assumptions/abstractions • Know fundamental algorithms to solve the problems. • However, the world keeps on changing: – technology – objectives – constraints – requirement on solution quality – computational power • It is more important to learn how to think – formulate the problem – solve it smartly
- 27. 27 1/1/2023 Problem Solving Techniques • Greedy Algorithm • Simulated Annealing/Genetic Algorithm • Mathematical Programming – Linear, Quadratic, Integer Linear, geometric, posynomial, … • Dynamic Programming • Reduction to graph problems – min-cut, max-cut, shortest path, longest path, bipartite matching, minimum spanning tree, etc. • Divide-and-Conquer • Many different heuristics • ....
- 28. 28 1/1/2023 System Specification Micro-Architectural Specification Timing & Relationship Between Units RTL (in HDL) Netlist Architectural Design Functional Design Logic Design Circuit Design VLSI Design Cycle
- 29. 29 1/1/2023 Netlist Layout Mask Packaged Chips Physical Design Fabrication Packaging And Testing VLSI Design Cycle
- 30. 30 1/1/2023 Conventional Physical Design Cycle Partitioning Floorplanning & Placement Routing
- 31. 31 1/1/2023 Technology Trend and Challenges Source: ITRS’03 Interconnect determines the overall performance In addition: noise, power => Design closure Furthermore: manufacturability => Manufacturing closure
- 32. 32 1/1/2023 New Trends in Physical Design • For nanometer IC designs, interconnect dominates • New physical effects – Noise: coupling, P/G noise – Power: leakage, power/voltage islands – Manufacturability: yield, printability – Reliability, … • More and more vertical integration – Logic synthesis coupled with physical design – Interconnect optimizations & design planning – Physical design as a bridge between lower level modeling and higher level optimization/planning • Existing CAD algorithms are far away from optimal
- 33. 33 1/1/2023 Check points Problem solving skills on underlying physical design algorithms Know what’s behind the scene of CAD tools Know the trend and critique ability if given a new research paper Project study of a topic of your choice and implementation (through class project) Presentation skill Paper writing and job preparation