llvm basic porting for risc v

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6https://github.com/lowRISC/riscv-llvm

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class Triple {
public:
enum ArchType {
...,
riscv32, // RISC-V (32-bit): riscv32
riscv64, // RISC-V (64-bit): riscv64
...,
};
...

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RISCVTargetMachine::RISCVTargetMachine(
const Target &T, // riscv32
const Triple &TT, // riscv32---elf
StringRef CPU, // generic-rv32
StringRef FS, // Feature String: +a,+m, …
const TargetOptions &Options, // FloatABIType = FloatABI::Default
Optional<Reloc::Model> RM, // Static, PIC_, etc.
Optional<CodeModel::Model> CM, // Small, Large, Medlow, Medany, Pic
CodeGenOpt::Level OL, // -O0 -O1 -O2 -Os -O3
bool JIT)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
getEffectiveRelocModel(TT, RM),
getEffectiveCodeModel(CM), OL),
TLOF(make_unique<TargetLoweringObjectFileELF>()) {
initAsmInfo();
}

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static std::string computeDataLayout(const Triple &TT) {
if (TT.isArch64Bit()) {
return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
} else {
assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
return "e-m:e-p:32:32-i64:64-n32-S128";
}
}

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------------- Classes -----------------
class ALU<bits<5> ALU:opcode = { ?, ?, ?, ?, ? }, string ALU:op = ?> {
bits<5> Opcode = { ALU:opcode{4}, ALU:opcode{3}, ALU:opcode{2}, ALU:opcode{1},
ALU:opcode{0} };
string Op = ALU:op;
string NAME = ?;
}
------------- Defs -----------------
def ADD { // ALU
bits<5> Opcode = { 1, 0, 1, 0, 1 };
string Op = "add";
string NAME = ?;
}
def SUB { // ALU
bits<5> Opcode = { 1, 0, 1, 1, 1 };
string Op = "sub";
string NAME = ?;
}
class ALU<bits<5> opcode, string op> {
bits<5> Opcode = opcode;
string Op = op;
}
def ADD : ALU<0b10101, "add">;
def SUB : ALU<0b10111, "sub">;

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RISCV.td
Assembler
Disassembler
Compiler

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let Namespace = "RISCV" in {
class RISCVReg<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
let HWEncoding{4-0} = Enc;
let AltNames = alt;
}
def ABIRegAltName : RegAltNameIndex;
} // Namespace = "RISCV"
// Integer registers
let RegAltNameIndices = [ABIRegAltName] in {
// RegNum RegName ABIName
def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>;
def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>;
def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>;
...
def X31 : RISCVReg<31, "x31", ["t6"]>, DwarfRegNum<[31]>;
}
// GPR: {X0, X1, …, X31}
def GPR : RegisterClass< "RISCV", [i32],
32, (add (sequence "X%u", 0, 31))>

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// R-type (e.g. add rd, rs1, rs2) I-type, S-type, etc.
class RVInstR<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, dag outs,
dag ins, string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, []> {
bits<5> rs2; //
bits<5> rs1;
bits<5> rd;
let Inst{31-25} = funct7; //
let Inst{24-20} = rs2;
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
let Opcode = opcode.Value;
}

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include "RISCVInstrFormats.td"
// Instruction Class Templates
class ALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
: RVInstR<funct7, funct3, OPC_OP, (outs GPR:$rd),
(ins GPR:$rs1, GPR:$rs2),
opcodestr, "$rd, $rs1, $rs2">;
def ADD : ALU_rr<0b0000000, 0b000, "add">; // add rd, rs1, rs2

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• $ llvm-tblgen ./RISCV.td -I ../../../include/
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def ADD { // Instruction RVInst RVInstR ALU_rr
field bits<32> Inst = { 0, 0, 0, 0, 0, 0, 0, // funct7
rs2{4}, rs2{3}, rs2{2}, rs2{1}, rs2{0}, // rs2
rs1{4}, rs1{3}, rs1{2}, rs1{1}, rs1{0}, // rs1
0, 0, 0, // funct3
rd{4}, rd{3}, rd{2}, rd{1}, rd{0}, // rd
0, 1, 1, 0, 0, 1, 1 }; // opcode
string Namespace = "RISCV";
dag OutOperandList = (outs GPR:$rd);
dag InOperandList = (ins GPR:$rs1, GPR:$rs2);
string AsmString = "add $rd, $rs1, $rs2"; // AsmParser, InstrPrinter
list<dag> Pattern = []; // pattern
...
int Size = 4; // 4-byte
bit isReturn = 0; // return
bit isBranch = 0; // branch
bits<7> Opcode = { 0, 1, 1, 0, 0, 1, 1 };
bits<5> rs2 = { ?, ?, ?, ?, ? };
bits<5> rs1 = { ?, ?, ?, ?, ? };
bits<5> rd = { ?, ?, ?, ?, ? };
}

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// Callee-save
callee:
sw s0, 12(sp)
...
mv s0, a1 # s0
...
lw s0, 12(sp)
// Caller-save
caller:
sw ra, 12(sp)
...
call callee
...
lw ra, 12(sp)

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// x10(a0) x11(a1)
int add(int a, int b) {
return a + b; // x10(a0)
}
void caller() {
// x10(a0) x11(a1)
int result = add(3, 5);
} // x10(a0)

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• .
// X10 X11
def RetCC_RISCV32 : CallingConv<[CCIfType<[i32], CCAssignToReg<[X10, X11]>>]>;
// RISCV 32-bit C Calling convention.
def CC_RISCV32 : CallingConv<[
// Promote i1/i8/i16 args to i32
CCIfType<[ i1, i8, i16 ], CCPromoteToType<i32>>,
// X10~X17
CCIfType<[i32], CCAssignToReg<[ X10, X11, X12, X13, X14, X15, X16, X17]>>,
// size 4 bytes, alignment 4 bytes
CCAssignToStack<4, 4>
]>;
// Callee-save
def CSR : CalleeSavedRegs<(add X1, X3, X4, X8, X9, (sequence "X%u", 18, 27))>;

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LLVM IR
Map IR instructions
to DAG
SelectionDAGBuilder
Target
Lowering
Instruction
Selection

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a
add
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add

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int add(int a, int b) {
return a + b;
}
define i32 @add(i32 signext %a,
i32 signext %b) #0 {
entry:
%add = add nsw i32 %a, %b
ret i32 %add
}
t0: ch = EntryToken
t4: i32,ch = CopyFromReg t0, Register:i32 %1
t2: i32,ch = CopyFromReg t0, Register:i32 %0
t5: i32 = add nsw t4, t2
t7: ch,glue = CopyToReg t0, Register:i32 %x10_32, t5
t8: ch = RISCVISD::RET_FLAG t7, Register:i32 %x10_32, t7:1

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LLVM IR
Map IR instructions
to DAG
SelectionDAGBuilder
Target
Lowering
Instruction
Selection

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• void setOperationAction(
unsigned Op, // S
MVT VT, //
LegalizeAction Action) // TL Target
// I S
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setOperationAction(ISD::ADD, MVT::i32, Legal)
setOperationAction(ISD::ADD, MVT::i8, Promote)
AddPromotedToType(ISD::ADD, MVT::i8, MVT::i32)
// P T L shift T PC L E
setOperationAction(ISD::MUL, MVT::i32, Expand);
setOperationAction(ISD::GlobalAddress, i32, Custom);

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RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
const RISCVSubtarget &STI)
: TargetLowering(TM), Subtarget(STI) {
// Set up the register classes.
addRegisterClass(MVT::i32, &RISCV::GPRRegClass);
// 32-bit promote 32-bit
// 32-bit 32-bit
computeRegisterProperties(STI.getRegisterInfo());
setStackPointerRegisterToSaveRestore(RISCV::X2);
// TODO: add all necessary setOperationAction calls.
setOperationAction(ISD::MUL, XLenVT, Expand);
...
setOperationAction(ISD::GlobalAddress, i32, Custom);
...
}

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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
bool IsVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
const SDLoc &DL, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const override;
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
SelectionDAG &DAG) const override;
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals) const override;

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LLVM IR
Map IR instructions
to DAG
SelectionDAGBuilder
Target
Lowering
Instruction
Selection

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// RISCVInstrInto.td
def Pat<(add GPR:$rs1, GPR:$rs2), (ADD GPR:$rs1, GPR:$rs2)>;

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def Pat<(add GPR:$rs1, simm12:$imm12), (ADDI GPR:$rs1, simm12:$imm12)>;

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void RISCVDAGToDAGISel::Select(SDNode *Node) {
// If we have a custom node, we have already selected
if (Node->isMachineOpcode()) {
DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "n");
Node->setNodeId(-1);
return;
}
// C
if (Node->getOpcode() == ISD::AND) {
...
return;
}
// A .td pattern
SelectCode(Node);
}
def Pat<(add GPR:$rs1, GPR:$rs2), (ADD GPR:$rs1, GPR:$rs2)>;

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// 3 12-bit sign-extension
def LO12Sext : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(SignExtend64<12>(N->getZExtValue()),
SDLoc(N), N->getValueType(0));
}]>;
// 32-bit 20-bit 11 1 1
def HI20 : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(((N->getZExtValue()+0x800) >> 12) & 0xfffff,
SDLoc(N), N->getValueType(0));
}]>;
def simm32 : ImmLeaf<XLenVT, [{return isInt<32>(Imm);}]>;
// simm12 -> addi rd, x0, simm12
def : Pat<(simm12:$imm), (ADDI X0, simm12:$imm)>;
// simm32 -> lui rd, uimm20 + addi rd, rd, simm12
def : Pat<(simm32:$imm), (ADDI (LUI (HI20 imm:$imm)), (LO12Sext imm:$imm))>;
# 0xabcd5566 a0, simm32 = (uimm20 << 12) + simm12
lui a0, 0xabcd5 # a0 = 0xabcd5
addi a0, a0, 0x566 # a0 = 0xabcd5566

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def : Pat<(load (add GPR:$rs1, simm12:$imm12)), (LW GPR:$rs1, simm12:$imm12)>;
LW rd, rs, simm12

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/// Loads
multiclass LdPat<PatFrag LoadOp, RVInst Inst> {
def : Pat<(LoadOp GPR:$rs1), (Inst GPR:$rs1, 0)>;
def : Pat<(LoadOp (add GPR:$rs1, simm12:$imm12)),
(Inst GPR:$rs1, simm12:$imm12)>;
}
defm : LdPat<sextloadi8, LB>;
defm : LdPat<extloadi8, LB>;
defm : LdPat<sextloadi16, LH>;
defm : LdPat<extloadi16, LH>;
defm : LdPat<load, LW>;
defm : LdPat<zextloadi8, LBU>;
defm : LdPat<zextloadi16, LHU>;
/// Stores
multiclass StPat<PatFrag StoreOp, RVInst Inst> {
def : Pat<(StoreOp GPR:$rs2, GPR:$rs1), (Inst GPR:$rs2, GPR:$rs1, 0)>;
def : Pat<(StoreOp GPR:$rs2, (add GPR:$rs1, simm12:$imm12)),
(Inst GPR:$rs2, GPR:$rs1, simm12:$imm12)>;
}
defm : StPat<truncstorei8, SB>;
defm : StPat<truncstorei16, SH>;
defm : StPat<store, SW>;

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• 4 5 8 7L DLM 9 -42 AI I LM M M C
• 4 5 8 5 I M FIP D . M C
• 4 5 8 5 I M AI O L M C

:
52
@G = global i32 0
define i32 @lw_global(i32 %a) {
%1 = load volatile i32, i32* @G
ret i32 %1
}
lui a0, %hi(G)
addi a0, a0, %lo(G)
lw a0, 0(a0)

3 M CL M
• 4 O M LM 4 5 8 C L M C
• 4 5 8 4 5 8 -0. AD L M C
• 4 5 8 LM E M C
• 4 5 8 I L 4 5 8 1 6 M L M C
• 4 5 8 LD 4 5 8 L 3 L M C
• 4 5 8 4 5 8 LM3 D M LD 1 LL F M M C
• . - 070 1 7
• 4 5 8 F M FIP D IA 5 5-0- 6 M C
• 4 5 8 7L DLM 9 -42 AI I LM M M C
• 4 5 8 5 I M FIP D . M C
• 4 5 8 5 I M AI O L M C

54
define void @condbr(i32 %a, i32 %b, i32 *%c) {
%tst = icmp ne i32 %a, %b
br i1 %tst, label %end, label %equal
equal:
store i32 1, i32* %c
br label %end
end:
ret void
}
def : Pat<(brcond (i32 (setne GPR:$rs1, GPR:$rs2)), bb:$imm12)
(BEQ GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12)>;
BEQ rs1, rs2, simm13_lsb0

3 M CL M
• 4 O M LM 4 5 8 C L M C
• 4 5 8 4 5 8 -0. AD L M C
• 4 5 8 LM E M C
• 4 5 8 I L 4 5 8 1 6 M L M C
• 4 5 8 LD 4 5 8 L 3 L M C
• 4 5 8 4 5 8 LM3 D M LD 1 LL F M M C
• 00 1 1 . . -- 0
• 4 5 8 F M FIP D IA 5 5-0- 6 M C
• 4 5 8 7L DLM 9 -42 AI I LM M M C
• 4 5 8 5 I M FIP D . M C
• 4 5 8 5 I M AI O L M C

• RISCVTargetLowering::LowerCall
• 0
• 7
• 0
56

57
let isCall = 1, Defs=[X1] in
def PseudoCALL : Pseudo<(outs), (ins GPR:$rs1), [(Call GPR:$rs1)]>,
PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>;
lui a0, %hi(external_function)
addi a3, a0, %lo(external_function)
// a0~a7
addi a0, zero, 1
addi a1, zero, 2
addi a2, zero, 3
// /
jalr ra, a3, 0
declare i32 @external_function(i32, i32, i32)
define i32 @test_call_external() nounwind {
%1 = call i32 @external_function(i32 1, i32 2, i32 3)
ret i32 %1
}
JALR rd, rs1, simm12
• target address: rs1 + simm12
• rd = pc + 4

3 M CL M
• 4 O M LM 4 5 8 C L M C
• 4 5 8 4 5 8 -0. AD L M C
• 4 5 8 LM E M C
• 4 5 8 I L 4 5 8 1 6 M L M C
• 4 5 8 LD 4 5 8 L 3 L M C
• 4 5 8 4 5 8 LM3 D M LD 1 LL F M M C
• . . 9 . 0 9-1
• 4 5 8 7L DLM 9 -42 AI I LM M M C
• 4 5 8 5 I M FIP D . M C
• 4 5 8 5 I M AI O L M C

59
:
define i32 @bare_select(i1 %a, i32 %b, i32 %c) {
%1 = select i1 %a, i32 %b, i32 %c
ret i32 %1
}
bare_select:
# %bb.0:
andi a0, a0, 1
addi a3, zero, 0
bne a0, a3, .LBB0_2
# %bb.1:
addi a1, a2, 0
.LBB0_2:
addi a0, a1, 0
jalr zero, ra, 0

3 M CL M
• 4 O M LM 4 5 8 C L M C
• 4 5 8 4 5 8 -0. AD L M C
• 4 5 8 LM E M C
• 4 5 8 I L 4 5 8 1 6 M L M C
• 4 5 8 LD 4 5 8 L 3 L M C
• 4 5 8 4 5 8 LM3 D M LD 1 LL F M M C
• 4 5 8 F M FIP D IA 5 5-0- 6 M C
• 02 02 2- 0 - -0 .
• 4 5 8 7L DLM 9 -42 AI I LM M M C
• 4 5 8 5 I M FIP D . M C
• 4 5 8 5 I M AI O L M C

29 I
• 3 L I 9D 3 4 7 9E I 9
• 3 4 7 3 F EAI AI L 9E AI L AE A C 9 IAE 9
• 3 4 7 3 4 7 -0. AE I 9
• 3 4 7 I 9 E 9
• 3 4 7 9IA 3 4 7 EI .F D9 I EI E F 3 AI 9
• 3 4 7 9 FE I 3 4 7 1 59 I 9
• 3 4 7 9IA 3 4 7 ID29 I 9
• 3 4 7 3 4 7 EI 2 AE 9E 9IA 1 9II D C 9
• 3 4 7 I F F 9CC 37 AEI AFEI 9
• 3 4 7 I F F AI9II D C 9
• 3 4 7 FDDFE A I 9E CF 9 AFEI 9
• 3 4 7 I F F 9 8CC 8 I 8 I 9
• 3 4 7 EA A9C F E I F F 06 F 9 AFEI 9
• 3 4 7 F E I F F D9 A9CAPAE FEI 9E I 9
• 3 4 7 F E I F F D DF F 9 AFEI 9
• 3 4 7 F E I F F D DF F 9 AFEI FE CF 9 9
• 3 4 7 F E F FE A AFE9C 9E I 9
• 3 4 7 4 F F E AFE 9CCI 9
• 3 4 7 D C D E CFM AE F 4 4-0- 5 9
• 3 4 7 4 F 9E I I F 9 L9 A F 9 A AFE9C 9
• 1 0 . - - .2
• 3 4 7 4 F CFM AE . 9D E 9
• 3 4 7 D C D E FCF 9E ACF AEI AFE 9
• 3 4 7 CCFM CFM AE F E9DA 8I 9 9CCF I 9 I9L 9
• 3 4 7 I FD 83 4 7 9CCAE FEL E AFE 9E AD 9
• 3 4 7 4 F F L9 9 I 9
• 3 4 7 4 F I 9 9D I 9E F I I F A I 9
• 3 4 7 9IA I F F AECAE 9ID FEI 9AE I 9
• 3 4 7 I F F CCLD 9D 9 II E9 9
• 3 4 7 D C D E 9E 9E9C IAI 9
addi a1, zero, 0
sub a0, a1, a0
sub a0, zero, a0

3 M CL M
• 4 O M LM 4 5 8 C L M C
• 4 5 8 4 5 8 -0. AD L M C
• 4 5 8 LM E M C
• 4 5 8 I L 4 5 8 1 6 M L M C
• 4 5 8 LD 4 5 8 L 3 L M C
• 4 5 8 4 5 8 LM3 D M LD 1 LL F M M C
• 4 5 8 F M FIP D IA 5 5-0- 6 M C
• 4 5 8 7L DLM 9 -42 AI I LM M M C
• 2 2 . 0 -
• 4 5 8 5 I M AI O L M C

63
// Replace FrameIndex with Offset
void RISCVRegisterInfo::eliminateFrameIndex
// Calculate Offset by FrameIndex
int RISCVFrameLowering::getFrameIndexReference
OffsetHigh Address
Low Address
fp/s0
sp
ra
s0/fp
s1
s2
s3
.
.
.
FrameIndex
0
1
2
3
4
sp + 12
sp + 16
sp + 20
sp + 24
sp + 28

3 M CL M
• 4 O M LM 4 5 8 C L M C
• 4 5 8 4 5 8 -0. AD L M C
• 4 5 8 LM E M C
• 4 5 8 I L 4 5 8 1 6 M L M C
• 4 5 8 LD 4 5 8 L 3 L M C
• 4 5 8 4 5 8 LM3 D M LD 1 LL F M M C
• 4 5 8 F M FIP D IA 5 5-0- 6 M C
• 4 5 8 7L DLM 9 -42 AI I LM M M C
• 4 5 8 5 I M FIP D . M C
• 03 0 3 2 2 3. 2 . .2 3 -
• 4 5 8 5 I M AI O L M C

0 / 0 / ) -/
• /
• I
• ( - ( //
•
• P ( // -
E (
• I
• -/
• ( ( //
- P E
•
•
•
65
func:
// Prologue
addi sp, sp, -32
sw ra, 28(sp)
sw s0/fp, 24(sp)
sw s1, 20(sp)
sw s2, 16(sp)
sw s3, 12(sp)
addi s0/fp, sp, 32
...
// callee-save
// register
...
// Epilog
lw s3, 12(sp)
lw s2, 16(sp)
lw s1, 20(sp)
lw s0/fp, 24(sp)
lw ra, 28(sp)
addi sp, sp, 32
ret

. .
• .
66
void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
...
uint64_t StackSize = MFI.getStackSize();
...
// addi sp, sp, -StackSize
adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup);
...
// addi fp, sp, StackSize
adjustReg(MBB, MBBI, DL, FPReg, SPReg, StackSize, MachineInstr::FrameSetup);
}
void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
...
uint64_t StackSize = MFI.getStackSize();
...
// Deallocate stack: addi sp, sp, StackSize
adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);
}

3 M CL M
• 4 O M LM 4 5 8 C L M C
• 4 5 8 4 5 8 -0. AD L M C
• 4 5 8 LM E M C
• 4 5 8 I L 4 5 8 1 6 M L M C
• 4 5 8 LD 4 5 8 L 3 L M C
• 4 5 8 4 5 8 LM3 D M LD 1 LL F M M C
• 4 5 8 F M FIP D IA 5 5-0- 6 M C
• 4 5 8 7L DLM 9 -42 AI I LM M M C
• 4 5 8 5 I M FIP D . M C
• - . 4 2 2 - 0
• 4 5 8 5 I M AI O L M C

3 M CL M
• 4 O M LM 4 5 8 C L M C
• 4 5 8 4 5 8 -0. AD L M C
• 4 5 8 LM E M C
• 4 5 8 I L 4 5 8 1 6 M L M C
• 4 5 8 LD 4 5 8 L 3 L M C
• 4 5 8 4 5 8 LM3 D M LD 1 LL F M M C
• 4 5 8 F M FIP D IA 5 5-0- 6 M C
• 4 5 8 7L DLM 9 -42 AI I LM M M C
• 4 5 8 5 I M FIP D . M C
• 2 0 . - 0 025 5
• 4 5 8 5 I M AI O L M C

3 M CL M
• 4 O M LM 4 5 8 C L M C
• 4 5 8 4 5 8 -0. AD L M C
• 4 5 8 LM E M C
• 4 5 8 I L 4 5 8 1 6 M L M C
• 4 5 8 LD 4 5 8 L 3 L M C
• 4 5 8 4 5 8 LM3 D M LD 1 LL F M M C
• 4 5 8 F M FIP D IA 5 5-0- 6 M C
• 4 5 8 7L DLM 9 -42 AI I LM M M C
• 4 5 8 5 I M FIP D . M C
• 2..- - 0 .

3 M CL M
• 4 O M LM 4 5 8 C L M C
• 4 5 8 4 5 8 -0. AD L M C
• 4 5 8 LM E M C
• 4 5 8 I L 4 5 8 1 6 M L M C
• 4 5 8 LD 4 5 8 L 3 L M C
• 4 5 8 4 5 8 LM3 D M LD 1 LL F M M C
• 4 5 8 F M FIP D IA 5 5-0- 6 M C
• 4 5 8 7L DLM 9 -42 AI I LM M M C
• 4 5 8 5 I M FIP D . M C
• 4 5 8 5 I M AI O L M C
• 7 . 2-7 3 ..7- 7 0 7

3 M CL M
• 4 O M LM 4 5 8 C L M C
• 4 5 8 4 5 8 -0. AD L M C
• 4 5 8 LM E M C
• 4 5 8 I L 4 5 8 1 6 M L M C
• 4 5 8 LD 4 5 8 L 3 L M C
• 4 5 8 4 5 8 LM3 D M LD 1 LL F M M C
• 4 5 8 F M FIP D IA 5 5-0- 6 M C
• 4 5 8 7L DLM 9 -42 AI I LM M M C
• 4 5 8 5 I M FIP D . M C
• 4 5 8 5 I M AI O L M C
• 0 8 . 0 0 - 2 8 0 8 8

3 M CL M
• 4 O M LM 4 5 8 C L M C
• 4 5 8 4 5 8 -0. AD L M C
• 4 5 8 LM E M C
• 4 5 8 I L 4 5 8 1 6 M L M C
• 4 5 8 LD 4 5 8 L 3 L M C
• 4 5 8 4 5 8 LM3 D M LD 1 LL F M M C
• 4 5 8 F M FIP D IA 5 5-0- 6 M C
• 4 5 8 7L DLM 9 -42 AI I LM M M C
• 4 5 8 5 I M FIP D . M C
• 4 5 8 5 I M AI O L M C
• 2 -2 0 - 0 .

3 M CL M
• 4 O M LM 4 5 8 C L M C
• 4 5 8 4 5 8 -0. AD L M C
• 4 5 8 LM E M C
• 4 5 8 I L 4 5 8 1 6 M L M C
• 4 5 8 LD 4 5 8 L 3 L M C
• 4 5 8 4 5 8 LM3 D M LD 1 LL F M M C
• 4 5 8 F M FIP D IA 5 5-0- 6 M C
• 4 5 8 7L DLM 9 -42 AI I LM M M C
• 4 5 8 5 I M FIP D . M C
• 4 5 8 5 I M AI O L M C
• .0- . 3 - 0 3

: .
• :
• : . :
• : / .
• : / : -: :
•
74

llvm basic porting for risc v

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