5. • Fan in or gate is the number of inputs that can practically be supported
without degrading practically input voltage level.
Fan in = 4
Fan Out
Fan In
Fanout = 4
5
• The maximum number of digital input that the output of a single
logic gate can feed and the gate must be same logic family.
• Fan Out is calculated from the amount of current available in the
output of a gate and the amount of current needed in each input of
the connecting gate.
• It is specified by manufacturer and is provided in the data sheet.
• Exceeding the specified maximum load may lead to misfunctioning
due to deficiency in demanded power.
6. Noise Margin
• Noise is present in all real systems. This
adds random fluctuations to voltages
representing logic levels.
• Small amounts of noise The maximum
noise voltage that can be tolerated by a
circuit is termed its noise immunity (noise
Margin).will not affect the circuit.
• Smaller noise margins mean circuits are
more sensitive to noise.
• the maximum gate input voltage guaranteed
to be recognized as logic 0
• the minimum gate input voltage
guaranteed to be recognized as logic 1
• Similarly
6
NML = VIL – VOL
NMH = VOH V
− IH
9. Transistor as a switch
• A circuit that can turn on/off current in
electrical circuit is referred to a switching
circuit and transistor can be employed
as an electronic switch.
• Cut off region - OFF State
Both junctions are reverse biased,
Ic = 0 and V(BE) < 0.7 v
• Saturation region - ON State
Ic = maximum and V(BE)>0.7 v
9
10. Transistor as SWITCH
• Both the NPN & PNP type bipolar
transistors can be made to operate as
“ON/OFF” type solid state switch by
biasing the transistors.
• COLLECTOR JUNCTION & EMITTER
JUNCTION are Forward biased in ON
transistor.
• COLLECTOR JUNCTION & EMITTER
JUNCTION are Reverse biased in OFF
transistor. This makes a transistor to
behave as a switch.
11. • The input and Base are grounded ( 0v )
• Base-Emitter voltage VBE < 0.7v
• Base-Emitter junction is reverse biased
• Base-Collector junction is reverse
biased
• Transistor is “fully-OFF” ( Cut-off region )
• No Collector current flows ( IC = 0 )
• VOUT = VCE = VCC = “1”
• Transistor operates as an “open switch”
12. • The input and Base are connected
to VCC
• Base-Emitter voltage VBE > 0.7v
• Base-Emitter junction is forward
biased
• Base-Collector junction is forward
biased
• Transistor is “fully-ON” ( saturation
region )
• Max Collector current flows
( IC = Vcc/RL )
• VCE = 0 ( ideal saturation )
• VOUT = VCE = “0”
• Transistor operates as a “closed
13. Advantages of RTL Logic circuit:
The primary advantage of RTL technology was that it
involved a minimum number of transistors, which
was an important consideration before integrated
circuit technology, as transistors were the most
expensive component to produce
Limitations:
The obvious disadvantage of RTL is its high current
dissipation when the transistor conducts to
overdrive the output biasing resistor. This requires
that more current be supplied to and heat be
removed from RTL circuits. In contrast, TTL circuits
minimize both of these requirements.• (NOR GATE USING RTL)
13
14. 14
The basic RTL device is a NOR gate.
The inputs represent either logic level HIGH (1) or LOW (0).
The logic level LOW is the voltage that drives corresponding transistor in cut-off
region, while logic level HIGH drives it into saturation region.
If both the inputs are LOW, then both the transistors are in cut-off i.e. they are
turned-off. Thus, voltage Vcc appears at output I.e. HIGH.
If either transistor or both of them are applied HIGH input, the voltage Vcc drops
across Rc and output is LOW.
Resistor Transistor Logic(RTL)
15. 15
The diode-transistor logic, also termed as DTL, replaced RTL family because of greater fan-out
capability and more noise margin.
DTL circuits mainly consists of diodes and transistors that comprises DTL devices.
The basic DTL device is a NAND gate.
Two inputs to the gate are applied through diodes viz. D1, D2 . The diode will conduct only when
corresponding input is LOW.
If any of the diode is conducting i.e. when at least one input is LOW, the voltage at output keeps
transistor T in cut-off and subsequently, output of transistor is HIGH. If all inputs are HIGH, all
diodes are non-conducting, transistor T is in saturation, and its output is LOW.
.
Diode Transistor Logic
16. (Block Diagram of DTL)
Due to number of
diodes
used in this circuit, the speed
of the circuit is significantly
low. Hence this family of logic
gates is modified to
transistor-transistor logic i.e.
TTL family which has
been discussed on next slide.
(DTL AND GATE) (SATURATING
INVERTER)
D1
16
D2
17. The output impedance is asymmetrical between the high
and low state, making them unsuitable for driving
transmission lines. This drawback is usually overcome by
buffering the outputs with special line-driver devices where
signals need to be sent through cables. ECL, by virtue of its
symmetric low-impedance output structure, does not have
this drawback.
15
( BLOCK DIAGRAM OF TTL)
18. 18
TTL family is a modification to the DTL. It has come to existence so as to
overcome the speed limitations of DTL family. The basic gate of this family is TTL
NAND gate.
Q3 is cutoff (act like a high RC ) when output transistor Q4 is saturated and Q3 is
saturated (act like a low RC ) when output transistor Q4 is cutoff . Thus, one
transistor is ON at one time.
The combination of Q3 and Q4 is called TOTEM POLE arrangement.
Q1 is called input transistor, which is multi emitter transistor, that drive transistor
Q2 which is used to control Q3 and Q4.
Diode D1 and D2 are used to protect Q1 from unwanted negative voltages and
diode D3 ensures when Q4 is ON, Q3 is OFF.
Transistor Transistor Logic
19. 19
ECL logic family implements the gates in differential amplifier configuration in
which transistors are never driven in the saturation region thereby improving
the speed of circuit to a great extent. The ECL family is fastest of all logic
families.
Based on BJT, but removes problems of delay time by preventing the transistors
from saturating.
Very fast operation - propagation delays of 1ns or less.
Low noise immunity of about 0.2-0.25 V .
The input impedance is high and the output impedance is low. As a result,
the transistors change states quickly, gate delays are low, and the fan out
capability is high.
Emitter Coupled Logic
20. (Block Diagram of ECL)
(ECL 2 INPUT OR/NOR GATE)
20
(FUNCTION TABLE) just for study
(LOGIC SYMBOL)
(TRUTH TABLE)
23. NMOS logic – logic function
realization f= A(B+C)
To get the appropriate basic operator, a NOT must follow any naturally-inverting function.
Here is an NMOS implementation, complete with trailing inverter, of the
boolean function a(b+c)
Parallel connection –OR
Series connection- AND
26. 26
Complimentary MOS (CMOS)
Considerably lower energy consumption than TTL and ECL, which has
made portable electronics possible.
Most widely used family for large-scale devices
Combines high speed with low power consumption
Usually operates from a single supply of 5 – 15 V
Excellent noise immunity of about 30% of supply voltage
Can be connected to a large number of gates (about 50) .
28. 28
Switching Circuit and Logic Design by Prof. Indranil Sengupta, IIT KGP
Modern digital Electronics by R P Jain
NPTEL VIDEO by Dr. Amitava Dasgupta, IITM
Logic Families by Dr. Basem Elhalawany
Logic Gates and Family by Dr. A. P. VAJPEYI, IITG
Reference
s
Editor's Notes
#12:Bus architecture
Cache aggregation, compare syllabus, text books, lib stu – comparison with BENCH MARKING SYLLABUS
COURSE PLAN, ASSIGNMENTS/TUTORIALS, CITATIONS FOR ASSIGNEMNT
RASPERRY PIE
