Logic gates and its realization

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Various logic gates are described with their logic symbol, truth table and the same are realized using Every Circuit app.

LOGIC GATES
 Logic gates are the basic building blocks of any digital
system.
 It is an electronic circuit having one or more than one
input and only one output.
 The relationship between the input and the output is
based on a certain logic.
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CLASSIFICATION
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SYMBOLS
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BASIC LOGIC GATES
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AND GATE
 The output of AND gate is high (‘1’) if all of its inputs are
high (‘1’).
 The output of AND gate is low (‘0’) if any one of its inputs
is low (‘0’).
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LOGIC SYMBOL
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TIMING DIAGRAM
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TRUTH TABLE
A B Y = A.B
0 0 0
0 1 0
1 0 0
1 1 1
A B C Y = A.B.C
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
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OR GATE
 The output of OR gate is high (‘1’) if any one of its inputs is
high (‘1’).
 The output of OR gate is low (‘0’) if all of its inputs are low
(‘0’).
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LOGIC SYMBOL
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TIMING DIAGRAM
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TRUTH TABLE
A B Y = A+B
0 0 0
0 1 1
1 0 1
1 1 1
A B C Y =
A+B+C
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
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NOT GATE
 The output of NOT gate is high (‘1’) if its input is low (‘0’).
 The output of NOT gate is low (‘0’) if its input is high (‘1’).
 It is clear that NOT gate simply inverts the given input.
 Since NOT gate simply inverts the given input, therefore it
is also known as Inverter Gate.
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LOGIC SYMBOL
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TIMING DIAGRAM
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TRUTH TABLE
A Y = A’
0
1
1
0
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UNIVERSAL LOGIC GATES
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NAND GATE
 A NAND Gate is constructed by connecting a NOT Gate at
the output terminal of the AND Gate.
 The output of NAND gate is high (‘1’) if at least one of its
inputs is low (‘0’).
 The output of NAND gate is low (‘0’) if all of its inputs are
high (‘1’).
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LOGIC SYMBOL
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TIMING DIAGRAM
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TRUTH TABLE
A B Y =
(A.B)’
0 0 1
0 1 1
1 0 1
1 1 0
A B C Y =
(A.B.C)’
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
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NOR GATE
 A NOR Gate is constructed by connecting a NOT Gate at
the output terminal of the OR Gate.
 The output of OR gate is high (‘1’) if all of its inputs are low
(‘0’).
 The output of OR gate is low (‘0’) if any of its inputs is high
(‘1’).
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LOGIC SYMBOL
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TIMING DIAGRAM
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TRUTH TABLE
A B Y =
(A+B)’
0 0 1
0 1 0
1 0 0
1 1 0
A B C Y =
(A+B+C)’
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
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OTHER LOGIC GATES
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EXOR GATE
 The logic gate which gives high output (i.e., 1) if either
input A or input B but not both are high (i.e. 1) is called
exclusive OR gate or the XOR gate.
 It may be noted that if both the inputs of the XOR gate are
high, then the output is low (i.e., 0).
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LOGIC SYMBOL
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TRUTH TABLE
A B Y =
A ⊕ B
0 0 0
0 1 1
1 0 1
1 1 0
A B C Y =
A ⊕ B ⊕ C
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
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EXNOR GATE
 The logic function implemented by a 2-input Ex-NOR gate
is given as “when both A AND B are the SAME” will give an
output at Q.
 In general, an Exclusive-NOR gate will give an output value
of logic “1” ONLY when there are an EVEN number of 1’s on
the inputs to the gate (the inverse of the Ex-OR gate)
except when all its inputs are “LOW”.
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LOGIC SYMBOL
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TRUTH TABLE
A B Y =
(A ⊕ B)’
0 0 1
0 1 0
1 0 0
1 1 1
A B C Y =
(A ⊕ B ⊕ C)’
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
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LOGIC GATES and THEIR ICs
IC NUMBER NAME OF THE GATE
7400 NAND
7402 NOR
7404 NOT
7408 AND
7432 OR
7486 EXOR/ XOR/ EOR
74266 EXNOR/ XNOR/ ENOR
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Logic gates and its realization

1. LOGIC GATES  Logic gates are the basic building blocks of any digital system.  It is an electronic circuit having one or more than one input and only one output.  The relationship between the input and the output is based on a certain logic. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 1

2. CLASSIFICATION 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 2

3. SYMBOLS 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 3

4. BASIC LOGIC GATES 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 4

5. AND GATE  The output of AND gate is high (‘1’) if all of its inputs are high (‘1’).  The output of AND gate is low (‘0’) if any one of its inputs is low (‘0’). 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 5

6. LOGIC SYMBOL 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 6

7. TIMING DIAGRAM 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 7

8. TRUTH TABLE A B Y = A.B 0 0 0 0 1 0 1 0 0 1 1 1 A B C Y = A.B.C 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 8

9. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 9

10. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 10

11. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 11

12. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 12

13. OR GATE  The output of OR gate is high (‘1’) if any one of its inputs is high (‘1’).  The output of OR gate is low (‘0’) if all of its inputs are low (‘0’). 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 13

14. LOGIC SYMBOL 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 14

15. TIMING DIAGRAM 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 15

16. TRUTH TABLE A B Y = A+B 0 0 0 0 1 1 1 0 1 1 1 1 A B C Y = A+B+C 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 16

17. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 17

18. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 18

19. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 19

20. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 20

21. NOT GATE  The output of NOT gate is high (‘1’) if its input is low (‘0’).  The output of NOT gate is low (‘0’) if its input is high (‘1’).  It is clear that NOT gate simply inverts the given input.  Since NOT gate simply inverts the given input, therefore it is also known as Inverter Gate. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 21

22. LOGIC SYMBOL 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 22

23. TIMING DIAGRAM 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 23

24. TRUTH TABLE A Y = A’ 0 1 1 0 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 24

25. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 25

26. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 26

27. UNIVERSAL LOGIC GATES 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 27

28. NAND GATE  A NAND Gate is constructed by connecting a NOT Gate at the output terminal of the AND Gate.  The output of NAND gate is high (‘1’) if at least one of its inputs is low (‘0’).  The output of NAND gate is low (‘0’) if all of its inputs are high (‘1’). 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 28

29. LOGIC SYMBOL 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 29

30. TIMING DIAGRAM 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 30

31. TRUTH TABLE A B Y = (A.B)’ 0 0 1 0 1 1 1 0 1 1 1 0 A B C Y = (A.B.C)’ 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 31

32. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 32

33. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 33

34. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 34

35. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 35

36. NOR GATE  A NOR Gate is constructed by connecting a NOT Gate at the output terminal of the OR Gate.  The output of OR gate is high (‘1’) if all of its inputs are low (‘0’).  The output of OR gate is low (‘0’) if any of its inputs is high (‘1’). 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 36

37. LOGIC SYMBOL 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 37

38. TIMING DIAGRAM 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 38

39. TRUTH TABLE A B Y = (A+B)’ 0 0 1 0 1 0 1 0 0 1 1 0 A B C Y = (A+B+C)’ 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 39

40. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 40

41. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 41

42. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 42

43. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 43

44. OTHER LOGIC GATES 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 44

45. EXOR GATE  The logic gate which gives high output (i.e., 1) if either input A or input B but not both are high (i.e. 1) is called exclusive OR gate or the XOR gate.  It may be noted that if both the inputs of the XOR gate are high, then the output is low (i.e., 0). 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 45

46. LOGIC SYMBOL 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 46

47. TRUTH TABLE A B Y = A ⊕ B 0 0 0 0 1 1 1 0 1 1 1 0 A B C Y = A ⊕ B ⊕ C 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 47

48. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 48

49. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 49

50. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 50

51. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 51

52. EXNOR GATE  The logic function implemented by a 2-input Ex-NOR gate is given as “when both A AND B are the SAME” will give an output at Q.  In general, an Exclusive-NOR gate will give an output value of logic “1” ONLY when there are an EVEN number of 1’s on the inputs to the gate (the inverse of the Ex-OR gate) except when all its inputs are “LOW”. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 52

53. LOGIC SYMBOL 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 53

54. TRUTH TABLE A B Y = (A ⊕ B)’ 0 0 1 0 1 0 1 0 0 1 1 1 A B C Y = (A ⊕ B ⊕ C)’ 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 54

55. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 55

56. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 56

57. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 57

58. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 58

59. LOGIC GATES and THEIR ICs IC NUMBER NAME OF THE GATE 7400 NAND 7402 NOR 7404 NOT 7408 AND 7432 OR 7486 EXOR/ XOR/ EOR 74266 EXNOR/ XNOR/ ENOR 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 59

60. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 60

61. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 61

62. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 62

63. 09-05-2020 RAMCO INSTITUTE OF TEHNOLOGY 63

Logic gates and its realization

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