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Microchip: CXL Use Cases and Enabling Ecosystem
- 1. A Leading Provider of Smart, Connected and Secure Embedded Control Solutions Microchip Technology Inc. and its subsidiaries © CXL Use Cases and Enabling Ecosystem Super Computing 2023 Sanketh Srinivas, Product Marketing
- 2. Microchip Technology Inc. and its subsidiaries © Agenda • Compute Memory Bottleneck • Heterogenous architectures and Memory Efficiency Plateau • Memory Disaggregation with CXLTM • Memory Tiering with CXL • Memory Tiering with CXL Switch-Attached Memory Expansion • CXL Memory Performance Comparison • Microchip SMC 2000
- 3. Microchip Technology Inc. and its subsidiaries © • CPU vendors are introducing powerful CPUs with higher core counts at a rapid pace • Amount of DDR memory that could be directly attached to CPU is limited due to • Number of parallel DDR interfaces/channels per CPU • Requires large number of IO pins for each memory channel (~300 pins) • Adding more interfaces will impact CPU die and package size Compute Memory Bottleneck Host CPU DDR Memory CORE CORE CORE CORE Parallel DDR Interface CPU to Memory Bottleneck Memory Controller
- 4. Microchip Technology Inc. and its subsidiaries © CPU CPU GPU GPU Accel Accel Heterogeneous Compute Resources Memory and Storage Resources Data Global Data Resources and Generation CPUs, GPUs, Custom Accelerators • Analysis extraction • Medical outcomes • Self-driving vehicles • Filtered and sorting • Data analytics • Cat photos • Time critical data • Stock market decisions • Task Prioritization • Augmented reality • Advertising • Catastrophe avoidance Heterogenous Architectures and Memory Efficiency Plateau
- 5. Microchip Technology Inc. and its subsidiaries © Memory Disaggregation with CXLTM • Lowering pin-count allows expansion • More memory added to support more processor cores • Allow memory pooling and multiple processors to share memory and data more efficiently
- 6. Microchip Technology Inc. and its subsidiaries © Memory Tiering with CXLTM CPU SSD SSD SSD HDD HDD HDD CPU CPU CPU IO Controller I O C T R L M E M C T R L L3 Cache DDR5 DIMMs L1 Cache L2 Cache DDR5 DIMMs CXL Switch DDR5 DIMMs M E M C T R L DDR4 DIMMs Low Latency NAND or PMEM CXL Flash Controller
- 7. Microchip Technology Inc. and its subsidiaries © Fabric-Attached Memory with CXL™
- 8. Microchip Technology Inc. and its subsidiaries © CXL™ Memory Performance Comparison CPU DDR CXL CXL OS 70 ns 30 ns 100 ns 100 ns 100 ns 40 ns 70 ns 150 ns Use-Case Load to Use Direct DDR ~100 ns Direct CXL ~170 ns Pooled CXL ~200 ns Switched CXL ~320 ns Memory Controller DRAM DRAM DRAM 30 ns DRAM DRAM DRAM CXL CXL Multi-head Memory Controller 30 ns DRAM DRAM DRAM Switch 40 ns Memory Controller 30 ns DRAM DRAM DRAM
- 9. Microchip Technology Inc. and its subsidiaries © Microchip SMC 2000 Performance, Resilience and Security
- 10. Microchip Technology Inc. and its subsidiaries © Optically Attached CXLTM Memory Super computing Demo – CXL Booth DDR4 64G DDR4 64G x4 x4 EOM OBO SMC 2000 Maximum CXL Configuration OBO 4 EOM 16 SMC 2000 4 CXL Memory 512 GB DDR5 64G DDR5 64G DDR5 64G DDR5 64G DDR5 64G DDR5 64G DDR5 64G DDR5 64G 512 GB Total 128 GB Total Optical Fiber Lengths (m) 1 3 30
- 11. Microchip Technology Inc. and its subsidiaries © CXLTM Memory Expansion Super computing Demo – MCHP Booth CXL Reference Design SMC 2000 2 CXL Memory 128 GB DDR4 64G DDR4 64G SMC 2000
- 12. Thank You Microchip Technology Inc. and its subsidiaries © Come Visit us at Booth #3200 !
Editor's Notes
- #6: First CXL product, brand new interconnect/protocol, industry transition, first use-case, solving the problem CXL was invented for