Microcontroller architecture
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This document provides an overview of Harvard and Von Neumann architectures, as well as RISC and CISC architectures. It explains that Harvard architecture uses separate memory and buses for instructions and data, allowing simultaneous fetching, while Von Neumann uses a single memory, requiring sequential fetching. It also outlines the key differences between RISC, which uses a small, optimized instruction set, and CISC, which includes more complex, specialized instructions.
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Microcontroller architecture
- 1. COURSE: EMBEDDED SYSTEM TOPIC: MICROCONTROLLER ARCHITECTURE HARVARD/ VON-NEUMANN; RISC/CISC DR. VIKAS J. DONGRE HOD ELECTRONICS &TELECOMMUNICATION GOVERNMENT POLYTECHNIC WASHIM (MS) EMAIL: [email protected] M: 9370668979
- 2. 1.2 Harvard and Von-Neumann architecture. A Basic Computer Model
- 3. Harvard and Von-Neumann architecture. Architecture of a micro computer or a micro controller refers to the arrangement of the CPU with respect of the RAM and ROM. Von-Neumann and Harvard architecture are the two ways through which the micro controller can have its arrangement of the CPU with RAM and ROM.
- 4. Harvard architecture.. In Harvard architecture, the CPU is connected with both the data memory (RAM) and program memory (ROM), separately. It requires more hardware since it will be requiring separate data nd address bus for each memory.. This requires more space. Speed of execution is faster because the processor fetches data and instructions simultaneously It results in wastage of space since if the space is left in the data memory then the instructions memory cannot use the space of the data memory and vice-versa. Controlling becomes complex since data and instructions are to be fetched simultaneously.
- 5. Harvard architecture. Harvard architecture require separate bus for instruction and data. Processor can complete an instruction in one cycle . Easier to pipeline, so high performance can be achieve. Comparatively high cost.
- 6. Von-Neumann architecture.. There is no separate data and program memory. Instead, a single memory connection is given to the CPU. requires less hardware since only a common memory needs to be reached. requires less space. Speed of execution is slower since it cannot fetch the data and instructions at the same time. Space is not wasted because the space of the data memory can be utilized by the instructions memory and vice-versa. Controlling becomes simpler since either data or instructions are to be fetched at a time.
- 7. Von-Neumann architecture.. Von Neumann architecture require only one bus for instruction and data. Processor needs two clock cycles to complete an instruction. Low performance as compared to Harvard architecture. Comparatively low cost.
- 8. RISC AND CISC ARCHITECTURE COMPARISON OF HARVARD AND VON NEUMANN ARCHITECTURE Harvard ◦ Separate memory for Instruction and Data ◦ Requires separate and dedicated bus for instruction and data ◦ Design is completed ◦ Instruction and data can be fetched simultaneously which increases speed ◦ Von Neumann ◦ Single memory for Instruction and Data ◦ Requires separate and dedicated bus for instruction and data ◦ Design is simple ◦ Instruction and data has to be fetched in sequence which reduces speed
- 9. RISC AND CISC ARCHITECTURE
- 11. CISC Architecture : Theory CISC is an acronym for Complex Instruction Set Computer Earliest machines were programmed in assembly language and memory was slow and expensive, CISC make efficient use of memory. Most common microprocessor Intel 80x86 and Motorola 68K series use CISC philosophy. But at present there is vast changes in software and hardware technology . CISC are modified and implemented with other RISC principles. CISC was developed to make compiler development simpler. It tried to reduce burden of generating machine instructions to the processor. Instead of having to make a compiler write long machine instructions to calculate a square-root, a CISC processor itself could do it.
- 12. Attributes of CISC CISC instructions sets some common characteristics: (constraints : small amounts of slow memory, most early machines were programmed in assembly language) A 2-operand format, where instructions have a source and a destination. Register to register, register to memory, and memory to register commands. Multiple addressing modes for memory, including specialized modes for indexing through arrays Variable length instructions where the length often varies according to the addressing mode Instructions which require multiple clock cycles to execute. E.g. Pentium is considered a modern CISC processor
- 13. CISC Disadvantages As the CISC generation processor advanced, the older instruction set and hardware need to be there to support the new version. This increased the complexity . Different instructions will take different amounts of clock time to execute, slowing down the overall performance of the machine. Complex and efficient machine instructions Many specialized instructions aren't used frequently. Relatively fewer registers Extensive Addressing Capabilities for memory operation
- 15. RISC Acronym RISC, or Reduced Instruction Set Computer. Utilizes a small, highly-optimized set of instructions. Instead of highly specialized set of instructions often found in other types of architectures. The first RISC projects came from IBM, Stanford, and UC-Berkeley in the late 70s and early 80s. The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were all designed with a similar philosophy which has become known as RISC. Certain design features have been characteristic of most RISC processors: One cycle execution time: RISC processors have a CPI (clock per instruction) of one cycle. Large number of registers: the RISC design philosophy generally incorporates a larger number of registers to prevent in large amounts of interactions with memory Pipelining: A technique that allows for simultaneous execution of parts, or stages, of instructions to process the instruction efficiently
- 16. Attributes of RISC RISC processors are more or less the opposite of the above: Reduced instruction set. Less complex, simple instructions. Hardwired control unit and machine instructions. Few addressing schemes for memory operands with only two basic instructions, LOAD and STORE Many symmetric registers which are organized into a register file.
- 17. RISC Disadvantages By making the hardware simpler, RISC architectures put a greater burden on the software. Is this worth the trouble because conventional microprocessors are becoming increasingly fast and cheap anyway? CISC and RISC Convergence Because a number of advancements are used by both RISC and CISC processors, the lines between the two architectures have begun to blur. In fact, the two architectures almost seem to have adopted the strategies of the other. Because processor speeds have increased, CISC chips are now able to execute more than one instruction within a single clock. This also allows CISC chips to make use of pipelining. With other technological improvements, it is now possible to fit many more transistors on a single chip.
- 18. CISC versus RISC CISC RISC Emphasis on hardware Emphasis on software Includes multi-clock complex instructions Single-clock,reduced instruction only Memory-to-memory:"LOAD" and "STORE“ incorporated in instructions Register to register: “LOAD" and STORE“ are independent instructions Small code sizes, high cycles per second Low cycles per second, large code sizes Transistors used for storing complex instructions Spends more transistors on memory registers